JP2005150356A - Substrate for electrooptic device, method of manufacturing same, electrooptic device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method by which a substrate for electrooptic device capable of obtaining high reliability can be manufactured at a high yield. <P>SOLUTION: The substrate for electrooptic device is provided with a semiconductor layer 226 formed on a supporting substrate 210 through insulating layers 212 and 216. The method of manufacturing the substrate includes a supporting substrate side forming step including a step of forming the insulating layer 212 on the supporting substrate 210; a semiconductor substrate side forming step including a step of forming a porous layer 236 on the semiconductor layer 226, and a step of forming the insulating layer 216 on the porous layer 236. The method also includes a laminated substrate producing step of laminating the supporting substrate 210 and semiconductor layer 226 to each other so that the formed insulating layers 212 and 216 may become joint surfaces. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a substrate for an electro-optical device having a silicon on insulator (hereinafter abbreviated as “SOI”) structure, a manufacturing method thereof, an electro-optical device, and an electronic apparatus.

  SOI (Silicon On Insulator) technology, which uses a silicon layer on an insulating layer to form semiconductor devices, is achieved with ordinary single crystal silicon substrates such as alpha ray resistance, latch-up characteristics, and short channel suppression effects. In order to exhibit excellent characteristics that cannot be achieved, development of the semiconductor device has been promoted for the purpose of high integration of semiconductor devices.

As a method for forming such an SOI structure (a structure in which a silicon layer is formed over an insulating layer), for example, there is a method by bonding a single crystal silicon substrate. This method, commonly referred to as a bonding method, is a method in which a single crystal silicon substrate including a bonding insulating layer and a supporting substrate are overlapped with each other through an insulating layer, and bonded at room temperature using OH groups on the substrate surface. After that, the single crystal silicon substrate is thinned by grinding, polishing, or etching, and then a siloxane bond (Si—O—Si) is generated by a heat treatment at about 600 ° C. to 1200 ° C. to increase the bonding strength and increase the silicon layer. Is formed on the support substrate. According to this method, since the single crystal silicon substrate is directly thinned, the silicon layer has excellent crystallinity, and therefore, a high-performance semiconductor device can be manufactured. Here, as disclosed in, for example, Patent Document 1, when a semiconductor device having the SOI structure is used in an electro-optical device such as a transmissive liquid crystal device, a translucent substrate such as a quartz substrate is used as a support substrate. Often used.
JP 2002-334994 A

  In the configuration disclosed in Patent Document 1, the thermal expansion coefficient is different between the translucent substrate as the support substrate and the silicon layer, and the step of thinning the single crystal silicon layer and the heat treatment step for improving the bonding strength In such a case, thermal stress is generated due to a difference in thermal expansion coefficient. As a result, slips, dislocations, lattice defects, HF defects, and the like are formed in the silicon layer, which may hinder device characteristics. In particular, the transistors disposed in the pixel portion and the peripheral circuit portion of the electro-optical device are transmission gates, and there is a concern that the breakdown voltage is reduced due to excess carriers generated by latch-up, and the display quality is deteriorated due to Vth shift and variation. . In addition, in the configuration disclosed in Patent Document 1, there is a problem in light shielding properties because there is a distance between the light shielding layer and the silicon layer formed on the back surface side of the semiconductor device.

  The present invention has been made in view of the above problems, and in an electro-optical device substrate having an SOI structure, it is difficult for thermal stress to occur at the bonding interface, resulting in slip, dislocation, and lattice defects. An object of the present invention is to provide a highly reliable substrate for an electro-optical device with few occurrences of HF defects and the like. Another object of the present invention is to provide a manufacturing method capable of simply providing such a substrate for an electro-optical device. Further, a highly reliable electro-optical device including such a substrate for an electro-optical device, The purpose is to provide electronic devices.

  In order to solve the above problems, an electro-optical device substrate according to the present invention is an electro-optical device substrate including a semiconductor layer disposed on a support substrate via an insulating layer, A porous layer is formed between the insulating layer and the insulating layer. According to such an electro-optical device substrate, the porous layer formed between the semiconductor layer and the insulating layer functions as a stress relaxation layer, that is, the coefficient of thermal expansion between the semiconductor layer and the insulating layer. The thermal stress generated by the difference will be relieved. In addition, since light that can enter the semiconductor layer from the insulating layer side can be shielded by the porous layer, it is possible to prevent or suppress the occurrence of light leakage current in the semiconductor layer.

  In the electro-optical device substrate of the present invention, the porous layer may be made of a semiconductor material. By forming a porous layer (semiconductor porous layer) of such a semiconductor material, the stress relaxation function between the semiconductor layer and the insulating layer is further enhanced. In particular, surplus carriers are generated in the semiconductor layer. Even when it occurs, the semiconductor porous layer functions as a recombination center of surplus carriers, and it is possible to prevent a decrease in withstand voltage and Vth shift / variation of an electro-optical device using the substrate.

  The porous layer may be made of the same semiconductor material as the semiconductor layer. By forming such a semiconductor porous layer, the stress relaxation function between the semiconductor layer and the insulating layer is further expressed, and even when surplus carriers are generated particularly in the semiconductor layer, the above semiconductor The porous layer functions as a recombination center of surplus carriers, and it is possible to prevent a decrease in withstand voltage and Vth shift / variation of an electro-optical device using the substrate. Further, when the electro-optical device substrate is manufactured, the structure of the present invention can be easily obtained by making a part of the semiconductor layer porous.

  Further, a light shielding layer may be formed between the porous layer and the support substrate. In this case, since light that can enter the semiconductor layer can be shielded by the porous layer and the light shielding layer, it is possible to prevent or suppress the occurrence of light leakage current in the semiconductor layer.

  The semiconductor layer may be formed directly on the porous layer. In this case, since the semiconductor layer and the porous layer are stacked, the light shielding property to the semiconductor layer is further increased. In addition, by adopting a structure in which a semiconductor layer and a porous layer are laminated in this way, a porous layer can be easily formed, for example, by subjecting the surface layer of the semiconductor layer to a porous treatment by an anodizing method or the like. It becomes.

  Next, in order to solve the above-described problem, the method for manufacturing a substrate for an electro-optical device according to the present invention is a method for manufacturing a substrate for an electro-optical device comprising a semiconductor layer disposed on a support substrate via an insulating layer. A method of forming a support substrate side including a step of forming an insulating layer on the support substrate; and forming a porous layer on the semiconductor substrate to form a stack of the semiconductor layer and the porous layer; A step of forming a semiconductor substrate side including a step of forming an insulating layer on the porous layer, and laminating the supporting substrate and the semiconductor substrate so that the formed insulating layers are bonded to each other. And a substrate generation step. By such a manufacturing method, the above-described electro-optical device substrate can be easily obtained. The supporting substrate side forming step includes a step of forming a light shielding layer in a predetermined region on the supporting substrate and a step of forming the insulating layer so as to cover the supporting substrate and the light shielding layer. It is possible to provide a substrate for an electro-optical device in which a light shielding layer is formed between a quality layer and a supporting substrate.

  In the method for manufacturing a substrate for an electro-optical device of the present invention, the porous layer can be formed by partially making the semiconductor substrate porous by an anodizing method. By making a part of the semiconductor substrate porous by such anodizing method, a porous layer can be easily formed, and a structure in which a semiconductor layer is formed immediately above the porous layer can be obtained. It becomes possible.

  In addition, after producing the bonded substrate, a step of thinning a semiconductor layer of the bonded substrate, a step of patterning the semiconductor layer and the porous layer, and forming a gate insulating layer on the semiconductor layer And a step of forming a gate electrode on the gate insulating layer. A substrate for an electro-optical device obtained by such a manufacturing method is a substrate including a thin film transistor having a semiconductor layer (for example, a single crystal silicon layer) as an active layer, and is suitable as a substrate for an active matrix type electro-optical device. It becomes. Here, for example, in the step of thinning the semiconductor layer, when a method of oxidizing a part of the semiconductor layer and removing the oxide layer is employed, the porous layer prevents oxidation / diffusion of the light shielding layer. The function to suppress will be provided. As a material constituting the light shielding layer of the present invention, for example, a simple substance of a refractory metal such as tungsten, chromium, molybdenum, tantalum, titanium, nitride, oxide, silicide, alloy, or the like can be employed.

  Next, an electro-optical device according to the present invention includes the electro-optical device substrate. Such an electro-optical device has a very high reliability because it hardly generates a light leakage current in the semiconductor layer, hardly causes a decrease in withstand voltage, a Vth shift / variation, and the like. Furthermore, an electronic apparatus according to the present invention includes the electro-optical device as a display unit, for example. In this case, it is possible to provide an electronic device with less occurrence of defects such as display defects.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following drawings, the film thicknesses and dimensional ratios of the respective components are appropriately changed in order to make the drawings easy to see.

(Electro-optical device substrate and manufacturing method thereof)
First, an embodiment of the method for manufacturing a substrate for an electro-optical device according to the present invention will be described with reference to FIGS. 1 to 4 are schematic cross-sectional views showing each manufacturing process of the electro-optical device substrate. First, as shown in FIG. 1A, a single crystal silicon substrate 226 is prepared, and hydrogen ions are implanted therein. As a result, an ion implantation layer having a penetration depth distribution is formed inside the single crystal silicon substrate 226. As ion implantation conditions at this time, for example, acceleration energy is set to 60 keV to 150 keV, and a dose amount is set to 5 × 10 ¹⁶ cm ⁻² to 10 × 10 ¹⁶ cm ⁻² .

  Next, as shown in FIG. 1B, a process for making the surface of the single crystal silicon substrate 226 porous is performed. Specifically, the surface of the single crystal silicon substrate 226 is anodized to change a predetermined thickness from the surface layer of the single crystal silicon substrate 226 to the porous silicon layer 236. Here, conditions for anodizing treatment are set in order to form a porous silicon layer 236 having a thickness of about 100 nm to 400 nm. Note that the anodizing treatment is performed by applying a current in a mixed solution of hydrogen fluoride and ethanol using the single crystal silicon substrate 226 as an anode.

  After the porous treatment, the insulating layer (silicon oxide film) 216 is formed by thermally oxidizing the surface of the porous silicon layer 236 as shown in FIG. Note that the insulating layer 216 is formed to a thickness of about 100 nm to 300 nm. Through the steps as described above, a single crystal semiconductor substrate with an insulating layer (single crystal semiconductor substrate for bonding) 260 including the single crystal silicon substrate (single crystal silicon layer) 226 shown in FIG.

  On the other hand, a support substrate 210 made of a quartz substrate as shown in FIG. 2A is prepared, and a light shielding layer 211 having a predetermined pattern is formed on the support substrate 210. As the support substrate 210, a quartz substrate can be used, and the light shielding layer 211 is obtained by depositing, for example, tungsten silicide to a thickness of about 100 nm to 300 nm, more preferably 200 nm by sputtering.

  The material of the light shielding layer 211 is not limited to this embodiment, and any material can be used as long as it is stable with respect to the maximum thermal process temperature of the device to be manufactured. For example, refractory metals such as chromium, molybdenum, tantalum, titanium, and the like, and oxides, nitrides, silicides, and alloys of these refractory metals are preferably used, and the formation method is other than sputtering using a photomask. The CVD method, the electron beam heating vapor deposition method, or the like can be used. Here, the photomask is formed in the same manner in a region corresponding to a region where a transistor element (TFT) to be described later is formed, as well as in a region where a transistor element is not formed (a peripheral region of the transistor element). The transistor element non-formation region specifically refers to a seal region that is applied in the peripheral region of the transistor element formation region and to which a sealant for laminating a counter substrate is applied, a data line, and a scanning line are driven. A peripheral portion of a driving circuit for performing the operation, a terminal pad region for forming a connection terminal for connecting an input / output signal line, and the like.

  Next, as shown in FIG. 2C, an insulating layer 212 made of, for example, a silicon oxide film is formed by sputtering or the like so as to cover the patterned light shielding layer 211. Such a silicon oxide film may be deposited by a plasma CVD method using TEOS (tetraethylorthosilicate). As the material for the insulating layer 212, in addition to the above-described silicon oxide film, for example, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), etc. Highly insulating glass can be used.

  Next, the surface of the insulating layer 212 is flattened globally under conditions that leave a predetermined film thickness on the light shielding layer 211, for example, so that the layer thickness on the light shielding layer 211 after polishing is about 500 nm to 1000 nm. Turn into. As a planarization method by polishing, for example, a CMP (chemical mechanical polishing) method can be used. In this manner, a support substrate with an insulating layer (supporting substrate for bonding) 270 in which the light shielding layer 211 and the insulating layer 212 are formed on the support substrate 210 is obtained.

  Subsequently, the semiconductor substrate 260 with an insulating layer and the support substrate 210 with an insulating layer obtained as described above are bonded to each other. Specifically, as shown in FIG. 3A, the single crystal semiconductor substrate 260 with an insulating layer shown in FIG. 1C and the supporting substrate 210 with an insulating layer shown in FIG. Bonding is performed at a temperature of about 300 ° C. to 600 ° C. with the insulating layers 216 and 212 facing each other.

  After such a bonding process, the film thickness of the single crystal silicon layer 226 is controlled. In this case, for example, a part of the surface layer of the single crystal silicon layer 226 is oxidized to form a sacrificial oxide layer having a predetermined thickness, and the sacrificial oxide layer is peeled off to form the single crystal silicon layer 226 having a predetermined thickness. Is obtained (FIG. 3B). Note that in this embodiment mode, sacrificial oxidation conditions are set so that the single crystal silicon layer 226 has a thickness of about 30 to 60 nm.

  Next, as shown in FIG. 3C, the porous silicon layer 236 and the single crystal silicon layer 226 are patterned. Here, in order to form an island pattern on the light shielding layer 211, patterning is performed by a photolithography method. Note that the porous silicon layer 236 and the single crystal silicon layer 226 can be separately patterned, that is, after the single crystal silicon layer 226 is patterned, the porous silicon layer 236 can be separately patterned.

  After the porous silicon layer 236 and the single crystal silicon layer 226 are patterned in a predetermined shape as described above, the surfaces of the porous silicon layer 236 and the single crystal silicon layer 226 are thermally oxidized as shown in FIG. Thus, a thermal oxide film 228 is formed on the surface layers of the porous silicon layer 236 and the single crystal silicon layer 226. Further, a high temperature oxide film (HTO film) 229 is formed on the surface layer of the insulating layer 216 including the thermal oxide film 228. The thermal oxide film 228 has a thickness of about 5 nm to 30 nm, and the high temperature oxide film 229 has a thickness of about 50 nm to 100 nm, and these oxide films function as a gate insulating film described later.

  After the formation of the oxide films 228 and 229, a conductive film such as doped polysilicon or a conductive metal film such as aluminum or the like is formed on the single crystal silicon layer 226 via the oxide films 228 and 229. The used multilayer film 227 is formed in a predetermined pattern. Note that the conductive metal film 227 has a thickness of about 300 nm to 500 nm, and this conductive metal film 227 functions as a gate electrode described later.

  The electro-optical device substrate 200 shown in FIG. 4B thus obtained has a single crystal silicon layer 226 as an active layer, and is provided with conductive films disposed via oxide films (gate insulating films) 228 and 229. As a substrate including a thin film transistor (semiconductor element) using the conductive metal film 227 as a gate electrode, the substrate can be applied to an electro-optical device such as a liquid crystal device. Here, the light shielding layer 211 plays a role of shielding light incident on the single crystal silicon layer 226. In addition, the porous silicon layer 236 functions as a stress relaxation layer, that is, relaxes thermal stress that may be generated between the single crystal silicon layer 226 and the insulating layer 216, and further, from the insulating layer 216 side, the single crystal silicon layer It also has a function of shielding light that can enter the H.226. By preventing or suppressing light incidence on the single crystal silicon layer 226 in this manner, generation of light leakage current in the single crystal silicon layer 226 can be prevented or suppressed.

  Further, when the single crystal silicon layer 226 is used as an active layer, even when surplus carriers are generated in the single crystal silicon layer 226, the porous silicon layer 236 can function as a recombination center of surplus carriers. . Accordingly, it is possible to prevent a decrease in withstand voltage and Vth shift / variation of the electro-optical device using the substrate 200. Note that, as described above, the light entry into the single crystal silicon layer 226 is prevented or suppressed by the porous silicon layer 236, and thus the light shielding layer 211 can be omitted as shown in FIG. Simplification of the manufacturing process or simplification of the apparatus can contribute to cost reduction.

(Electro-optical device)
Next, an embodiment of an electro-optical device employing the electro-optical device substrate 200 will be described.
FIG. 6 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms an image forming area (pixel portion or display area) of a liquid crystal device as an electro-optical device. FIG. 7 is an enlarged plan view showing a plurality of pixel groups adjacent to each other on a TFT array substrate (substrate on which TFT elements are formed) on which data lines, scanning lines, pixel electrodes, light shielding films, and the like are formed. is there.
FIG. 8 is a cross-sectional view taken along the line AA ′ of FIG. In FIG. 8, the scales of the respective layers and members are made different from each other in order to make each layer and each member recognizable on the drawing.

  In FIG. 6, a plurality of pixels formed in a matrix form that constitutes an image display area (pixel portion or display area) of the liquid crystal device according to the present embodiment includes a plurality of pixel electrodes 9 a and a pixel electrode 9 a that are formed in a matrix form. The data line 6 a to which an image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. good. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing.

  Image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9a are constant between the counter electrode 21 (see FIG. 8) formed on the counter substrate 20 (see FIG. 8). Hold for a period. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. In the normally white mode, incident light cannot pass through the liquid crystal part according to the applied voltage. In the normally black mode, incident light passes through the liquid crystal part according to the applied voltage. Through the liquid crystal device as a whole, light having a contrast according to the image signal is emitted. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 a and the counter electrode 21. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time when the voltage is applied to the data line. Thereby, the holding characteristics are further improved, and a liquid crystal device with a high contrast ratio can be realized.

Next, the planar structure in the pixel portion of the TFT array substrate (substrate on which the TFT 30 is formed) will be described in detail with reference to FIG. In the liquid crystal device according to the present embodiment, the above-described electro-optical device substrate 200 is used as the TFT array substrate.
As shown in FIG. 7, a plurality of transparent pixel electrodes 9a (outlined by dotted line portions 9a ') are provided in a matrix in the pixel portion on the TFT array substrate of the liquid crystal device. A data line 6a, a scanning line 3a, and a capacitor line 3b are provided along the vertical and horizontal boundaries of the electrode 9a. The data line 6a is electrically connected to a source region described later in the semiconductor layer 1a made of a single crystal silicon layer through the contact hole 5, and the pixel electrode 9a is connected to the source layer in the semiconductor layer 1a through the contact hole 8. It is electrically connected to a drain region described later. In addition, the scanning line 3a is arranged to face the channel region in the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode.

  The capacitor line 3b extends from a portion intersecting the main line portion (that is, the first region formed along the scanning line 3a in plan view) extending along the scanning line 3a and the data line 6a. And a protruding portion (that is, a second region extending along the data line 6 a when viewed in a plan view) that protrudes forward (upward in the drawing) along the data line 6 a.

  A plurality of first light-shielding films 11a corresponding to the light-shielding layer 211 shown in FIG. More specifically, the first light-shielding film 11a is provided at a position that covers the TFT 30 including the channel region of the semiconductor layer 1a in the pixel portion when viewed from the quartz substrate 10A (see FIG. 8) side, and further has a capacitance. A main line portion that extends in a straight line along the scanning line 3a facing the main line portion of the line 3b, and protrudes from a portion intersecting the data line 6a to the adjacent step side (that is, downward in the figure) along the data line 6a. And a protruding portion. The tip of the downward projecting portion in each stage (pixel row) of the first light shielding film 11a overlaps the tip of the upward projecting portion of the capacitor line 3b in the next stage under the data line 6a. A contact hole 13 for electrically connecting the first light-shielding film 11a and the capacitor line 3b to each other is provided at the overlapping portion. In other words, in the present embodiment, the first light shielding film 11 a is electrically connected to the previous-stage or subsequent-stage capacitor line 3 b through the contact hole 13.

  Next, a cross-sectional structure in the pixel portion of the liquid crystal device will be described with reference to FIG. As shown in FIG. 8, the liquid crystal device includes a TFT array substrate 10 and a transparent counter substrate 20 disposed to face the TFT array substrate 10. The TFT array substrate 10 includes a quartz substrate 10A, and the counter substrate 20 includes a glass substrate (or a quartz substrate) 20A. A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 40 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive thin film such as an ITO film (indium tin oxide film). The alignment film 40 is made of an organic thin film such as a polyimide thin film.

  On the other hand, on the counter substrate 20, the second light shielding film 23 is formed in a region facing the formation region of the data line 6 a, the scanning line 3 a, and the pixel switching TFT 30 on the TFT array substrate 10, that is, a region other than the opening region of each pixel portion. Is provided. Further, a counter electrode (common electrode) 21 is provided over the entire surface of the counter substrate 20 including the second light shielding film 23. Similarly to the pixel electrode 9a of the TFT array substrate 10, the counter electrode 21 is also formed of a transparent conductive film such as an ITO film. Due to the presence of the second light shielding film 23, incident light from the counter substrate 20 side does not enter the channel region 1 a ′, the low concentration source region 1 b, or the low concentration drain region 1 c of the semiconductor layer 11 a of the pixel switching TFT 30. Absent. Further, in a display device having a configuration including a color filter, the second light-shielding film 23 can exhibit functions such as an improvement in contrast ratio and prevention of color mixture of color materials, a function as a so-called black matrix. An alignment film 60 is formed on the entire upper surface of the counter electrode 21. The alignment film 60 may be an organic alignment film such as polyimide, or an inorganic alignment film formed by spray deposition of silicon oxide or the like.

  Between the TFT array substrate 10 and the counter substrate 20 arranged so that the pixel electrode 9a and the counter electrode 21 face each other, liquid crystal is sealed in a space surrounded by a seal material (not shown), and the liquid crystal layer 50 Is formed. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 40 and 60 in a state where an electric field from the pixel electrode 9a is not applied. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photocurable resin or a thermosetting resin for bonding the pair of substrates 10 and 20 around them, and is a glass for setting the distance between the two substrates to a predetermined value. Spacers such as fibers or glass beads are mixed.

  The pixel switching TFT 30 disposed on the TFT array substrate 10 has an LDD (Lightly Doped Drain) structure, and the channel of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a. The region 1a ′, the gate insulating film 2 that insulates the scanning line 3a and the semiconductor layer 1a, the data line 6a, the low concentration source region (source side LDD region) 1b and the low concentration drain region (drain side LDD region) of the semiconductor layer 1a 1c, a high concentration source region 1d and a high concentration drain region 1e of the semiconductor layer 1a. A corresponding one of the plurality of pixel electrodes 9a is connected to the high concentration drain region 1e.

  The source regions 1b and 1d and the drain regions 1c and 1e are formed by doping the semiconductor layer 1a with an n-type or p-type dopant having a predetermined concentration depending on whether an n-type or p-type channel is formed. Is formed. An n-type channel TFT has an advantage of high operating speed, and is often used as a pixel switching TFT 30 which is a pixel switching element.

  The data line 6a is composed of a light-shielding thin film such as a metal film such as Al or an alloy film such as metal silicide. On the scanning line 3a, the gate insulating film 2 and the interlayer insulating film 12, an interlayer insulating film 4 in which a contact hole 5 leading to the high concentration source region 1d and a contact hole 8 leading to the high concentration drain region 1e are respectively formed. Is formed. The data line 6a is electrically connected to the high concentration source region 1d through the contact hole 5 to the source region 1b.

  Further, an interlayer insulating film 7 in which a contact hole 8 to the high concentration drain region 1e is formed is formed on the data line 6a and the interlayer insulating film 4. The pixel electrode 9a is electrically connected to the high concentration drain region 1e through the contact hole 8 to the high concentration drain region 1e. The above-described pixel electrode 9a is provided on the upper surface of the interlayer insulating film 7 thus configured. The pixel electrode 9a and the high-concentration drain region 1e may be electrically connected by relaying the same Al film as the data line 6a or the same polysilicon film as the scanning line 3b.

  The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low concentration source region 1b and the low concentration drain region 1c, and the gate electrode 3a is masked. Alternatively, a self-aligned TFT in which impurity ions are implanted at a high concentration to form high concentration source and drain regions in a self-aligning manner may be used.

  On the other hand, the TFT array substrate 10 is provided with a first light-shielding film 11a that shields the pixel switching TFT 30 from the quartz substrate 10A side. Here, the first light-shielding film 11a is preferably made of an opaque high-melting point metal such as tungsten, chromium, molybdenum, tantalum, or titanium, or an oxide, nitride, silicide, alloy, or the like of these high-melting point metals. Can be used. By forming the first light-shielding film 11a as described above on the TFT array substrate 10, the return light from the quartz substrate 10A side is applied to the channel region 1a ′ and the LDD regions 1b and 1c of the pixel switching TFT 30. The incident state can be prevented in advance, and the deterioration of the characteristics of the pixel switching TFT 30 as a transistor element can be prevented or suppressed by the generation of the photocurrent.

  Between the first light-shielding film 11a and the semiconductor layer 1a, as shown in the electro-optical device substrate 200 in FIG. 4, the interlayer insulating film 12 made of insulating layers 212 and 216 (see FIG. 4), and A porous layer 11b made of a porous silicon layer 236 (see FIG. 4) is provided. The interlayer insulating film 12 has a function of electrically insulating the semiconductor layer 1a constituting the pixel switching TFT 30 from the first light shielding film 11a. The porous layer 11b has a function of reducing thermal stress that can occur between the interlayer insulating film 12 and the semiconductor layer 1a, and return light from the quartz substrate 10A is incident on the semiconductor layer 1a. It also has a function to prevent this. Further, even when surplus carriers are generated in the channel region 1a ′ of the semiconductor layer 1a, the porous layer 11b functions as a recombination center of surplus carriers, and prevents a decrease in withstand voltage and Vth shift / variation of the liquid crystal device. It also has a function.

  In the liquid crystal device of this embodiment having such a configuration, the TFT array substrate 10 is manufactured by the above-described manufacturing method of the electro-optical device substrate 200 shown in FIG. That is, the manufacturing method of the liquid crystal device of this embodiment includes at least the following steps. Specifically, the process shown in FIGS. 1 to 3 is used to manufacture a substrate including the semiconductor layer 1a (single crystal silicon layer 226), and the channel region 1a ′ is formed in the semiconductor layer 1a of the substrate. , Low-concentration source region 1b, low-concentration drain region 1c, high-concentration source region 1d, high-concentration drain region 1e, first storage capacitor electrode 1f, scanning line 3a, capacitor line 3b, second interlayer insulating film 4, and data line 6a The third interlayer insulating film 7, the contact hole 8, and the pixel electrode 9a are formed by a method similar to the conventional method (for example, photolithography), and the alignment film 40 is formed on the pixel electrode 9 to manufacture the TFT array substrate 10. And a process of performing. Further, the second light-shielding film 23, the counter electrode 21, and the alignment film 60 are formed on the substrate by the same process to obtain the counter substrate 20, and the TFT array substrate 10 and the counter substrate on which the respective layers are formed as described above. 20 is placed so that the alignment direction of the alignment film intersects (for example, 90 °), and is bonded with a sealant (not shown) so that the cell thickness is, for example, 4 μm, thereby producing an empty panel. As the liquid crystal, TN liquid crystal is used, and this liquid crystal is sealed in a panel to obtain the liquid crystal device of this embodiment.

(Overall configuration of liquid crystal device)
The overall configuration of the liquid crystal device of the present embodiment configured as described above will be described with reference to FIGS. 9 is a plan view of the TFT array substrate 10 as viewed from the side of the counter substrate 20 together with the components formed thereon. FIG. It is H 'sectional drawing.

  In FIG. 9, a sealing material 51 is provided on the TFT array substrate 10 along the edge thereof. In parallel with the inner side of the sealing material 51, for example, as a peripheral parting made of the same or different material as the second light shielding film 23. The second light shielding film 53 is provided. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region outside the sealing material 51, and the scanning line driving circuit 104 has two sides adjacent to the one side. It is provided along.

  Needless to say, when the delay of the scanning signal supplied to the scanning line 3a is not a problem, the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuit 101 may be arranged on both sides along the side of the screen display area. For example, the odd-numbered data lines 6a supply an image signal from a data line driving circuit disposed along one side of the screen display area, and the even-numbered data lines extend along the opposite side of the screen display area. Alternatively, an image signal may be supplied from a data line driving circuit arranged in this manner. If the data lines 6a are driven in a comb-like shape in this way, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be configured.

  Further, on the remaining side of the TFT array substrate 10, a plurality of wirings 105 for connecting the scanning line driving circuits 104 provided on both sides of the screen display area are provided, and further, a second light-shielding as a peripheral parting is provided. A precharge circuit may be provided hidden under the film 53. Further, at least one corner portion of the counter substrate 20 is provided with a conductive material 106 for electrical conduction between the TFT array substrate 10 and the counter substrate 20. As shown in FIG. 10, the counter substrate 20 having substantially the same contour as the sealing material 51 shown in FIG. 9 is fixed to the TFT array substrate 10 by the sealing material 51.

  On the TFT array substrate 10 of the above liquid crystal device, an inspection circuit or the like for inspecting the quality, defects, etc. of the liquid crystal device in the middle of manufacture or at the time of shipment may be further formed. Further, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, a driving LSI mounted on a TAB (tape automated bonding substrate) is connected to the periphery of the TFT array substrate 10. You may make it connect electrically and mechanically through the anisotropic conductive film provided in the area | region. Further, for example, a TN (twisted nematic) mode, an STN (super TN) mode, and a D-STN (dual scan) are respectively provided on the side on which the projection light of the counter substrate 20 enters and the side on which the outgoing light of the TFT array substrate 10 exits. -A polarizing film, a retardation film, a polarizing means, etc. are arranged in a predetermined direction according to the operation mode such as the -STN mode or the normally white mode / normally black mode.

  As described above, in the present embodiment, the liquid crystal device using the liquid crystal as the electro-optical material has been described as one embodiment of the electro-optical device. As the liquid crystal, for example, TN (Twisted Nematic) type, STN (Super Twisted Nematic) type having twisted orientation of 180 ° or more, BTN (Bistable Twisted Nematic) type, ferroelectric type, etc. are bistable. Well-known types can be widely used including molds, polymer dispersion types, guest host types, and the like.

  In addition, the present invention further includes various electro-optical devices using electro-optical materials other than liquid crystals, such as electroluminescence (EL), digital micromirror device (DMD), or fluorescence by plasma emission or electron emission, that is, Needless to say, the present invention can also be applied to organic EL displays, PDPs, FEDs, SEDs, and the like.

(Electronics)
Next, specific examples of the electronic apparatus including the liquid crystal device according to the above embodiment of the present invention will be described.
FIG. 11 is a perspective view showing an example of a mobile phone. In FIG. 11, reference numeral 500 indicates a mobile phone body, and reference numeral 501 indicates a display unit using the liquid crystal device. Since such an electronic device includes the display portion using the liquid crystal device of the above embodiment, it can be provided as a high-quality electronic device including a highly reliable display portion.

  Note that the present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the scope or spirit of the invention that can be read from the claims and the entire specification. A method for manufacturing a substrate for an electro-optical device, a substrate for an electro-optical device, an electro-optical device, and an electronic apparatus are also included in the technical scope of the present invention.

Sectional process drawing which shows the example of 1 process about the manufacturing method of the board | substrate for electro-optical apparatuses. Sectional process drawing which shows the process example following FIG. Sectional process drawing which shows the process example following FIG. Sectional process drawing which shows the process example following FIG. FIG. 6 is a schematic cross-sectional view showing a modification of the electro-optical device substrate. FIG. 2 is an equivalent circuit diagram of a liquid crystal device that is an embodiment of the electro-optical device of the invention. The top view which shows the several pixel group which the TFT array substrate of a liquid crystal device adjoins. Sectional drawing which follows the A-A 'line of FIG. The top view which shows the TFT array substrate of the liquid crystal device of this embodiment with each component formed on it. Sectional drawing which follows the H-H 'line | wire of FIG. FIG. 11 is a perspective view illustrating an embodiment of an electronic apparatus according to the invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 10 ... TFT array substrate, 20 ... Counter substrate, 11a ... 1st light shielding film (light shielding layer), 12 ... Interlayer insulating film (insulating layer), 30 ... TFT, 210 ... Support substrate, 211 ... Light shielding layer 212 ... Insulating layer, 216 ... Insulating layer, 226 ... Single crystal silicon layer (semiconductor layer), 236 ... Porous silicon layer (porous layer)

Claims (11)

An electro-optical device substrate comprising a semiconductor layer disposed on a support substrate via an insulating layer,
A substrate for an electro-optical device, wherein a porous layer is formed between the semiconductor layer and the insulating layer.   2. The electro-optical device substrate according to claim 1, wherein the porous layer is made of a semiconductor material.   3. The electro-optical device substrate according to claim 1, wherein the porous layer is made of the same semiconductor material as that of the semiconductor layer.   4. The electro-optical device substrate according to claim 1, wherein a light shielding layer is formed between the porous layer and the support substrate.   5. The electro-optical device substrate according to claim 1, wherein the semiconductor layer is formed directly on the porous layer. 6. A method for producing a substrate for an electro-optical device comprising a semiconductor layer disposed on a support substrate via an insulating layer,
A supporting substrate side forming step including a step of forming an insulating layer on the supporting substrate;
Forming a porous layer on the semiconductor substrate, forming a stack of the semiconductor layer and the porous layer, and forming a semiconductor substrate side including a step of forming an insulating layer on the porous layer;
A bonded substrate generation step of bonding the support substrate and the semiconductor substrate so that the formed insulating layers are bonded to each other;
A method for manufacturing a substrate for an electro-optical device, comprising:   The support substrate side forming step includes a step of forming a light shielding layer in a predetermined region on the support substrate, and a step of forming the insulating layer so as to cover the support substrate and the light shielding layer. 7. A method for producing a substrate for an electro-optical device according to 6.   8. The method of manufacturing a substrate for an electro-optical device according to claim 6, wherein the step of forming the porous layer is a step of partially forming a surface layer of the semiconductor substrate by an anodizing method. . After producing the bonded substrate,
A step of thinning the semiconductor layer of the bonded substrate;
Patterning the semiconductor layer and the porous layer;
Forming a gate insulating layer on the semiconductor layer;
Forming a gate electrode on the gate insulating layer;
The method for manufacturing a substrate for an electro-optical device according to claim 6, comprising:   An electro-optical device comprising the electro-optical substrate according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 10.

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