JP2005147679A - Semiconductor wafer, and inspection method and inspection device of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve efficiency of IC inspection, to prevent complication of the hardware of an LSI tester, and to reduce inspection cost. <P>SOLUTION: An inspection auxiliary device (BOST unit) used hitherto for inspection of an analog interface-related circuit or the like in an IC after packaging is integrated into this semiconductor wafer 20. A plurality of IC chips 22a-22f and the inspection auxiliary device (integrated BOST unit) 24 integrated into the semiconductor wafer 20 are electrically connected by a wire L, and inspection thereof is performed in a time division system or in a simultaneous system. In order to guarantee accuracy of the inspection auxiliary device 24 as a measuring machine, trimming or the like of the inspection auxiliary device 24 itself is performed as the need arises before inspection of the IC chips. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor wafer, a semiconductor device inspection method, and an inspection apparatus.

  If a complicated IC is inspected only with an LSI tester, the burden on the LSI tester becomes heavy. Therefore, a technique for reducing the burden on the LSI tester by using an inspection auxiliary device is used. There are BIST (Built In Self Test) and BOST (Built Off Self Test) as an inspection method using an auxiliary inspection device. BIST is mainly digital such as a memory or a microprocessor. Used for IC inspection. On the other hand, for example, inspection of analog input / output interface circuits (including A / D converters, D / A converters, high-frequency amplification amplifiers, etc.) mounted on analog / digital mixed ICs is more difficult to handle than digital signals. Since this process involves analog signal processing, an IC chip is cut out from a semiconductor wafer and packaged (or in a bare chip state), and then BOST is used. A test auxiliary device (hereinafter referred to as a “BOST unit”) that performs a BOST test may be built in an LSI tester. However, for the purpose of reducing tester hardware cost, test time, noise, etc. It is often mounted on a tool (test board).

  FIG. 11 is a diagram showing the configuration of an inspection apparatus for BOST. As shown in the figure, an evaluation jig 102 is provided on the LSI tester 101, and a BOST unit (inspection auxiliary device) 104 is mounted on the evaluation jig 102. The BOST unit (inspection auxiliary device) 104 is connected to an IC (in this case, an analog / digital mixed IC) 103 to be inspected via a signal line 110.

  Considering the case where the D / A converter built in the IC 103 is inspected, an analog signal for inspection is given from the BOST unit (inspection auxiliary device) 104, and as a result, the signal output from the IC 103 is sent to the BOST unit 104. The captured signal is converted into a digital signal by an A / D converter (digitizer) built in the BOST unit 104, and then the linearity is inspected. Then, the inspection result (PASS / FAIL) is sent to the LSI tester 101. A method for inspecting an IC after packaging using BOST and a socket used in the method are described in Patent Document 1.

JP 2001-183416 A

  However, since the IC inspection using the BOST unit is performed after the IC chip is cut out from the semiconductor wafer and packaged (or in a bare chip state), a plurality of ICs cannot be inspected collectively. In addition, as a result of the inspection using the BOST unit after dicing or packaging, for example, when a defect in an analog interface-related circuit is found, the IC is discarded as a defective product. Eventually, post-processing of IC manufacturing is wasted. In addition, since a BOST unit (that is, an evaluation jig or the like) is interposed between the LSI tester and the IC to be inspected, an analog signal related to the inspection may be distorted or affected by noise. Further, if it is attempted to improve the inspection efficiency (and inspection accuracy), the hardware of the LSI tester becomes complicated and the cost tends to increase.

  The present invention has been made in view of such points, and a semiconductor wafer capable of improving the efficiency of IC inspection, preventing the complexity of LSI tester hardware, reducing inspection costs, reducing the influence of noise, and the like. An object of the present invention is to provide a semiconductor device inspection method and inspection apparatus.

  A semiconductor wafer according to the present invention includes a plurality of semiconductor chips and at least one inspection auxiliary device for BOST (Built Off Self Test) for inspecting the plurality of semiconductor chips. By incorporating the BOST unit (inspection auxiliary device) on the semiconductor wafer (that is, making the BOST unit BIST), the circuit related to the analog input / output interface is inspected for a plurality of IC chips in the state of the semiconductor wafer. Therefore, the non-defective product / defective product can be selected at the stage of the previous process, and thus the inspection efficiency is remarkably improved. The LSI tester provides information necessary for inspection to the BOST unit (hereinafter referred to as the embedded BOST unit) incorporated in the semiconductor wafer and receives the inspection result, thereby preventing the hardware of the LSI tester from becoming complicated. The inspection cost can be reduced. Further, since the LSI tester and the circuit on the semiconductor wafer are directly connected and no evaluation jig or the like is interposed, distortion of analog signals and noise can be suppressed. In addition, with the recent increase in the diameter of semiconductor wafers, it is expected that variations in yield on a single wafer will become apparent. However, if the semiconductor wafer of the present invention is used, any defective product on the semiconductor wafer is expected. Information on whether or not the position is likely to be generated can be easily acquired, and the information acquired in this way can be used to improve the operating conditions of the manufacturing apparatus and the conditions of the semiconductor manufacturing process.

  According to another aspect of the semiconductor wafer of the present invention, the semiconductor chip includes an analog signal input / output interface circuit, and the inspection auxiliary device includes the analog signal input / output interface mounted on the semiconductor chip. Assist circuit inspection. As a result, it is possible to inspect a circuit related to an analog interface, which is difficult to inspect as compared with a digital circuit, in a wafer state, and thus, the efficiency of inspection is achieved.

  Another aspect of the semiconductor wafer of the present invention includes an analog signal input / output interface circuit that is commonly used for the inspection of the plurality of semiconductor chips, and the semiconductor wafer includes at least one of the plurality of semiconductor chips. Switch means for selectively connecting one to the inspection auxiliary device is provided for each of the plurality of semiconductor chips, and each of the plurality of semiconductor chips is sequentially controlled by the control of the switch means. inspect. Thus, a test can be performed by sequentially connecting one inspection auxiliary device (built-in BOST unit) to a plurality of IC chips.

  In another aspect of the semiconductor wafer of the present invention, the inspection auxiliary device includes an input / output interface circuit corresponding to each of the plurality of semiconductor chips, and the plurality of input / output interface circuits are connected to the plurality of input / output interface circuits. The signal output to each of the semiconductor chips or the signal fetching from each of the plurality of semiconductor chips is performed in a lump. Thereby, one inspection auxiliary device (built-in BOST unit) can be simultaneously connected to a plurality of IC chips and collectively inspected. Therefore, the inspection efficiency is greatly improved.

  In another aspect of the semiconductor wafer of the present invention, each of the plurality of semiconductor chips is arranged around the inspection auxiliary device and the length of each wiring extending from the inspection auxiliary device to each of the plurality of semiconductor chips. It arrange | positions so that the dispersion | variation in thickness may be suppressed. By devising the arrangement of one inspection auxiliary device (built-in BOST unit) and a plurality of IC chips on the semiconductor wafer, variations in the length of the signal path can be suppressed within an allowable range. As a result, it is possible to suppress variations among the IC chips related to signal attenuation (in particular, analog signals), distortion, noise, and the like. This contributes to realization of desired inspection accuracy.

  In another aspect of the semiconductor wafer of the present invention, a plurality of the inspection auxiliary devices are provided on a single semiconductor wafer. By arranging a plurality of inspection auxiliary devices (built-in BOST units) on a single semiconductor wafer and sharing the inspection with each inspection auxiliary device, the inspection can be carried out efficiently without difficulty.

  In another aspect of the semiconductor wafer of the present invention, at least one of the plurality of inspection auxiliary devices is provided in a scribe region of the single semiconductor wafer. The inspection auxiliary device (built-in BOST unit) pays attention to the fact that it is unnecessary after the inspection at the wafer stage is completed, and by providing the inspection auxiliary device in the scribe area which is an empty area on the semiconductor wafer, the dead space is reduced. It can be used effectively. Thereby, it is possible to prevent a decrease in the number (yield) of IC chips that can be obtained from the semiconductor wafer.

  In another aspect of the semiconductor wafer of the present invention, the inspection auxiliary device includes trimming means for maintaining a function as a measuring machine. In order to perform an accurate inspection, first, the accuracy of the inspection auxiliary device itself as a measuring machine must be guaranteed. For example, when inspecting an analog interface circuit mounted on an IC chip, an A / D converter or a D / A converter itself mounted on an inspection auxiliary device (embedded BOST unit) formed on a semiconductor wafer Therefore, prior to the inspection, the A / D converter, the D / A converter, and the like inside the inspection auxiliary device can be trimmed (calibrated). Thereby, it is possible to electrically calibrate the characteristic variation of the elements of the auxiliary inspection device formed on the semiconductor wafer, and therefore it is possible to prevent the inspection accuracy from being lowered.

  In another aspect of the semiconductor wafer of the present invention, when the trimming by the trimming means in the inspection auxiliary device cannot be performed or when the trimming is unsuccessful, a spare for use in place of the inspection auxiliary device is provided. An inspection auxiliary device is further provided. Thereby, even when trimming of the inspection auxiliary device is impossible or unsuccessful, it is possible to switch to the auxiliary inspection auxiliary device and trim and use the auxiliary inspection auxiliary device. That is, the redundancy of the inspection auxiliary device is increased. Therefore, even when one inspection auxiliary device is broken, the situation that the IC chip cannot be inspected does not occur.

  In the semiconductor device inspection method of the present invention, a probe needle of an LSI tester is electrically connected to the inspection auxiliary device on the semiconductor wafer and the semiconductor chip to be inspected. A step of providing a signal to the inspection auxiliary device, and the inspection auxiliary device supplies a signal to each of the plurality of semiconductor chips, and as a result, receives a signal output from each semiconductor chip, and stores the received signal in the memory And the test determination result based on the accumulated signal or the signal itself accumulated in the memory is sent to the LSI tester via the probe needle. As a result, a novel semiconductor device inspection method for efficiently inspecting a plurality of IC chips (particularly, analog interface-related inspection) by directly connecting an LSI tester to a semiconductor wafer is realized.

  Further, the LSI tester of the present invention includes a plurality of probes that are in direct contact with the inspection auxiliary device and the semiconductor chip to be inspected on the one semiconductor wafer for carrying out the semiconductor device inspection method of the present invention. Provide a needle. Thereby, a novel LSI tester having a probe needle for directly and simultaneously contacting a plurality of IC chips on a semiconductor wafer is realized. Data collection or pass / fail judgment, which is the basis of the inspection, is performed by an inspection auxiliary device provided on the semiconductor wafer, thereby reducing the burden on the LSI tester. Therefore, even an LSI tester for large-diameter wafers can suppress an increase in cost.

  According to the present invention, inspection of a circuit related to an analog input / output interface for a plurality of IC chips in the state of a semiconductor wafer is performed by incorporating a BOST inspection auxiliary device (BOST unit) into a semiconductor wafer. Therefore, the non-defective product / defective product can be selected at the stage of the previous process, and the inspection efficiency is remarkably improved. Also, ensure the inspection accuracy by devising the relative positional relationship between the inspection auxiliary device and the IC chip, or by trimming (calibrating) the internal circuit of the inspection auxiliary device and switching to the spare circuit. Can do. Further, the LSI tester only needs to give information necessary for the inspection to the built-in BOST unit and receive the inspection result, so that the hardware of the LSI tester can be prevented from becoming complicated and the inspection cost can be reduced. Further, since the LSI tester and the circuit on the semiconductor wafer are directly connected and no evaluation jig or the like is interposed, distortion of analog signals and noise can be suppressed. In addition, with the recent increase in the diameter of semiconductor wafers, it is expected that variations in yield on a single wafer will become apparent. However, if the semiconductor wafer of the present invention is used, any defective product on the semiconductor wafer is expected. Information about whether or not the position is likely to be generated can be acquired, and the acquired information can be used to improve the operating conditions of the manufacturing apparatus and the conditions of the semiconductor manufacturing process.

(First embodiment)
FIG. 1 is a diagram showing an arrangement and connection relationship between an IC chip and an inspection auxiliary device on a semiconductor wafer placed on a wafer placement table of an LSI tester. As illustrated, the semiconductor wafer 20 is positioned and placed by the positioning plate 10.

  The semiconductor wafer 20 is formed with a plurality of IC chips 22a to 22f to be inspected and an inspection auxiliary device (embedded BOST unit) 24. The IC chips 22a to 22f and the inspection auxiliary device 24 are They are electrically connected by wiring L. The term “IC chip” generally refers to a semiconductor chip that is individualized by dicing, but in this specification, for convenience of explanation, each semiconductor device before dicing formed on a semiconductor wafer is also referred to. , IC chip.

  The inspection auxiliary device 24 performs various digital tests in addition to inspection of analog input / output interface circuit-related circuits (A / D converters, D / A converters, high-frequency amplifiers, etc.) mounted on the IC chips 22a to 22f. Circuit inspection (for example, circuit inspection using a high-speed clock exceeding the frequency of the operation clock of the LSI tester) can also be performed. However, in the following description, a case where a particularly important test relating to an analog input / output interface is performed will be described.

  As a method for inspecting A / D converters and D / A converters mounted on the IC chips 22a to 22f with one inspection auxiliary device 24, the IC chips 22a to 22f are selectively inspected auxiliary devices. 24, there are a method of sequentially inspecting (sequential inspection method) and a method of inspecting each IC chip 22a to 22f in parallel (simultaneous inspection method).

  FIG. 2 is a diagram for explaining a configuration for realizing a method of sequentially inspecting each IC chip. In FIG. 2, only two IC chips 22d and 22e are illustrated for convenience of explanation. As illustrated, the IC chips 22d and 22e are each provided with connection terminals (connection pads) T1 to T3 and T7 to T9. Here, it is assumed that the connection terminals T2 and T8 are inspection pads of D / A converters (not shown in FIG. 2) mounted on the IC chips 22d and 22e.

  Switch means (for example, comprising transfer gates using MOS transistors) 29a, 29c for selecting the IC chip to be inspected between each connection terminal T2, T8 and the inspection auxiliary device (built-in BOST unit) 24 Is intervening. The opening and closing of the switch means 29a, 29c is controlled via the adjacent connection terminals T1, T7 (for example, the probe needle of the probe card built in the LSI tester is brought into contact with the connection terminals T1, T7 to supply power ( When VDD is supplied, the switch means 29a and 29c are thereby closed), so that only one IC chip can be connected to the inspection assistant device 24. Thus, by sequentially switching the switch means, each IC chip can be inspected in a time division manner.

  FIG. 3 is a circuit diagram showing a main circuit configuration in a semiconductor wafer provided with an inspection auxiliary device (built-in BOST unit) and a connection relationship between the semiconductor wafer and a prober (LSI tester). In FIG. 3, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals. As shown in FIG. 3, the semiconductor wafer 20 is formed with IC chips (here, analog / digital mixed ICs) 22d and 22e and an inspection auxiliary device (embedded BOST unit) 24.

  The IC chips (22d, 22e) and the inspection assisting device (built-in BOST unit) 24 include probe needles P1 to P7 (P1, P2, P6, P7) of a prober (an LSI tester and a probe card 210). It is indicated by a thick solid line, and P3 and P4 are indicated by a thick dotted line).

  The inspection auxiliary device (embedded BOST unit) 24 receives instructions from the prober 200, and A / D converters 25a and 25b and D / A converters 23a as analog input / output interface circuits mounted on the IC chips 22d and 22e. , 23b (mainly linearity) is inspected.

  The inspection auxiliary device (built-in BOST unit) 24 includes an A / D converter 30 with a trimming function, a D / A converter 32 with a trimming function, a control circuit 34 that comprehensively controls the operation of each circuit, and measurement data. A memory 36, a data output circuit 38, and a determination unit 40 are provided.

  The trimming function (calibration function) is added to the A / D converter 30 and the D / A converter 32 because of variations in characteristics of circuit elements formed on the semiconductor wafer. This is because the converters 30 and 32 in the inspection auxiliary device 24 can be calibrated first before the inspection of the IC chips 22d and 22e.

  That is, since the inspection auxiliary device (built-in BOST unit) 24 functions as a measuring machine, it is necessary to ensure absolute characteristics and accuracy. However, the inspection auxiliary device 24 that is still formed on the semiconductor wafer 20 may have a defect in characteristics. Therefore, before the IC chip is inspected, the characteristics of the inspection auxiliary device are measured, and trimming is performed as necessary, thereby ensuring the absolute characteristics.

  The specific circuit configuration and trimming operation of the A / D converter 30 with trimming function and the D / A converter 32 with trimming function will be described later with reference to FIGS. Further, in FIG. 3, reference numerals 29a to 29d are switch means for switching the IC chip to be inspected. The switch means 29a includes switches SW1 and SW2 made up of transfer gates. Similarly, the switch unit 29b includes switches SW3 and SW4, the switch unit 29c includes switches SW5 and SW6, and the switch unit 29d includes switches SW7 and SW8.

  The switch means 29a to 29d (switches SW1 to SW8) are driven by pull-down transistors 27a to 27d (denoted as PTR in the figure). For example, when inspecting the D / A converter 23a mounted on the IC chip 22d, the probe needle P1 of the prober 210 built in the prober 200 is connected to the connection terminal T1 of the IC chip 22d, and the probe needle P1 Supply power supply voltage (VDD).

  As a result, the D / A converter 23a of the IC chip 22d becomes operable, and at the same time, the pull-down transistor (PTR) 27a is turned on to drive the switch means 29a, and the switches SW1 and SW2 included in the switch means 29a are closed. . As a result, the D / A converter 23a is connected to the inspection auxiliary device (built-in BOST circuit) and becomes inspectable. Similarly, when inspecting the A / D converter 25a, the switches SW3 and SW4 included in the switch means 29b are closed. The same applies to the inspection of the D / A converter 23b and the A / D converter 25b mounted on the IC chip 22e. In FIG. 3, T <b> 1 to T <b> 19 indicate connection terminals, and L <b> 1 to L <b> 8 indicate wirings for electrically connecting the IC chip (22 d, 22 e) and the inspection auxiliary device (built-in BOST unit) 24.

  Next, the configurations of the A / D converter 30 with trimming function and the D / A converter 32 with trimming function incorporated in the inspection auxiliary device (built-in BOST unit) 24 will be described with reference to FIGS. . FIG. 4 is a block diagram showing a configuration of an A / D converter with a trimming function. This A / D converter is a successive approximation A / D converter. As illustrated, the A / D converter 30 with a trimming function includes a selector 50, a plurality of comparators CMP (1) to CMP (n), and a resistor R1 for generating a reference voltage supplied to these comparators. To Rn, an encoder 52, a latch 54, an error detection circuit 56, a control circuit 58, and a reference voltage selection circuit 60.

  The reference voltage selection circuit 60 is a variable voltage source that can change the output voltage, and receives a command (a plurality of voltages) in the vicinity of the input signal Vref1 that is set in advance in response to an instruction from the control circuit 58. Select and output. When the output voltage of the reference voltage selection circuit 60 changes, the reference voltage supplied to each of the plurality of comparators CMP (1) to CMP (n) changes, and as a result, the A / D conversion output is finely adjusted. .

  The selector 50 serves to selectively supply a normal analog input signal and a calibration reference signal Vref1 to the plurality of comparators CMP (1) to CMP (n). In the trimming (calibration) mode, the calibration reference signal Vref1 is selected. The operation of the selector 50 is controlled by the control circuit 58.

  The encoder 52 encodes each output signal of the plurality of comparators CMP (1) to CMP (n), thereby obtaining an A / D converted digital signal. The error detection circuit 56 detects an A / D conversion error in the trimming (calibration) mode. The control circuit 58 instructs the reference voltage selection circuit 60 to sequentially output a voltage in the vicinity of the input signal Vref1, which is set in advance, in order to reduce the detected error.

  When the output voltage of the reference voltage source 60 changes, the reference voltage supplied to each of the plurality of comparators CMP (1) to CMP (n) changes, and as a result, the A / D conversion output is finely adjusted. Each time the A / D conversion output is finely adjusted, the error detection circuit 56 detects the error, and the control circuit 58 advances the trimming by rotating the calibration loop while watching the detected error. Finally, the output voltage of the reference voltage selection circuit 60 that minimizes the conversion error is determined. In this way, the A / D converter is trimmed.

  FIG. 5 is a block diagram showing the configuration of the D / A converter with trimming function. This D / A converter is a successive approximation D / A converter. As illustrated, the D / A converter 32 with a trimming function includes a decoder 60, ladder resistors (R1 to Rn), switch means 62 (including transfer gates M1 to Mn), and a trimming resistor (RC1). To RC4) and trimming switch means 64 (including switches SW10 to SW13), a pull-down resistor RS, an error detection circuit 66, a selector 68, and a trimming control circuit 70.

  The selector 68 functions to switch between a normal mode (that is, an IC chip inspection mode) and a trimming (calibration) mode, and its operation is controlled by a switching signal. In the trimming mode, the selector 68 supplies the output signal of the error detection circuit 66 to the trimming control circuit 70, and in the normal mode, the D / A conversion output output from the switch means 64 is used as the IC chip to be inspected. This is given to the A / D converter 25a mounted on 22d.

  The decoder 60 decodes the data Din output from the data output circuit 38, and controls the opening and closing of the switches M1 to Mn of the switch means 62 by the decoded output. Thereby, a D / A conversion output is obtained.

  The trimming resistors (RC1 to RC4) are resistors for adjusting the voltage drop amount, and the voltage drop amount is determined depending on which of the four switches (SW10 to SW13) is selected. The trimming control circuit 70 controls opening and closing of the switches (SW10 to SW13). In the trimming mode, a conversion error is detected by the error detection circuit 66, and the detected error amount is sent to the trimming control circuit 70 via the selector 68. The trimming control circuit 70 controls opening and closing of the switches (SW10 to SW13) so that the error is reduced. In this way, the D / A converter 32 is trimmed.

  Next, returning to FIG. 3, the D / A converter (23 a, 23 b) and the A / D converter (25 a) mounted on the IC chip (22 d, 22 e) are used by using the inspection auxiliary device (built-in BOST unit) 24. 25b) will be described. First, probe needles P1 to P2 and P5 to P7 (indicated by thick solid lines in FIG. 3) of a probe card 210 built in the prober 200 are connected to an IC chip 22d formed on the semiconductor wafer 20 and an inspection control device ( The connection terminal (T1, T4, T13, T18, T19) of the built-in BOST unit) 24 is connected. The prober 200 supplies the power supply voltage (VDD) to the IC chip (22d, 22e, etc.) and the inspection auxiliary device 24, and inputs inspection information (upper order command) to the control circuit 34 of the inspection auxiliary device 24.

  Prior to the inspection, first, the performance of the A / D converter 30 with trimming function and the D / A converter 32 with trimming function of the inspection auxiliary device (built-in BOST unit) 24 is checked, and trimming is performed if necessary. The procedure described with reference to FIGS. 3 and 4 is performed. Thereafter, the IC chip 22d is inspected. In the following description, a case where the D / A converter 23a and the A / D converter 25a of the IC chip 22d are inspected will be described.

  In this case, the switch means 29a (switches SW1 and SW2) and the switch means 29b (switches SW3 and SW4) are closed, whereby the IC chip 22d is connected to the inspection auxiliary device (built-in BOST unit) 24. The inspection of the D / A converter 23a in the IC chip 22d is performed as follows.

  That is, data output from the data output circuit 38 of the inspection auxiliary device (built-in BOST unit) 24 is connected to the D / A converter 23a in the IC chip 22d via the connection terminal T15, the wiring L2, the switch SW2, and the connection terminal T3. Given to.

  The conversion output (analog signal) of the D / A converter 23a is A / D converted with a trimming function in the inspection auxiliary device (built-in BOST unit) 24 via the connection terminal T2, the switch SW1, the wiring L1, and the connection terminal T14. Is provided to the container 30. The conversion output (digital signal) of the A / D converter 30 with trimming function is stored in the measurement data memory 36. Then, based on the accumulated data, the determination unit 40 determines pass / fail. The determination result is sent to the probe card 210 mounted on the prober 200 via the connection terminal T18 and the probe needle P6.

  Similarly, the inspection of the A / D converter 25a in the IC chip 22d is performed as follows. That is, data output from the data output circuit 38 of the inspection auxiliary device (built-in BOST unit) 24 is converted into an analog signal by the D / A converter 32 with a trimming function. The converted analog signal is given to the A / D converter 25a in the IC chip 22d through the connection terminal T17, the wiring L4, the switch SW4, and the connection terminal T6.

  The conversion output (digital signal) of the A / D converter 25a is sent to the measurement data memory 36 in the inspection auxiliary device (built-in BOST unit) 24 via the connection terminal T5, the switch SW3, the wiring L3, and the connection terminal T16. Accumulated. Then, based on the accumulated data, the determination unit 40 determines pass / fail. The determination result is sent to the probe card 210 mounted on the prober 200 via the connection terminal T18 and the probe needle P6.

  In the above description, the inspection assisting device (built-in BOST unit) 24 performs the determination of a non-defective product / defective product, but the present invention is not necessarily limited to this. The LSI tester (prober) 200 may perform only data collection related to the IC chip, and calculation, analysis, pass / fail judgment, etc. based on the collected data.

  In this way, by using the inspection auxiliary device (built-in BOST unit) 24 formed on the wafer 20, the D / A converter 23a and the A / D converter 25a mounted on the IC chips 22d and 22e are inspected. Can be done efficiently. That is, by incorporating the BOST unit (inspection auxiliary device) 24 on the semiconductor wafer, it is possible to inspect a circuit related to the analog input / output interface for a plurality of IC chips in the state of the semiconductor wafer. That is, the non-defective product / defective product can be selected at the stage of the previous process, and the inspection efficiency is improved.

  Further, the LSI tester (prober) 200 may provide information necessary for inspection to the inspection auxiliary device (embedded BOST unit) 24 incorporated in the semiconductor wafer 20 and receive the inspection result. Therefore, the LSI tester (prober) ) 200 hardware can be prevented from becoming complicated, and inspection costs can be reduced. Further, since the LSI tester 200 and the circuit (22d, 22e, 24, etc.) on the semiconductor wafer 20 are directly connected without using an evaluation jig or the like, the wiring length is remarkably shortened and the influence of noise is reduced. It becomes less susceptible to distortion of the analog signal. In addition, with the recent increase in the diameter of semiconductor wafers, it is expected that variations in yield on a single wafer will become apparent. However, if the semiconductor wafer 20 of the present invention is used, defective products will be formed on the semiconductor wafer. Information on which position is likely to be generated can be acquired, and the information acquired in this way can be used to improve the operating conditions of the manufacturing apparatus and the conditions of the semiconductor manufacturing process, for example.

  Next, the relative positional relationship (layout on the semiconductor wafer) between the inspection auxiliary device (embedded BOST unit) on the semiconductor wafer and the plurality of IC chips to be inspected will be described with reference to FIG. As shown in FIG. 6, the IC chips 22 a to 22 h are arranged so as to surround the inspection auxiliary device (built-in BOST unit) 24. That is, one inspection auxiliary device is provided for eight IC chips. The inspection is performed in units of these 9 chips. The probe needle for wafer inspection is simultaneously connected to these 9 chips, and the inspection is performed in units of 9 chips.

  With the arrangement as shown in FIG. 6, variations in the length of the wiring to the inspection auxiliary device (built-in BOST unit) 24 and each of the surrounding IC chips 22a to 22h can be minimized. Therefore, the situation that the distortion and noise of the analog signal greatly vary due to the arrangement of the IC chips 22a to 22h does not occur.

(Second Embodiment)
In the first embodiment, a method of sequentially inspecting a plurality of IC chips (sequential inspection method) is adopted, but in this embodiment, a method of simultaneously inspecting a plurality of IC chips (simultaneous inspection method) is adopted. To do. In order to realize the simultaneous inspection method, in this embodiment, a plurality of D / A converters and A / D converters corresponding to each of a plurality of IC chips are mounted on the inspection auxiliary device (built-in BOST unit). Adopt the configuration.

  FIG. 7 is a circuit diagram showing the main circuit configuration of the semiconductor wafer according to the present embodiment and the connection relationship between the semiconductor wafer and a prober (LSI tester). The basic configuration of FIG. 7 is the same as that of FIG. 3, but in FIG. 7, a plurality of D / Ds corresponding to each of the plurality of IC chips (22d, 22e) are added to the inspection auxiliary device (built-in BOST unit) 82. The difference is that A converters (30a, 30b) and A / D converters (32a, 32b) are mounted. Since the basic configuration in FIG. 7 is the same as that in FIG. 3, for convenience of explanation, the description of a part of the configuration is omitted in FIG. 7. Further, in FIG. 7, the same parts as those in FIG.

  In FIG. 7, the A / D converter 30a and the D / A converter 32a in the inspection auxiliary device (built-in BOST unit) 82 are respectively a D / A converter 23a and an A / D converter mounted on the IC chip 22d. It is provided corresponding to the container 25a. The wiring L2 is a wiring for inputting data to the D / A converter 23a mounted on the IC chip 22d, and the wiring L1 outputs an analog signal output from the D / A converter 23a to the inspection auxiliary device. (Built-in BOST unit) Wiring for transmitting to the A / D converter 30a in the 82. The wiring L4 is a wiring for inputting an analog signal to the A / D converter 25a mounted on the IC chip 22d, and the wiring L3 converts the digital signal output from the A / D converter 25a into an inspection auxiliary device. This is a wiring for transmitting to the measurement data memory 36 in the (embedded BOST unit) 82.

  Similarly, the A / D converter 30b and the D / A converter 32b in the inspection auxiliary device (built-in BOST unit) 82 are respectively a D / A converter 23b and an A / D converter mounted on the IC chip 22e. 25b is provided. The wiring L11 is a wiring for inputting data to the D / A converter 23b mounted on the IC chip 22e, and the wiring L10 outputs an analog signal output from the D / A converter 23b to the inspection auxiliary device. (Built-in BOST unit) Wiring for transmitting to the A / D converter 30b in the 82. The wiring L12 is a wiring for inputting an analog signal to the A / D converter 25b mounted on the IC chip 22e, and the wiring L13 converts the digital signal output from the A / D converter 25b to the inspection auxiliary device. This is a wiring for transmitting to the measurement data memory 36 in the (embedded BOST unit) 82.

  Thus, the D / A converter mounted on the IC chip to be inspected, the A / D converter corresponding to the A / D converter, and the D / A converter are provided in the inspection auxiliary device 82. In addition, by providing wirings for transmitting inspection signals independently, signals are input in parallel to a plurality of inspection objects, and as a result, signals output from the inspection objects are simultaneously collected in the measurement data memory 36. be able to. Therefore, based on the collected data, the determination unit 40 can simultaneously determine pass / fail for each inspection target. In addition, the determination part 40 can also perform quality determination about each test object sequentially (that is, by time division). Thus, simultaneous inspection of a plurality of IC chips is realized, so that inspection efficiency is remarkably improved.

(Third embodiment)
FIG. 8 is a diagram showing the arrangement of the inspection auxiliary device and the IC chip in the semiconductor wafer provided with a plurality of inspection auxiliary devices. As illustrated, the plurality of auxiliary inspection devices 82 a to 82 e are distributed on the semiconductor wafer 20. Then, IC chips C1 to C28 are provided around the inspection auxiliary devices 82a to 82e. Although it is not impossible to inspect all IC chips with one inspection auxiliary device, this is a physical limitation in producing a wafer inspection probe card (reference numeral 210 in FIGS. 3 and 7). May become apparent, and the burden on the inspection assisting device also increases. Therefore, by providing a plurality of inspection auxiliary devices on one semiconductor wafer, it is possible to efficiently and efficiently inspect a large number of IC chips.

(Fourth embodiment)
FIG. 9 is a diagram showing an arrangement of the inspection auxiliary device and the IC chip in the semiconductor wafer in which a plurality of inspection auxiliary devices are provided in the scribe region. In the figure, SCL1 to SCL4 indicate scribe areas. The plurality of auxiliary examination devices 84a to 84l are provided in these scribe areas (SCL1 to SCL4). Paying attention to the point that the inspection auxiliary device becomes unnecessary after the inspection at the wafer stage is completed, the dead space can be effectively used by arranging the inspection auxiliary device in the scribe region. Thereby, it is possible to prevent a decrease in the number of IC chips that can be obtained from one semiconductor wafer (that is, a decrease in yield).

(Fifth embodiment)
In the present embodiment, when the inspection auxiliary device formed on the semiconductor wafer is broken and cannot be trimmed, or when the characteristics cannot be improved by the trimming, it is possible to switch to the auxiliary inspection auxiliary device.

  FIG. 10 is a diagram showing the arrangement and connection relationship between the IC chip and the inspection auxiliary device in the semiconductor wafer. 10 differs from FIG. 1 in that, in addition to the regular inspection assistance device (built-in BOST unit) 24, spare inspection assistance devices 90a and 90b are provided, and regular inspection assistance is performed by operating the switches SW20 to SW22. Instead of the device 24, a redundant configuration that can use spare inspection auxiliary devices 90a and 90b is employed. Since the inspection auxiliary device 24 functions as a measuring machine, it is necessary to prevent a situation in which the IC chip cannot be inspected even when the inspection auxiliary device itself is broken or trimming ends abnormally.

  Therefore, in the present embodiment, spare inspection auxiliary devices 90a and 90b are provided to provide redundancy, and when the normal inspection auxiliary device 24 cannot be used, the switch SW20 is opened, and the switches SW21 and SW22 are turned on. One of them is closed, and any one of the auxiliary inspection auxiliary devices 90a and 90b is connected to the wiring L to be usable. The preliminary inspection auxiliary device (any of 90a and 90b) connected to the wiring L is trimmed if necessary, and then the IC chips 22a to 22f are inspected. A fuse cutting method can be used instead of the open / close control by the switches SW20 to SW22.

  As described above, in the present invention, a conventional BOST unit is taken into a semiconductor wafer, and a plurality of IC chips formed on the semiconductor wafer by performing trimming adjustment and switching to a preliminary inspection auxiliary device as necessary. Sequential or simultaneous inspection will be conducted. Therefore, it is possible to perform an inspection using a BOST unit, which has conventionally only been inspected after packaging, in a wafer state.

  According to the present invention, a plurality of IC chips can be inspected at the same time, which is not possible in the inspection after packaging. As a result, it is possible to realize a marked improvement in inspection efficiency, a reduction in hardware cost of the LSI tester, a reduction in test time, a reduction in the influence of noise on signals used for inspection, and the like.

  Specifically, the following effects can be obtained. In other words, in the state of the semiconductor wafer, it is possible to inspect circuits related to the analog input / output interface for a plurality of IC chips, and therefore, it is possible to select non-defective / defective products at the stage of the previous process, Inspection efficiency is improved.

  Also, ensure the inspection accuracy by devising the relative positional relationship between the inspection auxiliary device and the IC chip, or by trimming (calibrating) the internal circuit of the inspection auxiliary device and switching to the spare circuit. Can do. Further, the LSI tester only needs to give information necessary for the inspection to the built-in BOST unit and receive the inspection result, so that the hardware of the LSI tester can be prevented from becoming complicated and the inspection cost can be reduced. Further, since the LSI tester and the circuit on the semiconductor wafer are directly connected and no evaluation jig or the like is interposed, distortion of analog signals and noise can be suppressed. In addition, with the recent increase in the diameter of semiconductor wafers, it is expected that variations in yield on a single wafer will become apparent. However, if the semiconductor wafer of the present invention is used, any defective product on the semiconductor wafer is expected. Information about whether or not the position is likely to be generated can be acquired, and the acquired information can be used to improve the operating conditions of the manufacturing apparatus and the conditions of the semiconductor manufacturing process. Therefore, it becomes easy to cope with an increase in the diameter of the semiconductor wafer.

  The semiconductor wafer, the semiconductor device inspection method and the inspection apparatus according to the present invention include analog input / output for a plurality of IC chips in the state of a semiconductor wafer by incorporating a BOST inspection auxiliary device (BOST unit) into the semiconductor wafer. It is possible to inspect circuits and the like related to the interface. Therefore, it is possible to select non-defective / defective products at the stage of the previous process, and there is an effect that the inspection efficiency is remarkably improved. It is useful as a semiconductor device inspection method and inspection apparatus.

The figure which shows the arrangement | positioning and connection relation of an IC chip and an inspection auxiliary device in the semiconductor wafer mounted on the wafer mounting table of the LSI tester The figure for demonstrating the structure for implement | achieving the system which test | inspects each IC chip sequentially. The circuit diagram which shows the main circuit structure in a semiconductor wafer provided with an inspection auxiliary device (built-in BOST unit), and the connection relation between a semiconductor wafer and a prober (LSI tester) Block diagram showing configuration of A / D converter with trimming function Block diagram showing configuration of D / A converter with trimming function The figure which shows the relative positional relationship (layout on a semiconductor wafer) with the test | inspection auxiliary | assistance apparatus (built-in BOST unit) on a semiconductor wafer, and several IC chip to be tested. The circuit diagram which shows the main circuit structure in the semiconductor wafer concerning this embodiment, and the connection relation of a semiconductor wafer and a prober (LSI tester) The figure which shows arrangement | positioning of an inspection auxiliary device and an IC chip in a semiconductor wafer provided with a plurality of inspection auxiliary devices The figure which shows arrangement | positioning of an inspection auxiliary device and an IC chip in a semiconductor wafer provided with a plurality of inspection auxiliary devices in a scribe region The figure which shows the arrangement and connection relation of IC chip and inspection auxiliary device in the semiconductor wafer The figure which shows the structural example of the inspection apparatus for conventional BOST.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Positioning plate 20 Semiconductor wafer 22a-22f Semiconductor chip 24 Inspection auxiliary | assistance apparatus (built-in BOST unit)

Claims (11)

  A semiconductor wafer comprising a plurality of semiconductor chips and at least one inspection assistance device for BOST (Built Off Self Test) for inspecting the plurality of semiconductor chips. The semiconductor wafer according to claim 1,
The semiconductor chip is equipped with an analog signal input / output interface circuit, and the inspection auxiliary device is a semiconductor wafer for assisting the inspection of the analog signal input / output interface circuit mounted on the semiconductor chip. A semiconductor wafer according to claim 1 or 2, wherein
The inspection auxiliary device includes an analog signal input / output interface circuit that is commonly used for inspection of the plurality of semiconductor chips, and selectively inspects at least one of the plurality of semiconductor chips on the semiconductor wafer. A semiconductor wafer, wherein a switch means for connecting to an auxiliary device is provided for each of the plurality of semiconductor chips, and each of the plurality of semiconductor chips is sequentially inspected by the control of the switch means. A semiconductor wafer according to claim 1 or 2, wherein
The inspection auxiliary device includes an input / output interface circuit corresponding to each of the plurality of semiconductor chips, and through each of the input / output interface circuits, a signal output to each of the plurality of semiconductor chips, or the plurality of the plurality of semiconductor chips. A semiconductor wafer that collectively collects signals from each of the semiconductor chips. A semiconductor wafer according to claim 3 or 4, wherein
Each of the plurality of semiconductor chips is arranged around the inspection auxiliary device so as to suppress variation in length of each wiring from the inspection auxiliary device to each of the plurality of semiconductor chips. Wafer. A semiconductor wafer according to any one of claims 3 to 5,
A semiconductor wafer in which a plurality of inspection auxiliary devices are provided on a single semiconductor wafer. A semiconductor wafer according to claim 6, wherein
A semiconductor wafer in which at least one of the plurality of auxiliary inspection devices is provided in a scribe region of the one semiconductor wafer. A semiconductor wafer according to any one of claims 1 to 7,
The inspection auxiliary device is a semiconductor wafer provided with trimming means for maintaining the function as a measuring machine. A semiconductor wafer according to claim 8, wherein
A semiconductor wafer provided with a spare inspection auxiliary device for use in place of the inspection auxiliary device when trimming by the trimming means in the inspection auxiliary device is impossible or when the trimming is unsuccessful. A method for inspecting a semiconductor device for inspecting electrical characteristics of the plurality of semiconductor chips formed on the semiconductor wafer according to any one of claims 1 to 9,
Electrically connecting a probe needle of an LSI tester to the inspection auxiliary device on the semiconductor wafer and the semiconductor chip to be inspected, and supplying information or signals necessary for the inspection from the LSI tester to the inspection auxiliary device; ,
The inspection auxiliary device supplies a signal to each of the plurality of semiconductor chips, and as a result, receives a signal output from each semiconductor chip, accumulates the received signal in a memory, and based on the accumulated signal A method for inspecting a semiconductor device, comprising: sending a determination result of inspection or the signal itself stored in the memory to the LSI tester via the probe needle.   11. An inspection apparatus comprising a plurality of probe needles that are in direct contact with the inspection auxiliary device on the semiconductor wafer and the semiconductor chip to be inspected for carrying out the semiconductor device inspection method according to claim 10.

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