CN114019352A - Capacitive fingerprint identification chip large-plate FT test system and test method - Google Patents
Capacitive fingerprint identification chip large-plate FT test system and test method Download PDFInfo
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Abstract
The invention discloses a large-plate FT test system and a large-plate FT test method for a capacitive fingerprint identification chip, relates to the technical field of FT tests of semiconductor devices, and solves the technical problem that the existing FT test of the capacitive fingerprint identification chip is low in test efficiency and accuracy. The test system comprises a chip large board, automatic test equipment and a PC host; the large chip board is fixed on automatic test equipment and used for placing n chips to be tested, the automatic test equipment is in communication connection with the PC host, the automatic test equipment is connected with m test boards, and the m test boards are all connected with the PC host; under the control of the PC host, the m test boards are connected with the m chips to be tested in the n at one time, and the connected chips to be tested are subjected to time-sharing test. In addition, the invention also provides a capacitive fingerprint identification chip large-plate FT test method. The invention not only improves the testing speed of the FT testing system, but also improves the stability and accuracy of the FT testing system.
Description
Technical Field
The invention relates to the technical field of FT testing of semiconductor devices, in particular to a capacitive fingerprint identification chip large-plate FT testing system and a testing method.
Background
In the semiconductor industry, chips are generally subjected to cp (chip combining) testing and ft (functional test) testing before they enter the market. CP test is to carry on some important performance tests after the wafer is flowed slice; the FT test is to test the performance and the functional quality of the chip after the chip is packaged from the wafer, and screen out the chips with abnormal functions or performance which does not reach the design standard. The capacitive fingerprint chip can generate an excitation square wave when a fingerprint image is collected, and when the square wave is interfered, the collected fingerprint image has stripe interference and even image disorder. Dozens or even hundreds of fingerprint chips are arranged on a large capacitive fingerprint identification chip plate (hereinafter, the large capacitive fingerprint identification chip plate is generally called as a chip plate).
At present, the FT test of the capacitive fingerprint identification chip generally uses two methods: the first is that the automatic test equipment has a single test seat on the machine table, and can only perform function test on one fingerprint chip, and the test method has high stability, but the time is required in the process of moving the test seat of the equipment from one fingerprint chip to the next fingerprint chip, so the whole test time is long; the second is, there are many test seats on the automatic test equipment board, can carry out many fingerprint chip functional test simultaneously, but when many fingerprint chips simultaneous operation, the excitation square wave of production can interfere with each other, the fingerprint chip quantity of simultaneous operation is more, and the interference is more serious more, leads to the fingerprint image quality unstable of gathering, and the PC host computer can judge the fingerprint chip test result by mistake, judges good chip test fail, extravagant good product chip, increases the cost price of single good product chip.
Disclosure of Invention
The invention aims to provide a capacitive fingerprint identification chip large-panel FT test system and a test method, which are used for solving the technical problems of long test time and low efficiency in the first FT test mode and the technical problem of low test accuracy caused by mutual interference of a plurality of square waves in the second FT test mode. The technical effects that can be produced by the preferred technical scheme in the technical schemes provided by the invention are described in detail in the following.
In order to achieve the purpose, the invention provides the following technical scheme:
the invention provides a capacitive fingerprint identification chip large-plate FT test system, which comprises a chip large plate, automatic test equipment and a PC host; the chip large plate is fixed on the automatic test equipment and used for placing n chips to be tested; the automatic test equipment is in communication connection with the PC host; the automatic test equipment is connected with m test boards which are all connected with the PC host; and under the control of the PC host, the m test boards are connected with the m chips to be tested in the n at one time, and the connected chips to be tested are subjected to time-sharing test.
Further, the automatic test equipment also comprises a plurality of test seats; the m test boards are fixedly connected with the test seats, and each test board is connected with at least one test seat; each test socket can be connected with a pin of the chip to be tested.
Further, the automatic test equipment also comprises a conductive rubber head, a first motion mechanism and a second motion mechanism; the first motion mechanism is fixedly connected with the conductive rubber head and used for driving the conductive rubber head to move up and down, and the conductive rubber head can be contacted with the chip to be tested when moving down; the second motion mechanism is connected with the chip large plate and used for driving the chip large plate to move up and down or horizontally move left and right, and the test seat can be connected with pins of the chip to be tested when the chip large plate moves down.
The invention also provides a capacitive fingerprint identification chip large-plate FT test method, which is used for carrying out the following tests by the capacitive fingerprint identification chip large-plate FT test system:
s10, connecting the m test boards with the m chips to be tested in the n;
s11, performing open circuit and short circuit tests on the chips to be tested connected with the m test boards, and identifying the chips to be tested without open circuit or short circuit as qualified; otherwise, identifying the chip to be tested with an open circuit or a short circuit as unqualified;
s12, performing an IDLE current test on the to-be-tested chip qualified in the open circuit and short circuit tests, and identifying the to-be-tested chip with the IDLE current falling into a first set range as qualified; otherwise, identifying the chip to be tested with the IDLE current exceeding the first set range as unqualified;
s13, collecting white pictures corresponding to the chips to be tested which are qualified in the IDLE current test in a time-sharing manner, and identifying the chips to be tested which are not provided with black dead pixels in the white pictures as being qualified; otherwise, identifying the chip to be tested with the black dead pixel in the white image as unqualified;
s14, collecting black images corresponding to the chips to be tested which are qualified in white image test in a time-sharing manner, and identifying the chips to be tested which are not provided with white dead pixels in the black images as being qualified; otherwise, identifying the chip to be tested with the white dead pixel in the black image as unqualified;
s15, collecting gray images corresponding to the chips to be tested, which are qualified in black image testing, in a time-sharing manner, and identifying the chips to be tested, of which the flatness and the packaging thickness of the gray images fall into a second set range, as being qualified; otherwise, identifying the chip to be tested with the flatness or the packaging thickness of the gray graph exceeding the second set range as unqualified;
s16, performing capture current test on the to-be-tested chip qualified in the gray image test, and identifying the to-be-tested chip with the capture current falling into a third set range as qualified; otherwise, identifying the chip to be detected with the capture current exceeding the third set range as unqualified; outputting a test result;
s17, separating the m test boards from the m chips to be tested connected with the test boards, returning to the step S10, and testing the next group of m chips to be tested which are not tested.
Further, the automatic test equipment comprises a conductive rubber head, a plurality of test seats, a first motion mechanism and a second motion mechanism; step S10 includes the following steps:
s100, placing the large chip board to be tested into a tray;
s101, starting the automatic test equipment, and feeding back a test starting signal to the PC host by the automatic test equipment;
s102, the automatic test equipment receives an instruction sent by the PC host computer for starting a second motion mechanism, and the second motion mechanism is started to move the large chip plate downwards so that pins of a chip to be tested on the large chip plate are connected with spring ejector pins of the test seat;
s103, each test board feeds back the corresponding ID number to the PC host.
Further, step S13 includes the following steps:
s130, the test board receives an instruction of collecting white pictures in a time-sharing mode sent by the PC host, and the test board configures white picture parameters for the chips to be tested which are connected with the test board and qualified in the IDLE current test;
s131, the test board collects the white pictures corresponding to the chips to be tested, which are qualified in IDLE current test, one by one from low to high according to the ID numbers of the chips to be tested in the configured time;
s132, the test board transmits the collected white image to the PC host.
Further, step S14 includes the following steps:
s140, the automatic test equipment receives an instruction sent by the PC host computer for starting the first motion mechanism, and starts the first motion mechanism to move downwards so that the conductive rubber head moves downwards to be connected with the chip to be tested;
s141, the test board receives an instruction of collecting black images in a time-sharing mode sent by the PC host, and the test board configures black image parameters for the chips to be tested which are connected with the test board and qualified in the white image test;
s142, the test board collects the black images corresponding to the chips to be tested which are qualified in white image test one by one from low to high according to the ID numbers of the chips to be tested within the configured time;
s143, the test board transmits the collected black image to the PC host.
Further, step S15 includes the following steps:
s150, the test board receives an instruction of time-sharing gray image acquisition sent by the PC host, and the test board configures gray image parameters for the chips to be tested which are qualified in the black image test connected with the test board;
s151, the test board collects the gray patterns corresponding to the chips to be tested, which are qualified in black pattern test, one by one from low to high according to the ID numbers of the chips to be tested in the configured time;
s152, the test board transmits the collected gray image to the PC host.
Further, step S17 includes the following steps:
s170, the automatic test equipment receives a test ending instruction sent by the PC host, and starts a first motion mechanism to lift the conductive rubber head;
s171, the automatic test equipment receives a test ending instruction sent by the PC host, and starts a second motion mechanism to lift up the large chip board;
and S172, starting a second motion mechanism by the automatic test equipment to horizontally move leftwards or rightwards, aligning the next group of m untested chips to be tested in the chip large board to the m test boards, and returning to the step S102 to carry out the next group of tests.
The implementation of one of the technical schemes of the invention has the following advantages or beneficial effects: the invention realizes the simultaneous test of a plurality of fingerprint chips by arranging the chip large plate and collecting the black, white and grey images of the fingerprint chips in a time-sharing manner; meanwhile, images are acquired in a time-sharing mode through the tested fingerprint chips, so that the phenomenon that excitation square wave signals are mutually influenced to cause image interference or image disorder due to the fact that a plurality of fingerprint chips are subjected to function testing at the same time is avoided. Therefore, the method and the device not only improve the testing speed of the FT testing system, but also improve the stability and accuracy of the FT testing system.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a block diagram of a capacitive fingerprint identification chip large panel FT test system according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a large chip board according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an automatic test equipment according to an embodiment of the present invention;
FIG. 4 is a flowchart of a method for testing a capacitive fingerprint identification chip large panel FT according to an embodiment of the present invention;
FIG. 5 is a detailed flowchart of step S10 in the method for testing a capacitive fingerprint identification chip panel FT according to an embodiment of the present invention;
FIG. 6 is a detailed flowchart of step S13 in the method for testing a capacitive fingerprint identification chip panel FT according to an embodiment of the present invention;
FIG. 7 is a detailed flowchart of step S14 in the method for testing a capacitive fingerprint identification chip panel FT according to an embodiment of the present invention;
FIG. 8 is a detailed flowchart of step S15 in the method for testing a capacitive fingerprint identification chip panel FT according to an embodiment of the present invention;
fig. 9 is a detailed flowchart of step S17 in the method for testing the capacitive fingerprint identification chip large panel FT according to the embodiment of the present invention.
In the figure: 1. a chip large plate; 10. a chip placement frame body; 2. automatic test equipment; 20. a test board; 21. a conductive rubber head; 22. a tray; 23. a test seat; 24. a first movement mechanism; 25. a second movement mechanism; 26. a first body portion; 27. a second body portion; 3. a PC host; 4. a multi-port tap.
Detailed Description
In order that the objects, aspects and advantages of the present invention will become more apparent, various exemplary embodiments will be described below with reference to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary embodiments in which the invention may be practiced. The same numbers in different drawings identify the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. It is to be understood that they are merely examples of processes, methods, apparatus, etc. consistent with certain aspects of the present disclosure as detailed in the appended claims, and that other embodiments may be used or structural and functional modifications may be made to the embodiments set forth herein without departing from the scope and spirit of the present disclosure.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," and the like are used in the orientations and positional relationships illustrated in the accompanying drawings for the purpose of facilitating the description of the present invention and simplifying the description, and do not indicate or imply that the elements so referred to must have a particular orientation, be constructed in a particular orientation, and be operated. The terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "plurality" means two or more. The terms "coupled" and "connected" are to be construed broadly and may include, for example, a fixed connection, a removable connection, a unitary connection, a mechanical connection, an electrical connection, a communicative connection, a direct connection, an indirect connection via intermediate media, and may include, but are not limited to, a connection between two elements or an interactive relationship between two elements. The term "and/or" includes any and all combinations of one or more of the associated listed items. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In order to explain the technical solution of the present invention, the following description is made by way of specific examples, which only show the relevant portions of the embodiments of the present invention.
The first embodiment is as follows:
as shown in fig. 1-2, the invention provides a capacitive fingerprint identification chip large panel FT test system, which comprises a chip large panel 1, automatic test equipment 2, and a PC host 3. Specifically, a chip large plate 1 is fixed on an automatic test device 2 and used for placing n chips to be tested; automatic test equipment 2 and PC host computer 3 communication connection, and automatic test equipment 2 is provided with m and surveys test panel 20, and m surveys test panel 20 and all links to each other with PC host computer 3. Wherein n and m are natural numbers larger than 1, and n is not smaller than m, preferably, n is an integer multiple of m, and m is equal to 8. Further, the chip large board 1 is fixed to the automatic test equipment 2 by a tray 22, and the chip large board 1 can be directly placed in the tray 22, and the tray 22 is fixed to a second moving mechanism 25 described below. Under the control of the PC host 3, the m test boards 20 are connected with the m chips to be tested in n at a time, and the connected chips to be tested are subjected to time-sharing test. In this embodiment, the chip to be measured is preferably a fingerprint chip (short for capacitive fingerprint identification chip), the large chip board 1 has a fixed size, a plurality of fingerprint chips with a fixed number are arranged on the large chip board, and the size of the large chip board 1 is matched with the overall size of the plurality of fingerprint chips. The fingerprint chips are uniformly distributed in the transverse direction and the longitudinal direction, such as 4 rows and 14 columns, are of an integral structure, and are cut into single fingerprint chips when the fingerprint chips to be tested are used.
The large-plate FT test system of the capacitive fingerprint identification chip can simultaneously test 8 fingerprint chips at one time. A plurality of columns of chip placement frames 10 (the chip refers to a capacitive fingerprint identification chip or a fingerprint chip) are arranged on the chip large plate 1, each column of chip placement frames 10 can place 4 fingerprint chips, the total number of n chip placement frames 10 is n, and the chip placement frames 10 need to be arranged according to a specific chip structure. Of course, the chip placement frame 10 is provided with a hole structure through which the pins of the chip to be tested can penetrate and which matches the number and structure of the pins of the chip to be tested, and the hole structure needs to be set according to the shape of the pins of the chip to be tested. Therefore, the invention can simultaneously test a plurality of fingerprint chips and can also carry out time-sharing test (collecting images of the fingerprint chips in a time-sharing way) on the tested fingerprint chips, thereby avoiding that the chips to be tested on the same chip large plate 1 are simultaneously collected with images, and excitation signals (square wave signals) can mutually influence to cause image interference or image disorder during simultaneous image collection. Therefore, the invention not only improves the testing speed, but also improves the stability and the accuracy of the capacitive fingerprint identification chip large-plate FT testing system.
As shown in fig. 3, the automatic test equipment 2 further includes a conductive rubber head 21, and a plurality of test sockets 23. Specifically, the tray 22 is disposed between the conductive rubber head 21 and the test socket 23, and is used for placing the chip large board 1. The m test boards 20 are all fixedly connected (e.g., screwed) with the test sockets 23, and each test board 20 is connected with at least one test socket via a flat cable, and each test socket can be connected with a pin of a chip to be tested, so that the number of the test sockets is consistent with the number of the pins of the chip to be tested. The m test boards 20 are connected to the PC host 3 via a multi-port tap 4, preferably an 8-port USB tap 4. Further, the automatic test equipment 2 is provided with a control module (not illustrated), the control module is connected to 8 test boards 20 through a flat cable, the 8 test boards 20 are respectively connected to 8 USB taps through USB cables, and the PC host 3 can communicate with the 8 test boards 20 simultaneously by connecting the USB taps through only one USB port. It should be noted that the test socket 23 is provided with a test pin, and the test pin can be simultaneously contacted with pins of two columns of chips (8 fingerprint chips) of the chip large board 1, so as to fasten the chip to be tested in the test process, so that the test socket can be better connected with the pins of the chip to be tested.
Further, the automatic test equipment 2 further includes a first body portion 26, a second body portion 27, a first movement mechanism 24, and a second movement mechanism 25. The first motion mechanism 24 is fixedly connected (e.g., screwed) with the conductive rubber head 21, and is used for driving the conductive rubber head 21 to move up and down, and when moving down, the conductive rubber head 21 can be connected with a chip to be tested, so as to perform time-sharing drawing; the second motion mechanism 25 is fixedly connected (e.g., screwed) with the tray 22, and is used for driving the tray 22 to move up and down or move horizontally left and right, when moving down, two rows (8) of chip pins of the chip large board 1 on the tray 22 are connected with spring ejector pins of the test socket, so as to test open circuits, short circuits or IDLE currents of a plurality of fingerprint chips; when moving to the left or right, the next group (8 fingerprint chips) of test flow is entered. Furthermore, the m test boards 20 are fixedly connected to the first body portion 26 by a fixing device (e.g. a fixing bracket), the second moving mechanism 25 is further fixedly connected to the first body portion 26 by a screw, and the second body portion 27 is further fixedly connected to the first moving mechanism 24 by a screw. Preferably, the first movement mechanism 24 and the second movement mechanism 25 are both air cylinders (of course, other movement mechanisms are also possible, and are not limited in particular), and are both electrically connected to the control module of the automatic test equipment 2.
Example two:
as shown in fig. 4 to 9, the present invention further provides a capacitive fingerprint identification chip large panel FT test method, which performs the following tests by using the capacitive fingerprint identification chip large panel FT test system according to the first embodiment:
and S10, connecting the m test boards with the m chips to be tested in the n. The method comprises the following steps:
s100, placing a chip large plate 1 to be tested into a tray 22;
s101, starting automatic test equipment, and feeding back a test starting signal to the PC host 3 by the automatic test equipment. Specifically, a test start key switch on the automatic test equipment 2 is clicked, and the automatic test equipment 2 (a control module, the same applies below) feeds back a test start signal to the PC host 3;
s102, the automatic test equipment 2 receives an instruction sent by the PC host 3 for starting the second movement mechanism 25, and starts the second movement mechanism 25 to move the tray 22 downwards, so that pins of part of chips to be tested (8 chips to be tested) on the chip large plate 1 on the tray 22 are connected with spring ejector pins of the test base. By the first embodiment, it is known that dozens or even hundreds of fingerprint chips are arranged on the chip large board 1, and by using the method, the chips to be tested on the chip large board 1 need to be tested for many times, and 8 chips to be tested can be tested each time;
s103, each test board 20 feeds back the corresponding ID number to the PC host 3. PC host computer 3 matches the ID number of test board 20 to the chip under test connected to test board 20, i.e. the ID number of the chip under test is identical to the ID number of test board 20.
S11, performing open circuit and short circuit tests on the chips to be tested connected with the m test boards, and identifying the chips to be tested without open circuit or short circuit as qualified; otherwise, the chip to be tested with the open circuit or the short circuit is marked as unqualified. The procedure is further illustrated as follows:
a PC host side: the PC host 3 receives the ID number corresponding to each test board 20, and simultaneously sends open-circuit and short-circuit test signals to the m test boards 20 according to the ID numbers; the PC host 3 receives the test results fed back by the m test boards 20, judges whether the chips to be tested connected with the m test boards have short circuit or open circuit according to the voltage or current values in the test results, marks the chips to be tested with open circuit or short circuit as NG, and judges the chips to be defective; otherwise, the product is qualified and identified as YG.
Testing a board end: each test board 20 receives the open-circuit and short-circuit test signals of the PC host 3, simultaneously energizes the chip to be tested connected thereto, and feeds back the current or voltage corresponding to the corresponding pin of the chip to the PC host 3 as a test result.
S12, performing IDLE current test on the to-be-tested chips qualified in the open circuit and short circuit tests, and identifying the to-be-tested chips with IDLE current falling into a first set range as qualified; otherwise, identifying the chip to be tested with the IDLE current exceeding the first set range as unqualified. The specific description is as follows:
a PC host side: the PC host 3 sends IDLE current test signals to test boards 20 corresponding to all chips to be tested, wherein the chips to be tested are qualified in open circuit and short circuit tests; and receiving the IDLE current test result sent by the test board 20, identifying the chip to be tested corresponding to the IDLE current exceeding the first set range in the test result as NG, and determining the chip to be tested as a defective product, otherwise, identifying the chip to be tested as a qualified product as YG. The first set range of the IDLE current is determined according to national or industrial standards;
testing a board end: the test board 20 corresponding to all the chips to be tested which are qualified in the open circuit and short circuit tests receives the IDLE current test signal; initializing all chips to be tested which are qualified in open circuit and short circuit tests, and reading and writing corresponding registers of the capacitive fingerprint identification chips; and the IDLE current corresponding to the corresponding pins of all the chips to be tested, which are qualified in the open circuit and short circuit tests, is used as a test result and fed back to the PC host 3.
S13, collecting white pictures corresponding to the chips to be tested which are qualified in the IDLE current test in a time-sharing manner, and identifying the chips to be tested which are not provided with black dead pixels in the white pictures as being qualified; otherwise, identifying the chip to be tested with the black dead pixel in the white image as unqualified. In particular, the amount of the solvent to be used,
s130, the test board 20 receives the command of time-sharing white image collection sent by the PC host 3, and the test board 20 configures white image parameters for the chips to be tested that are qualified in the IDLE current test connected thereto (i.e. writes corresponding parameters to the white image setting register). Setting RGB values of a white image (for example, setting R: 255, G: 255, B: 255), and setting time of time-sharing collection (after a PC host 3 sends an instruction to a first test board 20 to collect the white image and the collection is completed, and the PC host 3 sends an instruction to a second test board 20 to collect the white image and the collection is repeated) of the white image (the specific time is determined according to the actual situation);
s131, the test board 20 collects white pictures corresponding to the chips to be tested, which are qualified in the IDLE current test, one by one from low to high according to the ID numbers of the chips to be tested in the configured time;
s132, the test board 20 transmits the acquired white image to the PC host 3. Further, the program executed on the PC host side is: the PC host 3 sends a signal for testing a white image to a test board 20 connected with the chip to be tested, which is qualified in the IDLE current test; receiving the white images collected by the test board 20, detecting whether black dead pixels exist in all the collected white images one by one, marking the chip to be tested corresponding to the black dead pixels as NG, and judging the chip to be tested as a defective product; otherwise, the product is determined to be a good product and identified as YG.
S14, collecting black images corresponding to the chips to be tested which are qualified in the white image test in a time-sharing manner, identifying the chips to be tested which do not have white dead spots in the black images as qualified, and otherwise identifying the chips to be tested which have white dead spots in the black images as unqualified. The method comprises the following specific steps:
s140, the automatic test equipment 2 receives an instruction sent by the PC host 3 for starting the first motion mechanism 24, and starts the first motion mechanism 24 to move downwards, so that the conductive rubber head 21 moves downwards to be connected with the chip to be tested. It should be noted that the number of the conductive rubber heads 21 is 8, and all the conductive rubber heads 21 are connected to the ground, so as to maintain the consistency of the electric potential on the conductive rubber heads;
s141, the test board 20 receives the instruction of time-sharing black image collection sent by the PC host 3, the test board 20 configures black image parameters (i.e. writes corresponding parameters to a black image setting register) for the qualified chip to be tested of the white image test connected with the test board 20, and the black image parameters comprise setting RGB values of the black image (for example, setting R: 0, G: 0 and B: 0) and setting time for time-sharing black image collection (the specific time is determined according to the actual situation);
s142, the test board 20 collects black pictures corresponding to the chips to be tested which are qualified in the white picture test one by one from low to high according to the ID numbers of the chips to be tested within the configured time;
s143, the test board 20 transmits the collected black image to the PC mainframe 3. Further, the program executed by the PC host is: the PC host 3 sends a signal for testing a black image to a test board 20 corresponding to the chip to be tested which is qualified in the white image test; the white images collected by the test board 20 are received, whether white dead pixels exist in all the collected black images is detected one by one, the chip to be tested corresponding to the white dead pixels is identified as NG, and the chip to be tested is judged to be a defective product, otherwise, the chip to be tested is judged to be a qualified product, and the chip to be tested is identified as YG.
S15, collecting gray images corresponding to the chips to be tested which are qualified in the black image test in a time-sharing manner, and identifying the chips to be tested which are qualified in the flatness and the packaging thickness of the gray images in a second set range as being qualified; otherwise, the chip to be tested with the flatness or the packaging thickness of the gray graph exceeding the second set range is marked as unqualified. The further steps are as follows:
s150, the test board 20 receives the command of time-sharing gray pattern collection sent by the PC host 3, and the test board 20 configures gray pattern parameters for the chips to be tested that are qualified in the black pattern test connected to the test board 20. The method comprises the steps of setting RGB values of a gray map (such as setting R: 96, G: 96 and B: 96) and setting time for collecting the gray map when the gray map is acquired (the specific time is determined according to actual conditions);
s151, the test board 20 collects gray patterns corresponding to the chips to be tested, which are qualified in the black pattern test, one by one from low to high according to the ID numbers of the chips to be tested in the configured time;
s152, the test board 20 transmits the collected gray image to the PC mainframe 3. Further, the program executed by the PC host is: the PC host 3 sends a signal for testing a 'grey picture' to the test board 20 corresponding to the chip to be tested, which is qualified in the black picture test; receiving the gray patterns collected by the test board 20, detecting whether the flatness and the package thickness of all the collected gray patterns are within a second set range one by one, and identifying the chip to be tested which is beyond the second set range as NG, and determining the chip to be tested as a defective product, otherwise, determining the chip to be tested as a qualified product, and identifying the chip to be tested as YG. The second setting range is executed with reference to national or industrial standards.
S16, performing capture current test on the to-be-tested chip qualified in the gray image test, and identifying the to-be-tested chip with the capture current falling in a set range as qualified; otherwise, identifying the chip to be detected with the capture current exceeding the third set range as unqualified; and outputting a test result. Specifically, the PC host side: the PC host 3 sends a capture current test signal to a test board 20 corresponding to a chip to be tested which is qualified in gray image test; receiving the capture current sent by the test board 20, and identifying the capture current exceeding the third set range as NG, determining the capture current as a defective product, otherwise, determining the capture current as a qualified product, and identifying the capture current as YG; and outputting a test result. The third set range of capture current is implemented according to national or industry standards. It should be noted that, the test result identifier YG or NG of 8 chips to be tested corresponding to the unique ID number of 8 test boards outputs a test result, and whether the chip to be tested is qualified or not can be determined according to the test result identifier corresponding to the ID number. Of course, the test results of each time will be saved separately and not be overwritten or replaced by the next test result.
Testing a board end: the test board 20 corresponding to all the chips to be tested which are qualified in the gray image test receives the capture current test signal; the test board 20 corresponding to all the chips to be tested which pass the gray pattern test sets the collection mode of the chip to be the 'picture collection mode'; and sending the capture currents corresponding to the pins of all the chips to be tested, which are qualified in the gray graph test, to the PC host 3.
And S17, separating the m test boards from the m chips to be tested connected with the test boards, returning to the step S10, and testing the next group of m chips to be tested which are not tested. The method comprises the following steps:
s170, the automatic test equipment 2 receives a test ending instruction sent by the PC host 3, and starts the first motion mechanism 24 to lift the conductive rubber head 21;
s171, the automatic test equipment 2 receives a test ending instruction sent by the PC host 3, and starts the second motion mechanism 25 to lift the chip large board 1;
and S172, starting the second motion mechanism 25 by the automatic test equipment 2 to horizontally move left and right, aligning the next group of m untested chips to be tested in the chip large plate 1 to the m test plates, and returning to the step S102 to carry out the next group of tests. And repeating the steps until all the chips to be tested are tested or a stop command is controlled.
In conclusion, the invention realizes the simultaneous test of a plurality of fingerprint chips by arranging the large chip board and collecting the black, white and grey images of the fingerprint chips in a time-sharing manner; meanwhile, images are acquired in a time-sharing mode through the tested fingerprint chips, so that the phenomenon that excitation square wave signals are mutually influenced to cause image interference or image disorder due to the fact that a plurality of fingerprint chips are subjected to function testing at the same time is avoided. Therefore, the system and the method not only improve the testing speed of the FT testing system, but also improve the stability and the accuracy of the FT testing system.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (9)
1. A capacitive fingerprint identification chip large-plate FT test system is characterized by comprising a chip large plate, automatic test equipment and a PC host;
the chip large plate is fixed on the automatic test equipment and used for placing n chips to be tested; the automatic test equipment is in communication connection with the PC host;
the automatic test equipment is connected with m test boards which are all connected with the PC host;
and under the control of the PC host, the m test boards are connected with the m chips to be tested in the n at one time, and the connected chips to be tested are subjected to time-sharing test.
2. The capacitive fingerprint identification chip large panel FT test system of claim 1, wherein the automatic test equipment further comprises a plurality of test sockets;
the m test boards are fixedly connected with the test seats, and each test board is connected with at least one test seat;
each test socket can be connected with a pin of the chip to be tested.
3. The capacitive fingerprint identification chip large panel FT testing system of claim 2, wherein the automatic testing device further comprises a conductive rubber head, a first motion mechanism and a second motion mechanism;
the first motion mechanism is fixedly connected with the conductive rubber head and used for driving the conductive rubber head to move up and down, and the conductive rubber head can be contacted with the chip to be tested when moving down;
the second motion mechanism is connected with the chip large plate and used for driving the chip large plate to move up and down or horizontally move left and right, and the test seat can be connected with pins of the chip to be tested when the chip large plate moves down.
4. A capacitive fingerprint identification chip large-plate FT test method is characterized in that the capacitive fingerprint identification chip large-plate FT test system of any one of claims 1-3 is used for carrying out the following tests:
s10, connecting the m test boards with the m chips to be tested in the n;
s11, performing open circuit and short circuit tests on the chips to be tested connected with the m test boards, and identifying the chips to be tested without open circuit or short circuit as qualified; otherwise, identifying the chip to be tested with an open circuit or a short circuit as unqualified;
s12, performing an IDLE current test on the to-be-tested chip qualified in the open circuit and short circuit tests, and identifying the to-be-tested chip with the IDLE current falling into a first set range as qualified; otherwise, identifying the chip to be tested with the IDLE current exceeding the first set range as unqualified;
s13, collecting white pictures corresponding to the chips to be tested which are qualified in the IDLE current test in a time-sharing manner, and identifying the chips to be tested which are not provided with black dead pixels in the white pictures as being qualified; otherwise, identifying the chip to be tested with the black dead pixel in the white image as unqualified;
s14, collecting black images corresponding to the chips to be tested which are qualified in white image test in a time-sharing manner, and identifying the chips to be tested which are not provided with white dead pixels in the black images as being qualified; otherwise, identifying the chip to be tested with the white dead pixel in the black image as unqualified;
s15, collecting gray images corresponding to the chips to be tested, which are qualified in black image testing, in a time-sharing manner, and identifying the chips to be tested, of which the flatness and the packaging thickness of the gray images fall into a second set range, as being qualified; otherwise, identifying the chip to be tested with the flatness or the packaging thickness of the gray graph exceeding the second set range as unqualified;
s16, performing capture current test on the to-be-tested chip qualified in the gray image test, and identifying the to-be-tested chip with the capture current falling into a third set range as qualified; otherwise, identifying the chip to be detected with the capture current exceeding the third set range as unqualified; outputting a test result;
s17, separating the m test boards from the m chips to be tested connected with the test boards, returning to the step S10, and testing the next group of m chips to be tested which are not tested.
5. The capacitive fingerprint identification chip large panel FT test method according to claim 4, wherein the automatic test equipment comprises a conductive rubber head, a plurality of test seats, a first motion mechanism and a second motion mechanism;
step S10 includes the following steps:
s100, placing the large chip board to be tested into a tray;
s101, starting the automatic test equipment, and feeding back a test starting signal to the PC host by the automatic test equipment;
s102, the automatic test equipment receives an instruction sent by the PC host computer for starting a second motion mechanism, and the second motion mechanism is started to move the large chip plate downwards so that pins of a chip to be tested on the large chip plate are connected with spring ejector pins of the test seat;
s103, each test board feeds back the corresponding ID number to the PC host.
6. The capacitive fingerprint identification chip large panel FT test method according to claim 5, wherein the step S13 comprises the steps of:
s130, the test board receives an instruction of collecting white pictures in a time-sharing mode sent by the PC host, and the test board configures white picture parameters for the chips to be tested which are connected with the test board and qualified in the IDLE current test;
s131, the test board collects the white pictures corresponding to the chips to be tested, which are qualified in IDLE current test, one by one from low to high according to the ID numbers of the chips to be tested in the configured time;
s132, the test board transmits the collected white image to the PC host.
7. The capacitive fingerprint identification chip large panel FT test method according to claim 5, wherein the step S14 comprises the steps of:
s140, the automatic test equipment receives an instruction sent by the PC host computer for starting the first motion mechanism, and starts the first motion mechanism to move downwards so that the conductive rubber head moves downwards to be connected with the chip to be tested;
s141, the test board receives an instruction of collecting black images in a time-sharing mode sent by the PC host, and the test board configures black image parameters for the chips to be tested which are connected with the test board and qualified in the white image test;
s142, the test board collects the black images corresponding to the chips to be tested which are qualified in white image test one by one from low to high according to the ID numbers of the chips to be tested within the configured time;
s143, the test board transmits the collected black image to the PC host.
8. The capacitive fingerprint identification chip large panel FT test method according to claim 5, wherein the step S15 comprises the steps of:
s150, the test board receives an instruction of time-sharing gray image acquisition sent by the PC host, and the test board configures gray image parameters for the chips to be tested which are qualified in the black image test connected with the test board;
s151, the test board collects the gray patterns corresponding to the chips to be tested, which are qualified in black pattern test, one by one from low to high according to the ID numbers of the chips to be tested in the configured time;
s152, the test board transmits the collected gray image to the PC host.
9. The capacitive fingerprint identification chip large panel FT test method according to claim 5, wherein the step S17 comprises the steps of:
s170, the automatic test equipment receives a test ending instruction sent by the PC host, and starts a first motion mechanism to lift the conductive rubber head;
s171, the automatic test equipment receives a test ending instruction sent by the PC host, and starts a second motion mechanism to lift up the large chip board;
and S172, starting a second motion mechanism by the automatic test equipment to horizontally move leftwards or rightwards, aligning the next group of m untested chips to be tested in the chip large board to the m test boards, and returning to the step S102 to carry out the next group of tests.
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