JP2005129756A - Method of joining semiconductor element - Google Patents

Method of joining semiconductor element Download PDF

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Publication number
JP2005129756A
JP2005129756A JP2003364275A JP2003364275A JP2005129756A JP 2005129756 A JP2005129756 A JP 2005129756A JP 2003364275 A JP2003364275 A JP 2003364275A JP 2003364275 A JP2003364275 A JP 2003364275A JP 2005129756 A JP2005129756 A JP 2005129756A
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semiconductor element
transparent electrode
conductive film
substrate
anisotropic conductive
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Chiharu Wakamatsu
千春 若松
Takeshi Fujiyama
毅 藤山
Yosuke Koga
陽介 古賀
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of joining semiconductor element by which the junction reliability between semiconductor elements and a substrate can be secured and, at the same time, the fall of the electrical characteristics of the elements can be prevented at the time of mounting the elements on the substrate at fine pitches by using an anisotropic conductive film. <P>SOLUTION: In the method of joining semiconductor element, bumps 5 which are projecting electrodes formed on the semiconductor elements 3 are respectively conductively connected to transparent electrodes 2 formed on the top surface of a glass substrate 1 which transmits ultraviolet rays 12 through the anisotropic conductive film 6. After the anisotropic conductive film 6 is transferred to the transparent electrodes 2 and the bumps 5 are respectively placed on the electrodes 2, walls 9 are formed by curing the conductive film 6 by projecting light upon the peripheral sections of the electrodes 2 from the bottom surface of the glass substrate 1. Then the semiconductor elements 3 are pressurized and the conductive film 6 is cured by projecting the ultraviolet rays 12 upon the area of the glass substrate 1 including the transferred extent of the conductive film 6 from the bottom surface of the substrate 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、液晶パネルを構成するガラス基板上に、半導体素子を異方導電性フィルムを用いてフェイスダウンにて接合する半導体素子の接合方法に関するものである。   The present invention relates to a semiconductor element bonding method in which a semiconductor element is bonded face down using an anisotropic conductive film on a glass substrate constituting a liquid crystal panel.

異方導電性フィルムは、加熱により溶融し硬化反応がおきるエポキシ樹脂等の熱硬化性樹脂に、金属（金やニッケル）メッキを施したプラスチック粒子を含有した、常温では半固形の接着フィルムである。その硬化にはアミン系の潜在型触媒が主に用いられ、半導体素子とガラス基板、プリント配線基板の電気的接続に広く利用されている。   An anisotropic conductive film is a semi-solid adhesive film at room temperature containing plastic particles obtained by applying metal (gold or nickel) plating to a thermosetting resin such as an epoxy resin that melts upon heating and undergoes a curing reaction. . For the curing, an amine-based latent catalyst is mainly used, and is widely used for electrical connection between a semiconductor element, a glass substrate, and a printed wiring board.

この異方導電性フィルムを用いた接合方法は、まず、電極が形成されたプリント配線基板に異方導電性フィルムを加熱しながら転写する。次にこの異方導電性フィルムを転写したプリント配線基板に、半導体素子を半導体素子に形成されたバンプと電極の位置を合わせて載置する。最後に、ヒートツール等の圧着用の治具を用いて加圧・加熱しながら固着させる。このとき、加圧・加熱によって異方導電性フィルム中の樹脂が溶融し、バンプと電極の間から流れ出し、異方導電性フィルムに含有される導電粒子がバンプと電極の間に捕獲される。   In the bonding method using the anisotropic conductive film, first, the anisotropic conductive film is transferred to a printed wiring board on which electrodes are formed while heating. Next, the semiconductor element is placed on the printed circuit board onto which the anisotropic conductive film has been transferred with the bumps and electrodes formed on the semiconductor element being aligned. Finally, it is fixed while pressing and heating using a crimping jig such as a heat tool. At this time, the resin in the anisotropic conductive film is melted by pressurization and heating, and flows out from between the bump and the electrode, and the conductive particles contained in the anisotropic conductive film are captured between the bump and the electrode.

半導体素子の実装分野においては、高密度化・小型化・薄型化が要求されており、接続ピッチは４０μｍ以下、バンプ面積も５００μｍ2程度以下と細密化が進んでいる。バンプの細密化とともに、必然的にプリント配線基板に形成されるパターンの寸法も小さくなっている。その結果、半導体素子とプリント配線基板の接合の際に、バンプと電極との間に捕獲される導電粒子の数が少なくなり、接続信頼性が低下するということが問題となってきた。また、隣接するバンプ同士の間に導電粒子が数珠つながりとなり、短絡することで電気特性の低下も発生し、問題となっている。 In the field of mounting semiconductor devices, higher density, smaller size, and thinner thickness are required, and the connection pitch is 40 μm or less and the bump area is about 500 μm 2 or less, and the density is increasing. As the bumps become finer, the dimensions of the pattern formed on the printed circuit board are inevitably reduced. As a result, when the semiconductor element and the printed wiring board are joined, the number of conductive particles trapped between the bump and the electrode is reduced, and the connection reliability is lowered. In addition, the conductive particles are connected in a row between adjacent bumps, and a short circuit causes a decrease in electrical characteristics, which is a problem.

このような問題を解決するために、バンプの形状を、基板電極に対向する面の周辺部を突出させることで、流れ去ってしまっていた導電粒子が、突出部により遮られ、バンプと基板電極との間に導電粒子を捕獲することで高い信頼性が得られるということが特許文献１に記載されている。   In order to solve such a problem, the bump is made to protrude from the periphery of the surface facing the substrate electrode, so that the conductive particles that have flowed away are blocked by the protrusion, and the bump and the substrate electrode Patent Document 1 describes that high reliability can be obtained by capturing conductive particles between the two.

また、プリント配線基板に形成された電極近傍に電極の厚みよりも厚いレジストを電極の周辺に設けて、レジストと電極とで凹形状を形成し、電子部品とプリント配線基板の接合時において、異方導電性フィルムの溶融による導電粒子の流れを抑制するということが特許文献２に記載されている。
特開平１０−９８０６９号公報（段落番号００２２−００３２） 特開平１１−１６９４９号公報（段落番号００１２−００１５） In addition, a resist thicker than the thickness of the electrode is provided near the electrode formed on the printed wiring board, and a concave shape is formed by the resist and the electrode. Patent Document 2 describes that the flow of conductive particles due to melting of the conductive film is suppressed.
JP-A-10-98069 (paragraph numbers 0022-0032) Japanese Patent Laid-Open No. 11-16949 (paragraph numbers 0012-0015)

しかしながら、特許文献１および特許文献２の接合方法では、電子部品をプリント配線基板に載置し、バンプが電極に当接する際に、導電粒子の流れを抑止するバンプに形成された突出部やレジスト付近に、押し流された導電粒子が滞留し、ひとかたまりとなってしまう。そうなると、バンプと電極間の導電粒子の偏りによりバンプの平衡度が保たれないので、バンプの中心部の導電粒子が少ない状態となり、バンプと電極が非接触となったり、局所的な荷重によるバンプの変形が発生したりし、接続信頼性が確保できないという問題がある。   However, in the joining methods disclosed in Patent Document 1 and Patent Document 2, when an electronic component is placed on a printed wiring board and the bump contacts the electrode, a protrusion or resist formed on the bump that suppresses the flow of conductive particles. In the vicinity, the swept conductive particles stay and become a lump. As a result, the balance of the bumps cannot be maintained due to the bias of the conductive particles between the bumps and the electrodes, so that the conductive particles in the center of the bumps are few, the bumps and the electrodes are not in contact, or the bumps due to local loads There is a problem that the connection reliability cannot be ensured.

そこで本発明の目的は、異方導電性フィルムを用いた半導体素子のファインピッチ実装において、半導体素子と基板の接合信頼性を確保するとともに、電気的特性の低下を防止できる半導体素子の接合方法を提供する。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor element bonding method capable of ensuring the reliability of bonding between a semiconductor element and a substrate and preventing deterioration of electrical characteristics in fine pitch mounting of a semiconductor element using an anisotropic conductive film. provide.

この課題を解決するために本発明は、基板に形成した透明電極に、半導体素子に形成したバンプを、異方導電性フィルムを介して導通接続する半導体素子の接合方法において、透明電極に異方導電性フィルムを転写し、バンプを透明電極に載置し、光を基板の下方から透明電極の周囲部分に照射し、異方導電性フィルムを部分的に硬化させ壁部を形成した後、半導体素子を押圧し、異方導電性フィルムを硬化させることを特徴とする半導体素子の接合方法としたものである。   In order to solve this problem, the present invention relates to a method for bonding a semiconductor element in which a bump formed on a semiconductor element is electrically connected to a transparent electrode formed on a substrate via an anisotropic conductive film. After transferring the conductive film, placing the bumps on the transparent electrode, irradiating light to the surrounding area of the transparent electrode from below the substrate, partially curing the anisotropic conductive film to form the wall, the semiconductor The semiconductor element bonding method is characterized in that the element is pressed to cure the anisotropic conductive film.

これにより、半導体素子を基板に載置し押圧する際に、壁部内の導電粒子が流出しないため、半導体素子のバンプと基板の透明電極の間に、充分な導電性粒子の数を確保できる。   Thus, when the semiconductor element is placed on the substrate and pressed, the conductive particles in the wall portion do not flow out, so that a sufficient number of conductive particles can be ensured between the bumps of the semiconductor element and the transparent electrode of the substrate.

ここで、透明電極の周囲部分とは、透明電極の外周から透明電極間の１／２の距離までの範囲をいう。つまり、光照射による異方導電性フィルムの硬化を透明電極間の１／２の距離までの範囲内で透明電極の外周に壁部を形成することで、隣接する透明電極に形成した壁部と重なり合っても壁部から導電粒子の流出が発生しない。   Here, the peripheral portion of the transparent electrode refers to a range from the outer periphery of the transparent electrode to a half distance between the transparent electrodes. That is, the wall portion formed on the adjacent transparent electrode is formed by forming the wall portion on the outer periphery of the transparent electrode within a range up to ½ distance between the transparent electrodes by curing the anisotropic conductive film by light irradiation. Even if they overlap, the conductive particles do not flow out of the wall.

また、光とは、紫外線、赤外線および可視光線を含み、照射することで異方導電性フィルムが硬化可能であればどの種類の光を用いても良いが、局所的に照射する場所を制御する場合は、紫外線レーザ等を使用するのが望ましい。   The light includes ultraviolet rays, infrared rays, and visible rays, and any kind of light may be used as long as the anisotropic conductive film can be cured by irradiation, but the place to be irradiated locally is controlled. In this case, it is desirable to use an ultraviolet laser or the like.

なお、本発明の説明においては、基板に形成された透明電極側の面を上側、反対面を下側としている。   In the description of the present invention, the surface on the transparent electrode side formed on the substrate is the upper side, and the opposite surface is the lower side.

本発明により、以下の効果を奏することができる。
（１）請求項１に記載の発明によれば、透明電極の周辺部分に壁部を形成することで、半導体素子を基板に載置する際に、壁部内の導電粒子が流出しないため、半導体素子のバンプと基板の透明電極の間に、充分な導電性粒子の数を確保できるので、バンプと透明電極で確実な導電粒子の捕獲ができる。また、壁部により導電粒子が隣接するバンプの間に数珠つながりとなることがないため、隣接するバンプ同士での短絡が防止できる。よって、確実なバンプと透明電極との接続が図れ、高い接続信頼性を確保することができる。
（２）請求項２に記載の発明によれば、透明電極表面にメッキ加工を施すことで、光の照射を、透明電極を含む透明電極の周辺部分にすれば良いので、光の照射の制御が簡易となる。
（３）請求項３に記載の発明によれば、壁部を形成する際に、基板と光源の間に遮断板を介在させることにより、光の照射にレーザ装置等の局所的に制御をするような高価な装置を必要とせず、異方導電性フィルムが硬化する光であればメタルやハロゲン球等の安価な照明装置が使用できるので、コストを押えた容易な半導体素子の接合方法とすることができる。
（４）請求項４に記載の発明によれば、半導体素子を載置し押圧し、壁部の開口した一側面から樹脂や導電粒子が流れ出ることで、バンプが壁部内に挿入したときの内部圧力の増加を抑制し、樹脂の流動を保ちつつ、導電粒子のバンプと透明電極の間の導電粒子の捕獲がより容易となり、電気的接合の信頼性が向上する。
（５）請求項５に記載の発明によれば、基板の下方から光を基板の異方導電性フィルムが転写された範囲を含む領域に光を照射した後に、半導体素子および基板を加熱することで、半導体素子の接合に要する時間を短くすることができる。 According to the present invention, the following effects can be obtained.
(1) According to the invention described in claim 1, by forming the wall portion in the peripheral portion of the transparent electrode, the conductive particles in the wall portion do not flow out when the semiconductor element is placed on the substrate. Since a sufficient number of conductive particles can be secured between the element bumps and the transparent electrode of the substrate, the conductive particles can be reliably captured by the bumps and the transparent electrode. In addition, since the conductive particles are not connected between adjacent bumps by the wall portion, a short circuit between adjacent bumps can be prevented. Therefore, reliable connection between the bump and the transparent electrode can be achieved, and high connection reliability can be ensured.
(2) According to the invention described in claim 2, since light irradiation may be performed on the peripheral portion of the transparent electrode including the transparent electrode by plating the surface of the transparent electrode, the light irradiation is controlled. Becomes simple.
(3) According to the invention described in claim 3, when the wall portion is formed, the shielding device is interposed between the substrate and the light source to locally control the irradiation of light, such as a laser device. Such an expensive conductive device can be used as long as the anisotropic conductive film cures light without using such an expensive device, so that it is possible to use an inexpensive lighting device such as a metal or a halogen bulb. be able to.
(4) According to the invention described in claim 4, the semiconductor element is placed and pressed, and the resin and conductive particles flow out from one side of the wall that is opened, so that the inside when the bump is inserted into the wall. While suppressing the increase in pressure and maintaining the flow of resin, it becomes easier to capture the conductive particles between the bumps of the conductive particles and the transparent electrode, and the reliability of electrical joining is improved.
(5) According to the invention described in claim 5, the semiconductor element and the substrate are heated after irradiating light from below the substrate to the region including the range where the anisotropic conductive film of the substrate is transferred. Thus, the time required for bonding the semiconductor elements can be shortened.

本願の請求項１に記載の発明は、光を透過する基板の上面に形成した透明電極に、半導体素子に形成した突起状の電極であるバンプを、異方導電性フィルムを介して導通接続する半導体素子の接合方法において、前記透明電極に前記異方導電性フィルムを転写し、前記バンプを前記透明電極に載置し、光を前記基板の下方から前記透明電極の周囲部分に照射し、前記異方導電性フィルムを硬化させ壁部を形成し、前記半導体素子を押圧し、前記異方導電性フィルムを硬化させることを特徴とする半導体素子の接合方法としたものであり、壁部を形成することにより、半導体素子と基板の接合に際して、半導体素子のバンプと基板の透明電極の間に、充分な導電性粒子の数を確保することができる。   According to the first aspect of the present invention, a bump, which is a protruding electrode formed on a semiconductor element, is conductively connected via a anisotropic conductive film to a transparent electrode formed on an upper surface of a substrate that transmits light. In the semiconductor element bonding method, the anisotropic conductive film is transferred to the transparent electrode, the bumps are placed on the transparent electrode, light is irradiated from below the substrate to the peripheral portion of the transparent electrode, An anisotropic conductive film is cured to form a wall portion, the semiconductor element is pressed, and the anisotropic conductive film is cured. By doing so, a sufficient number of conductive particles can be ensured between the bumps of the semiconductor element and the transparent electrode of the substrate when the semiconductor element and the substrate are bonded.

請求項２に記載の発明は、前記透明電極の下面にメッキ加工を施し、前記基板の下方から光を前記透明電極の周囲部分にのみ照射する際は、前記透明電極も含めて照射することを特徴とする請求項１記載の半導体素子の接合方法としたものであり、透明電極の下面にメッキ加工を施すことにより、光の照射を、透明電極を含む透明電極の周辺部分とすることができる。   In the invention according to claim 2, when the lower surface of the transparent electrode is plated, and light is irradiated only from the lower side of the substrate to the peripheral portion of the transparent electrode, the transparent electrode is also irradiated. The semiconductor element bonding method according to claim 1, wherein the irradiation of light can be performed on a peripheral portion of the transparent electrode including the transparent electrode by plating the lower surface of the transparent electrode. .

請求項３に記載の発明は、前記光を前記基板の下方から前記透明電極の周囲部分のみ照射する際に、前記透明電極の周囲部分に光を通過させる壁部形成孔を有する遮断板を前記基板と光源との間に介在させ、前記光を照射することを特徴とする請求項１記載の半導体素子の接合方法としたものであり、基板と光源の間に遮断板を介在させることにより、光の照射に局所的な制御を必要せず、壁部を形成できる。   According to a third aspect of the present invention, there is provided a blocking plate having a wall forming hole that allows light to pass through the peripheral portion of the transparent electrode when only the peripheral portion of the transparent electrode is irradiated from below the substrate. The semiconductor element bonding method according to claim 1, wherein the light is irradiated by interposing between a substrate and a light source, and by interposing a blocking plate between the substrate and the light source, The wall can be formed without requiring local control for light irradiation.

請求項４に記載の発明は、前記遮断板の前記壁部形成孔に、前記光を通過させない遮断部を有したことを特徴とする請求項３記載の半導体素子の接合方法としたものであり、半導体素子の押圧により、バンプが壁部内に侵入しても、遮断部を有した壁部形成孔により遮断板への光の照射によって、透明電極の周囲部分に一側面が開口した壁部を形成することにより、壁部の開口した一側面から樹脂や導電粒子が流れ出ることで、バンプが壁部内に挿入したときの内部圧力の増加を抑制することができる。   According to a fourth aspect of the present invention, there is provided the semiconductor element bonding method according to the third aspect, wherein the wall forming hole of the blocking plate has a blocking portion that does not allow the light to pass through. Even if the bumps penetrate into the wall due to the pressure of the semiconductor element, the wall part having a side surface opened in the peripheral part of the transparent electrode by irradiating the light to the shielding plate through the wall part forming hole having the shielding part By forming the resin and the conductive particles from the side surface where the wall portion is opened, an increase in internal pressure when the bump is inserted into the wall portion can be suppressed.

請求項５に記載の発明は、前記壁部を形成し、前記半導体素子を押圧した後に、前記異方導電性フィルムを硬化させる時には、基板の下方から前記光を前記基板の異方導電性フィルムが転写された範囲を含む領域に前記光を照射し、前記半導体素子および前記基板を加熱することを特徴とする請求項１から４いずれかに記載の半導体素子の接合方法としたものであり、半導体素子の接合に要する時間を短くすることができる。   In the invention according to claim 5, when the anisotropic conductive film is cured after the wall portion is formed and the semiconductor element is pressed, the light is transmitted from below the substrate from the anisotropic conductive film of the substrate. The semiconductor element bonding method according to claim 1, wherein the semiconductor element and the substrate are heated by irradiating the region including the area where the light is transferred, and heating the semiconductor element and the substrate. The time required for bonding the semiconductor elements can be shortened.

（実施の形態１）
本発明の実施の形態１に係る半導体素子の接合方法について、図１から図３および図１０に基づいて説明する。 (Embodiment 1)
A semiconductor element bonding method according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 3 and FIG.

図１は、本発明の実施の形態１に係る半導体素子の接合方法の構成を説明する図である。図２は、本発明の実施の形態１に係る半導体素子の接合方法の説明図である。図３は、実施の形態１に係る半導体素子の接合方法によりガラス基板に形成した壁部の部分拡大底面図である。図１０は、基板の平面図およびその部分拡大図である。   FIG. 1 is a diagram illustrating a configuration of a semiconductor element bonding method according to the first embodiment of the present invention. FIG. 2 is an explanatory diagram of the semiconductor element bonding method according to the first embodiment of the present invention. FIG. 3 is a partially enlarged bottom view of the wall portion formed on the glass substrate by the semiconductor element bonding method according to the first embodiment. FIG. 10 is a plan view of the substrate and a partially enlarged view thereof.

図１０において、基板の一例である液晶パネルに使用するガラス基板１の片側端部に透明電極２が形成されている。透明電極２は、インジウム錫酸化物（Indium Tin Oxide）で形成されている。透明電極２は、縦８０μｍ、横２３μｍの矩形状に形成され、隣接する透明電極２の間は１５μｍである。透明電極２は導通線（図示せず）により液晶パネルの各部へ接続されている。   In FIG. 10, the transparent electrode 2 is formed in the one side edge part of the glass substrate 1 used for the liquid crystal panel which is an example of a board | substrate. The transparent electrode 2 is made of indium tin oxide. The transparent electrode 2 is formed in a rectangular shape having a length of 80 μm and a width of 23 μm, and the distance between adjacent transparent electrodes 2 is 15 μm. The transparent electrode 2 is connected to each part of the liquid crystal panel by a conductive line (not shown).

図１において、ガラス基板１に形成された透明電極２に接合する半導体素子３は、パッド４と、パッド４に形成された突起状電極であるバンプ５を有している。半導体素子３とガラス基板１とは、異方導電性フィルム６を介して接合される。   In FIG. 1, a semiconductor element 3 bonded to a transparent electrode 2 formed on a glass substrate 1 has a pad 4 and a bump 5 that is a protruding electrode formed on the pad 4. The semiconductor element 3 and the glass substrate 1 are joined via an anisotropic conductive film 6.

異方導電性フィルム６は、接着剤の役目をする、例えば紫外線硬化性の触媒を含有した樹脂７に、プラスチック粒子のコアに導電性のあるＮｉやＡｕのメッキを施した導電粒子８を含有している。紫外線硬化性の触媒を含有した樹脂７は、ガラス基板１の下方より１００〜３００ｍＷ／ｃｍ2程度の出力の紫外線１１を照射することにより、５秒から１０秒で半硬化する。 The anisotropic conductive film 6 contains conductive particles 8 in which a plastic particle core is plated with conductive Ni or Au on a resin 7 containing an ultraviolet curable catalyst, for example, serving as an adhesive. doing. The resin 7 containing the ultraviolet curable catalyst is semi-cured in 5 to 10 seconds by irradiating the ultraviolet ray 11 having an output of about 100 to 300 mW / cm 2 from below the glass substrate 1.

紫外線１１は、例えば紫外線照射装置（図示せず）を光源とし、局所的に照射する場所が制御可能な光線である。この紫外線１１を照射して壁部９を形成する。   The ultraviolet ray 11 is a light beam that can control the location of irradiation locally using, for example, an ultraviolet irradiation device (not shown) as a light source. The wall portion 9 is formed by irradiating the ultraviolet rays 11.

次に、実施の形態１に係る半導体素子の接合方法について図２に基づいて説明をする。図２は、実施の形態１に係る半導体素子の接合方法の説明図である。   Next, the semiconductor element bonding method according to the first embodiment will be described with reference to FIG. FIG. 2 is an explanatory diagram of the semiconductor element bonding method according to the first embodiment.

まず、透明電極２を含むガラス基板１の透明電極２を含む範囲の上面に異方導電性フィルム６を加熱して転写する（同図（ａ））。   First, the anisotropic conductive film 6 is heated and transferred to the upper surface of the glass substrate 1 including the transparent electrode 2 in a range including the transparent electrode 2 ((a) in the figure).

次に、半導体素子３をバンプ５と透明電極２の位置を合わせて載置する。この時点では、まだ、押圧していないため、バンプ５と透明電極２との間には僅かながら隙間がある（同図（ｂ））。   Next, the semiconductor element 3 is placed with the bumps 5 and the transparent electrodes 2 aligned. At this point in time, there is a slight gap between the bump 5 and the transparent electrode 2 because it has not yet been pressed ((b) in the figure).

そして、ガラス基板１の下方より透明電極２の外周から透明電極２、２間の１／２の距離までの範囲に対し紫外線１１を照射する。すなわち、透明電極２、２間は１５μｍなので、透明電極２の外周約７μｍの矩形状の範囲に紫外線１１を照射するということである。従って、紫外線１１が照射された透明電極２の外周から約７μｍの周囲部分の異方導電性フィルム６の樹脂７が硬化し、透明電極２を囲うよう上面に開口部１０を有する水平断面が矩形の筒状の壁部９が形成される。壁部９は、ガラス基板１の下方から紫外線１１を照射するので、樹脂７内にて徐々に紫外線１１の照度が減衰していくため、壁部９の側面は、垂直断面が三角形状となる（同図（ｃ））。   Then, the ultraviolet rays 11 are applied to the range from the outer periphery of the transparent electrode 2 to the half distance between the transparent electrodes 2 and 2 from below the glass substrate 1. That is, since the space between the transparent electrodes 2 and 15 is 15 μm, the ultraviolet light 11 is irradiated to a rectangular area of about 7 μm on the outer periphery of the transparent electrode 2. Accordingly, the resin 7 of the anisotropic conductive film 6 around 7 μm from the outer periphery of the transparent electrode 2 irradiated with the ultraviolet rays 11 is cured, and the horizontal cross section having the opening 10 on the upper surface so as to surround the transparent electrode 2 is rectangular. A cylindrical wall portion 9 is formed. Since the wall portion 9 irradiates the ultraviolet rays 11 from below the glass substrate 1, the illuminance of the ultraviolet rays 11 gradually attenuates in the resin 7, and the side surface of the wall portion 9 has a triangular cross section. (FIG. (C)).

図３に、ガラス基板１に形成した壁部９の部分拡大底面図を示す。   In FIG. 3, the partial expanded bottom view of the wall part 9 formed in the glass substrate 1 is shown.

なお、図３においては、便宜上、ガラス基板１の図示は省略してある。   In addition, in FIG. 3, illustration of the glass substrate 1 is abbreviate | omitted for convenience.

透明電極２の周囲部分に壁部９が矩形状に形成されている。壁部９は、透明電極２を囲むように形成されるので、導電粒子８は壁部９の内側に確保された状態となる。   A wall portion 9 is formed in a rectangular shape around the transparent electrode 2. Since the wall 9 is formed so as to surround the transparent electrode 2, the conductive particles 8 are secured inside the wall 9.

図２（ｃ）に戻って、半導体素子３をヒートツール２９により押圧する。半導体素子３を押圧することにより、バンプ５は、透明電極２との隙間にあった導電粒子８を捕獲し、壁部９内にあった樹脂７は、バンプ５が壁部９に挿入されることにより壁部９の開口部１０から溢れる。この時、導電粒子８は樹脂７より比重が重いので、壁部９の開口部１０から溢れることはない（同図（ｃ））。   Returning to FIG. 2C, the semiconductor element 3 is pressed by the heat tool 29. By pressing the semiconductor element 3, the bump 5 captures the conductive particles 8 in the gap with the transparent electrode 2, and the resin 7 in the wall portion 9 is inserted into the wall portion 9. This overflows from the opening 10 of the wall 9. At this time, since the specific gravity of the conductive particles 8 is heavier than that of the resin 7, the conductive particles 8 do not overflow from the opening 10 of the wall 9 ((c) in the same figure).

ガラス基板１の下方より異方導電性フィルム６を転写した範囲を含む領域に紫外線１２を照射する。紫外線１２は、広い範囲に照射するので、紫外線１１のように局所的に照射する位置を制御する必要はなく、高圧水銀ランプでも照射が可能である。この紫外線１２の照射により、異方導電性フィルム６の樹脂７が硬化し、半導体素子３とガラス基板１が固着し、バンプ５と透明電極２が導通接続する（同図（ｄ））。   The region including the range where the anisotropic conductive film 6 is transferred from below the glass substrate 1 is irradiated with ultraviolet rays 12. Since the ultraviolet rays 12 are irradiated over a wide range, it is not necessary to control the position of irradiation locally like the ultraviolet rays 11, and irradiation with a high-pressure mercury lamp is also possible. By the irradiation of the ultraviolet rays 12, the resin 7 of the anisotropic conductive film 6 is cured, the semiconductor element 3 and the glass substrate 1 are fixed, and the bump 5 and the transparent electrode 2 are conductively connected ((d) in the figure).

（実施の形態２）
本発明の実施の形態２に係る半導体素子の接合方法を図４に基づいて説明する。図４は、本発明の実施の形態２に係る半導体素子の接合方法の説明図である。なお、図４においては、ガラス基板１、半導体素子３、パッド４、バンプ５、異方導電性フィルム６、導電粒子８は図１と同様のものであるため、同符号を付して説明は省略する。 (Embodiment 2)
A semiconductor element bonding method according to the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is an explanatory diagram of a method for bonding semiconductor elements according to the second embodiment of the present invention. In FIG. 4, the glass substrate 1, the semiconductor element 3, the pad 4, the bump 5, the anisotropic conductive film 6, and the conductive particles 8 are the same as those in FIG. Omitted.

本発明の実施の形態２に係る半導体素子の接合方法は、実施の形態１の透明電極２の下面にメッキ２８を施し紫外線を遮断するようにしたものである。   In the semiconductor element bonding method according to the second embodiment of the present invention, the lower surface of the transparent electrode 2 according to the first embodiment is plated 28 to block ultraviolet rays.

メッキ透明電極１３は、ガラス基板１の表面をクロム等のメタルにてメッキを施し、表面にインジウム錫酸化物の透明電極２でコーティングしてあり、紫外線を透過しないようにしている。   The plated transparent electrode 13 is formed by plating the surface of the glass substrate 1 with a metal such as chromium and coating the surface with the transparent electrode 2 of indium tin oxide so as not to transmit ultraviolet rays.

紫外線１４は、メッキ透明電極１３の周囲部分とメッキ透明電極１３を含む範囲に、紫外線照射装置等（図示せず）により照射された光線である。   The ultraviolet ray 14 is a light beam irradiated by an ultraviolet irradiation device or the like (not shown) to a range including the peripheral portion of the plated transparent electrode 13 and the plated transparent electrode 13.

以下に本発明の実施の形態２に係る半導体素子の接合方法を説明する。   The semiconductor element bonding method according to the second embodiment of the present invention will be described below.

まず、異方導電性フィルム６を実施の形態１と同様にメッキ透明電極１３を含む範囲の上面に加熱して転写し、半導体素子３をバンプ５とメッキ透明電極１３の位置を合わせて載置する。そして、ガラス基板１の下方よりメッキ透明電極１３を含む周囲部分に対し紫外線１４を照射し壁部２７を形成する。   First, the anisotropic conductive film 6 is heated and transferred onto the upper surface including the plated transparent electrode 13 in the same manner as in the first embodiment, and the semiconductor element 3 is placed with the bumps 5 and the plated transparent electrode 13 aligned. To do. And the ultraviolet-ray 14 is irradiated with respect to the surrounding part containing the plating transparent electrode 13 from the downward direction of the glass substrate 1, and the wall part 27 is formed.

そして、半導体素子３をヒートツールにより加熱、押圧し、硬化させる。   Then, the semiconductor element 3 is heated and pressed with a heat tool to be cured.

この接合方法においては、透明電極の下面にメッキを施すことにより、紫外線１４を局所的に照射する制御が簡易となる。   In this joining method, the control of locally irradiating the ultraviolet rays 14 is simplified by plating the lower surface of the transparent electrode.

（実施の形態３）
本発明の実施の形態３に係る半導体素子の接合方法を図５から図７に基づいて説明する。図５は、本発明の実施の形態３に係る半導体素子の接合方法の説明図である。図６は、紫外線をマスクする遮断板の部分拡大平面図である。図７は、本発明の実施の形態３に係る半導体素子の接合方法の説明図である。 (Embodiment 3)
A semiconductor element bonding method according to the third embodiment of the present invention will be described with reference to FIGS. FIG. 5 is an explanatory diagram of a method for bonding semiconductor elements according to the third embodiment of the present invention. FIG. 6 is a partially enlarged plan view of a blocking plate that masks ultraviolet rays. FIG. 7 is an explanatory diagram of a method for bonding semiconductor elements according to the third embodiment of the present invention.

なお、図５から図７においては、ガラス基板１、透明電極２、半導体素子３、パッド４、バンプ５、異方導電性フィルム６、導電粒子８、紫外線１２は図１と同様のものであるため、同符号を付して説明は省略する。   5 to 7, the glass substrate 1, the transparent electrode 2, the semiconductor element 3, the pad 4, the bump 5, the anisotropic conductive film 6, the conductive particles 8, and the ultraviolet rays 12 are the same as those in FIG. Therefore, the same reference numerals are given and the description is omitted.

本発明の実施の形態３に係る半導体素子の接合方法は、実施の形態１の紫外線照射装置による局所的に照射とせず、紫外線を透過させない遮断板を使用して照射する範囲を限定するものである。   The semiconductor element bonding method according to the third embodiment of the present invention limits the range of irradiation using a blocking plate that does not transmit ultraviolet light locally and is not locally irradiated by the ultraviolet irradiation device of the first embodiment. is there.

図５において、ガラス基板１の下方から紫外線１２を照射する光源（図示せず）とガラス基板１との間に、紫外線１２を透過しない遮断板１５を介在させて照射している。   In FIG. 5, irradiation is performed with a shielding plate 15 that does not transmit ultraviolet light 12 interposed between a light source (not shown) that emits ultraviolet light 12 and the glass substrate 1 from below the glass substrate 1.

図６において、遮断板１５は、ガラス基板１の異方導電性フィルム６を転写した範囲の紫外線１２を遮断する基板遮断部１６と、透明電極２の周囲部分と透明電極２を含む範囲に照射された紫外線１２を通過させる貫通孔１７と、透明電極２に対し紫外線１２を遮断する電極遮断部１８と、基板遮断部１６と電極遮断部１８に接続されている接続部１９から構成される。   In FIG. 6, the blocking plate 15 irradiates a range including the substrate blocking portion 16 that blocks the ultraviolet rays 12 in the range where the anisotropic conductive film 6 of the glass substrate 1 is transferred, and the transparent electrode 2 and the surrounding portion. The through hole 17 through which the ultraviolet ray 12 passes, the electrode blocking part 18 blocking the ultraviolet ray 12 with respect to the transparent electrode 2, and the connection part 19 connected to the substrate blocking part 16 and the electrode blocking part 18.

貫通孔１７と電極遮断部１８は矩形状をしており、貫通孔１７は、透明電極２および透明電極２の周囲部分を含む範囲の形状に形成されており、電極遮断部１８は、透明電極２と同じ矩形状で同面積に形成している。   The through hole 17 and the electrode blocking part 18 have a rectangular shape, and the through hole 17 is formed in a shape that includes the transparent electrode 2 and the peripheral part of the transparent electrode 2. 2 and the same area.

接続部１９は、基板遮断部１６と電極遮断部１８を接続しており、紫外線１２を遮断するため、影響を最小限とするため、１０μｍ以下程度の幅で形成されている。   The connection portion 19 connects the substrate blocking portion 16 and the electrode blocking portion 18 and is formed with a width of about 10 μm or less in order to block the ultraviolet rays 12 and minimize the influence.

貫通孔１７と電極遮断部１８と接続部１９により、紫外線１２を通過させる穴は、略Ｃ字状の壁部形成孔２０となっている。   The through-hole 17, the electrode blocking portion 18, and the connecting portion 19 allow the ultraviolet ray 12 to pass therethrough as a substantially C-shaped wall portion forming hole 20.

壁部２１は、壁部形成孔２０に、紫外線１２を通過させて異方導電性フィルム６を硬化させることにより形成される。壁部２１は、接続部１９を１０μｍ以下程度の幅で形成することにより、接続部１９の投影部分も紫外線１２で異方導電性フィルム６が硬化するので、透明電極２を囲った上面に開口部２２を有する水平断面が矩形の筒状に形成される。   The wall portion 21 is formed by allowing the ultraviolet ray 12 to pass through the wall portion forming hole 20 and curing the anisotropic conductive film 6. The wall portion 21 is formed on the upper surface surrounding the transparent electrode 2 because the anisotropic conductive film 6 is cured by the ultraviolet rays 12 in the projection portion of the connection portion 19 by forming the connection portion 19 with a width of about 10 μm or less. A horizontal section having the portion 22 is formed in a rectangular cylindrical shape.

次に、本発明の実施の形態３に係る半導体素子の接合方法を図７に基づいて説明する。   Next, a semiconductor element bonding method according to the third embodiment of the present invention will be described with reference to FIG.

図７は、本発明の実施の形態３に係る半導体素子の接合方法を説明する図である。   FIG. 7 is a diagram for explaining a semiconductor element bonding method according to the third embodiment of the present invention.

まず、ガラス基板１の表面に形成された透明電極２の上面に異方導電性フィルム６を転写する（同図（ａ））。   First, the anisotropic conductive film 6 is transcribe | transferred on the upper surface of the transparent electrode 2 formed in the surface of the glass substrate 1 (the figure (a)).

次に、半導体素子３をバンプ５と透明電極２の位置を合わせて載置する。この時点では、まだ、押圧していないため、バンプ５と透明電極２との間には僅かながら隙間がある（同図（ｂ））。   Next, the semiconductor element 3 is placed with the bumps 5 and the transparent electrodes 2 aligned. At this point in time, there is a slight gap between the bump 5 and the transparent electrode 2 because it has not yet been pressed ((b) in the figure).

そして、ガラス基板１と紫外線１２の光源との間に、遮断板１５を挿入する。この時に、紫外線１２の光源から電極遮断部１８の投影面が透明電極２となるように配設する。ガラス基板１の下方より紫外線１２を照射する。紫外線１２は、遮断板１５により、壁部形成孔２０以外は光が通過しない。壁部形成孔２０により通過した紫外線１２は、異方導電性フィルム６が部分的に半硬化して壁部２１を形成する。次に、半導体素子３をヒートツール２９により押圧する。半導体素子３を押圧することにより、バンプ５は、透明電極２との隙間にあった導電粒子８を捕獲し、壁部２１内にあった樹脂７は、バンプ５が壁部２１に侵入することにより壁部２１の開口部２２から溢れる。この時、導電粒子８は樹脂７より比重が重いので、壁部２１の開口部２２から溢れることはない（同図（ｃ））。   Then, a blocking plate 15 is inserted between the glass substrate 1 and the ultraviolet light source 12. At this time, it arrange | positions so that the projection surface of the electrode interruption | blocking part 18 may become the transparent electrode 2 from the light source of the ultraviolet-ray 12. FIG. Ultraviolet rays 12 are irradiated from below the glass substrate 1. The ultraviolet rays 12 do not pass through the blocking plate 15 except for the wall forming holes 20. The ultraviolet rays 12 that have passed through the wall forming hole 20 are partially semi-cured by the anisotropic conductive film 6 to form the wall 21. Next, the semiconductor element 3 is pressed by the heat tool 29. By pressing the semiconductor element 3, the bump 5 captures the conductive particles 8 in the gap with the transparent electrode 2, and the resin 7 in the wall 21 causes the bump 5 to enter the wall 21. Overflows from the opening 22 of the wall 21. At this time, since the specific gravity of the conductive particles 8 is heavier than that of the resin 7, the conductive particles 8 do not overflow from the opening 22 of the wall portion 21 ((c) in the figure).

最後に、遮断板１５を取り除くことで、ガラス基板１の異方導電性フィルム６を転写した範囲を含む領域に紫外線１２が照射されるので、異方導電性フィルム６の樹脂７が硬化し、半導体素子３とガラス基板１が固着し、バンプ５と透明電極２が導通接続する（同図（ｄ））。   Finally, by removing the blocking plate 15, the region 12 including the range where the anisotropic conductive film 6 of the glass substrate 1 is transferred is irradiated with ultraviolet rays 12, so that the resin 7 of the anisotropic conductive film 6 is cured, The semiconductor element 3 and the glass substrate 1 are fixed, and the bump 5 and the transparent electrode 2 are conductively connected ((d) in the figure).

なお、本実施の形態３では、遮断板１５の接続部１９は、１箇所で基板遮断部１６と電極遮断部１８を接続していたが、２箇所以上であっても、接続部１９の幅が１０μｍ〔単位〕程度以下であれば良い。   In the third embodiment, the connection portion 19 of the blocking plate 15 connects the substrate blocking portion 16 and the electrode blocking portion 18 at one location, but the width of the connection portion 19 is not limited to two or more locations. May be about 10 μm [unit] or less.

（実施の形態４）
本発明の実施の形態４に係る半導体素子の接合方法を図８および図９に基づいて説明する。図８は、本発明の実施の形態４に係る半導体素子の接合方法の遮断板の部分拡大平面図である。図９は、本発明の実施の形態４に係る半導体素子の接合方法によりガラス基板に形成した壁部の底面図である。なお、図９においては、便宜上ガラス基板の図示は省略してある。 (Embodiment 4)
A semiconductor element bonding method according to Embodiment 4 of the present invention will be described with reference to FIGS. FIG. 8 is a partially enlarged plan view of the blocking plate of the semiconductor element bonding method according to the fourth embodiment of the present invention. FIG. 9 is a bottom view of the wall portion formed on the glass substrate by the semiconductor element bonding method according to the fourth embodiment of the present invention. In addition, in FIG. 9, illustration of the glass substrate is abbreviate | omitted for convenience.

本発明の実施の形態４に係る半導体素子の接合方法は、実施の形態３の遮断板について、電極遮断部と基板遮断部を接続する接続部の幅を透明電極と同じ幅とした開放部とすることで、壁部の水平断面を略コ字状とするものである。   In the semiconductor element bonding method according to the fourth embodiment of the present invention, the open portion in which the width of the connection portion connecting the electrode blocking portion and the substrate blocking portion is the same as that of the transparent electrode in the blocking plate of the third embodiment. By doing so, the horizontal cross section of the wall portion is substantially U-shaped.

図８において、基板遮断部１６、貫通孔１７、電極遮断部１８は、図６と同様であり、図９において、バンプ５、樹脂７、導電粒子８は図１と同様のものであるため、同符号を付して説明は省略する。   In FIG. 8, the substrate blocking part 16, the through hole 17, and the electrode blocking part 18 are the same as in FIG. 6. In FIG. 9, the bump 5, the resin 7, and the conductive particles 8 are the same as in FIG. The same reference numerals are given and description thereof is omitted.

図８に示すように、遮断板２３は、基板遮断部１６と、貫通孔１７と、電極遮断部１８を有しており、基板遮断部１６と電極遮断部１８は、開放部２４により接続されている。   As shown in FIG. 8, the blocking plate 23 has a substrate blocking portion 16, a through hole 17, and an electrode blocking portion 18, and the substrate blocking portion 16 and the electrode blocking portion 18 are connected by an open portion 24. ing.

開放部２４は、矩形状をしており、電極遮断部１８と同一の幅で形成されている。   The open part 24 has a rectangular shape and is formed with the same width as the electrode blocking part 18.

貫通孔１７と電極遮断部１８と開放部２４により、紫外線１２を通過させる孔は、略コ字状の壁部形成孔２５としている。壁部形成孔２５の開放部２４は、隣接した壁部形成孔２５側ではない位置に設けられている。   The through-hole 17, the electrode blocking part 18, and the open part 24 allow the ultraviolet ray 12 to pass therethrough as a substantially U-shaped wall part forming hole 25. The open portion 24 of the wall portion forming hole 25 is provided at a position that is not adjacent to the wall portion forming hole 25 side.

図９において、壁部２６は、壁部形成孔２５に、紫外線１２を通過させて異方導電性フィルム６を硬化させることにより、上面および一側面が開口した水平断面が略コ字の筒状に形成される。また、壁部２６の開口した一側面は、隣接した透明電極２側ではない方向に形成される。   In FIG. 9, the wall portion 26 is a cylindrical shape having a substantially U-shaped horizontal cross section with an upper surface and one side surface opened by allowing the ultraviolet ray 12 to pass through the wall forming hole 25 and curing the anisotropic conductive film 6. Formed. Further, the opened side surface of the wall portion 26 is formed in a direction other than the adjacent transparent electrode 2 side.

次に、本実施の形態４に係る半導体素子の接合方法であるが、実施の形態３と同様に行うことができる。   Next, a semiconductor element bonding method according to the fourth embodiment can be performed in the same manner as in the third embodiment.

この壁部２６を用いた半導体素子の接合方法では、半導体素子を載置し加熱、押圧した時点で、バンプ５の壁部２６内への挿入により、樹脂７および導電粒子８が、開口した一側面から流れ出る。しかし、壁部２６が隣接した透明電極２側に開口していないため、隣接するバンプ５同士の間に導電粒子８が数珠つながりになって、短絡することがない。   In this semiconductor element bonding method using the wall portion 26, when the semiconductor element is placed, heated, and pressed, the resin 7 and the conductive particles 8 are opened by insertion of the bump 5 into the wall portion 26. It flows out from the side. However, since the wall portion 26 does not open to the adjacent transparent electrode 2 side, the conductive particles 8 are connected in a row between the adjacent bumps 5 so as not to be short-circuited.

なお、本実施の形態においては、遮断板２３に形成した全ての壁部形成孔２５の開放部２４を同一の方向に形成したが、隣接した壁部形成孔２５側ではない方向へ設ければ良いため、必ずしも、壁部形成孔２５の開放部２４を同一方向に形成する必要はない。   In the present embodiment, the opening portions 24 of all the wall portion forming holes 25 formed in the blocking plate 23 are formed in the same direction, but if provided in a direction other than the adjacent wall portion forming hole 25 side. For this reason, it is not always necessary to form the opening 24 of the wall forming hole 25 in the same direction.

（実施の形態５）
本発明の実施の形態５に係る半導体素子の接合方法は、半導体素子とガラス基板との固着に際し、紫外線を照射した後に、半導体素子とガラス基板を加熱し異方導電性フィルムを硬化させる。 (Embodiment 5)
In the semiconductor element bonding method according to Embodiment 5 of the present invention, when the semiconductor element and the glass substrate are fixed, after the ultraviolet ray is irradiated, the semiconductor element and the glass substrate are heated to cure the anisotropic conductive film.

本実施の形態の異方導電性フィルムは、例えば、光硬化特性を有するラジカル重合型アクリレート樹脂または、光や熱でカチオン重合するエポキシ樹脂の併用硬化型である。   The anisotropic conductive film of the present embodiment is, for example, a radical curing type acrylate resin having photocuring characteristics or a combined curing type of an epoxy resin that is cationically polymerized by light or heat.

以下に本実施の形態の半導体素子の接合方法について説明する。   The semiconductor element bonding method of this embodiment will be described below.

実施の形態１から４の半導体素子の接合方法によって、異方導電性フィルムを転写したガラス基板に壁部を形成する。そして、ガラス基板の下方から異方導電性フィルムを転写した範囲を含む領域に紫外線を照射して異方導電性フィルムを部分的に半硬化させる。最後に、ヒートツールで半導体素子を加熱、加圧して、異方導電性フィルムを硬化させる。   A wall portion is formed on the glass substrate to which the anisotropic conductive film is transferred by the semiconductor element bonding method according to the first to fourth embodiments. And an ultraviolet-ray is irradiated to the area | region containing the range which transcribe | transferred the anisotropic conductive film from the downward direction of the glass substrate, and an anisotropic conductive film is partially semi-hardened. Finally, the semiconductor element is heated and pressurized with a heat tool to cure the anisotropic conductive film.

このように、加熱処理にて異方導電性フィルムの樹脂を硬化させるので、光硬化よりも早く固着されることができるため、半導体素子の接合作業時間を短縮することができる。   Thus, since the resin of the anisotropic conductive film is cured by heat treatment, it can be fixed faster than photocuring, so that the semiconductor device bonding operation time can be shortened.

本発明の半導体素子の接合方法は、液晶パネルを構成するガラス基板上に、半導体素子を異方導電性フィルムを用いてフェイスダウンする方法として有用であり、特にガラス基板上に形成された透明電極に、半導体素子に形成されたバンプを接続するのに適している。   The semiconductor element bonding method of the present invention is useful as a method of face-downing a semiconductor element using an anisotropic conductive film on a glass substrate constituting a liquid crystal panel, and in particular, a transparent electrode formed on a glass substrate. Moreover, it is suitable for connecting bumps formed on the semiconductor element.

本発明の実施の形態１に係る半導体素子の接合方法の構成を説明する図The figure explaining the structure of the joining method of the semiconductor element which concerns on Embodiment 1 of this invention. 実施の形態１に係る半導体素子の接合方法の説明図Explanatory drawing of the joining method of the semiconductor element concerning Embodiment 1 実施の形態１に係る半導体素子の接合方法によりガラス基板に形成した壁部の部分拡大底面図The partially expanded bottom view of the wall part formed in the glass substrate by the joining method of the semiconductor element concerning Embodiment 1 本発明の実施の形態２に係る半導体素子の接合方法の説明図Explanatory drawing of the joining method of the semiconductor element which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体素子の接合方法の説明図Explanatory drawing of the joining method of the semiconductor element which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る半導体素子の接合方法の遮断板の部分拡大平面図The elements on larger scale of the shielding board of the semiconductor element joining method concerning Embodiment 3 of this invention 本発明の実施の形態３に係る半導体素子の接合方法の説明図Explanatory drawing of the joining method of the semiconductor element which concerns on Embodiment 3 of this invention. 本発明の実施の形態４に係る半導体素子の接合方法の遮断板の部分拡大平面図The elements on larger scale of the shielding board of the semiconductor element joining method concerning Embodiment 4 of this invention 実施の形態４に係る半導体素子の接合方法によりガラス基板に形成した壁部の底面図The bottom view of the wall part formed in the glass substrate by the joining method of the semiconductor element concerning Embodiment 4 基板の平面図およびその部分拡大図Plan view of substrate and partial enlarged view thereof

符号の説明Explanation of symbols

１ ガラス基板
２ 透明電極
３ 半導体素子
４ パッド
５ バンプ
６ 異方導電性フィルム
７ 樹脂
８ 導電粒子
９ 壁部
１０ 開口部
１１ 紫外線
１２ 紫外線
１３ メッキ透明電極
１４ 紫外線
１５ 遮断板
１６ 基板遮断部
１７ 貫通孔
１８ 電極遮断部
１９ 接続部
２０ 壁部形成孔
２１ 壁部
２２ 開口部
２３ 遮断板
２４ 開放部
２５ 壁部形成孔
２６ 壁部
２７ 壁部
２８ メッキ
２９ ヒートツール DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Transparent electrode 3 Semiconductor element 4 Pad 5 Bump 6 Anisotropic conductive film 7 Resin 8 Conductive particle 9 Wall part 10 Opening part 11 Ultraviolet 12 Ultraviolet 13 Plating transparent electrode 14 Ultraviolet 15 Blocking board 16 Substrate blocking part 17 Through-hole DESCRIPTION OF SYMBOLS 18 Electrode block part 19 Connection part 20 Wall part formation hole 21 Wall part 22 Opening part 23 Blocking plate 24 Opening part 25 Wall part formation hole 26 Wall part 27 Wall part 28 Plating 29 Heat tool

Claims (5)

光を透過する基板の上面に形成した透明電極に、半導体素子に形成した突起状の電極であるバンプを、異方導電性フィルムを介して導通接続する半導体素子の接合方法において、前記透明電極に前記異方導電性フィルムを転写し、前記バンプを前記透明電極に載置し、光を前記基板の下方から前記透明電極の周囲部分に照射し、前記異方導電性フィルムを硬化させ壁部を形成し、前記半導体素子を押圧し、前記異方導電性フィルムを硬化させることを特徴とする半導体素子の接合方法。 In a method for bonding a semiconductor element in which a bump, which is a protruding electrode formed on a semiconductor element, is electrically connected to a transparent electrode formed on an upper surface of a substrate that transmits light via an anisotropic conductive film, The anisotropic conductive film is transferred, the bumps are placed on the transparent electrode, light is irradiated from below the substrate to the peripheral portion of the transparent electrode, the anisotropic conductive film is cured, and the wall portion is A method for bonding semiconductor elements, comprising forming, pressing the semiconductor elements, and curing the anisotropic conductive film. 前記透明電極の下面にメッキ加工を施し、前記基板の下方から光を前記透明電極の周囲部分にのみ照射する際は、前記透明電極も含めて照射することを特徴とする請求項１記載の半導体素子の接合方法。 2. The semiconductor according to claim 1, wherein the lower surface of the transparent electrode is plated, and when the light is irradiated only from a lower portion of the substrate to the peripheral portion of the transparent electrode, the semiconductor includes the transparent electrode. Element joining method. 前記光を前記基板の下方から前記透明電極の周囲部分のみ照射する際に、前記透明電極の周囲部分に光を通過させる壁部形成孔を有する遮断板を前記基板と光源との間に介在させ、前記光を照射することを特徴とする請求項１記載の半導体素子の接合方法。 When irradiating only the peripheral portion of the transparent electrode from the lower side of the substrate, a shielding plate having a wall forming hole for allowing the light to pass through the peripheral portion of the transparent electrode is interposed between the substrate and the light source. The semiconductor element bonding method according to claim 1, wherein the light is irradiated. 前記遮断板の前記壁部形成孔に、前記光を通過させない遮断部を有したことを特徴とする請求項３記載の半導体素子の接合方法。 4. The semiconductor element bonding method according to claim 3, wherein the wall forming hole of the blocking plate has a blocking portion that does not allow the light to pass therethrough. 前記壁部を形成し、前記半導体素子を押圧した後に、前記異方導電性フィルムを硬化させる時には、基板の下方から前記光を前記基板の異方導電性フィルムが転写された範囲を含む領域に前記光を照射し、前記半導体素子および前記基板を加熱することを特徴とする請求項１から４のいずれかの項に記載の半導体素子の接合方法。 When the anisotropic conductive film is cured after the wall portion is formed and the semiconductor element is pressed, the light is applied from below the substrate to a region including a range where the anisotropic conductive film of the substrate is transferred. The semiconductor element bonding method according to claim 1, wherein the semiconductor element and the substrate are heated by irradiating the light.
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CN108369939A (en) * 2015-12-22 2018-08-03 英特尔公司 Semiconductor packages with electromagnetic interference shield

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