JP2005123935A - Data transmission method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To transmit essential data, e.g. audio data, while adding other data, e.g. a control signal or video data, intentionally as a jitter of the essential data. <P>SOLUTION: A transmission side apparatus T comprising a data generating section 1 outputting essential data (DATA) to be transmitted and clocks MCK, BCK and LRCK, and a section 2 for transmitting the essential data modulated by the clocks is provided with a modulating section 4 outputting an MCK including a jitter modulated by additional data Da, and data having a jitter is transmitted such that the time axis in the transmitting section 2 operates with clocks each having a jitter. A reception side apparatus R comprising a receiving section 5 having a primary PLL section 5a and obtaining the essential data, and a data using section 7 is provided with a demodulating section 8 for recovering the additional data Da from a received signal sync clock LRCK for data including the jitter, thus obtaining the additional data Da. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data transmission method for transmitting additional data as modulated jitter together with original data.

  Conventionally, in a digital audio data transmission system (IEC958, USB, UART, etc.) having a concept of a reference clock, as shown in FIG. 10, the transmission side device T includes a data generation unit 1, a digital audio interface device (transmission unit). ) 2 etc. The receiving device R includes a digital audio interface device (reception unit) 5 having a built-in or external PLL (phase-locked loop) 5a, a DAC (D / A converter), a DSP (digital signal processing processor), and the like. The audio data using unit 7 provided with

  The data generator 1 divides the digital audio data DATA, the main clock MCK, the bit clock BCK obtained by dividing the main lock MCK by 2 (or divided by 4 or 8), and the left and right obtained by dividing the bit clock BCK by 64. The transmitting unit 2 modulates the digital audio data DATA into the clock LRCK and transmits it in a predetermined transmission format.

  The receiving unit 5 receives the transmission in a predetermined transmission format, and outputs data DATA and clocks LRCK, BCK, and MCK to the audio data using unit 7, and the audio data using unit 7 uses these clocks to convert the digital data DATA to DAC. For example, convert it to an analog signal.

Usually, jitter (fluctuation) in digital audio data transmission has an adverse effect on sound quality, and therefore it has been directed to reduce jitter as much as possible. As a method for removing jitter, there is a clock generation circuit that follows the jitter of a signal including jitter (see, for example, Patent Document 1).
Japanese Patent No. 20800305 (column 4, FIG. 1).

  However, with regard to jitter in data transmission, there is often no definition as to whether or not an allowable range is defined in the transmission format, and it is not always necessary that jitter = 0, but conventionally, additional information or the like is transmitted using jitter. There was no idea.

  It is an object of the present invention to provide a data transmission method for intentionally adding data such as control signals and video data other than original data such as audio data as jitter of the original data.

  The data transmission method of the present invention intentionally adds jitter modulated to the reference clock in a system (IEC 958, USB, UART, etc.) that transmits digital data having the concept of a reference clock, thereby In addition, additional data is sent.

   In the data transmission method, the jitter size and frequency are within an allowable range in a transmission system format, the reference clock jitter is limited to a range that does not directly affect performance, and the jitter Even if the component is within the allowable range of the transmission format, the reference clock generated by the receiving device is passed through the narrow-band, low-gain secondary PLL unit, and the jitter component of the reference clock is almost completely removed. An error correction circuit is provided, the jitter is concentrated on one side of + or-, and the modulation method of the additional data does not have a DC component and / or a low frequency component so that the frequency of the reference clock does not shift, and the jitter is + or The modulation method of the additional data has a direct current component and a frequency so that the frequency of the reference clock does not shift. / Or having no low-frequency components, such as is desirable.

Since the present invention intentionally adds modulated jitter to a reference clock in a system for transmitting digital data with the concept of a reference clock, thereby sending additional data in addition to the original data.
(1) Additional data can be reliably transmitted within the allowable range of the transmission format with a simple configuration without affecting the original performance of the device.
(2) Since the additional data is transmitted using fluctuations on the frequency axis, it is not affected by amplitude, duty, or the like.

  An embodiment of the present invention will be described with reference to FIGS. 1 is a schematic configuration diagram of a digital audio data transmission system according to an embodiment, FIG. 2 is a block circuit diagram showing a jitter generation unit, FIG. 4 is a block circuit diagram showing a jitter detection unit, and FIG. 7 shows a jitter determination unit. It is a block circuit diagram. In the figure, the same components as those in FIG.

(System configuration)
Referring to FIG. 1, the transmission side device T includes a data generation unit 1 that outputs digital audio data DATA obtained by converting an audio signal into data, a main clock MCK, a bit clock BCK, a left and right clock LRCK, and the data generation unit 1. And a digital audio interface device (transmitting unit) 2 that receives data BCLK, MCK, LRCK, etc. and transmits data modulated by LRCK, and additional data Da (for example, added to the data as a jitter component) The data generation unit (data for receiving audio device control) is generated, and an additional data generation unit (jitter addition device) 3 composed of a microcomputer or the like, and the clock MCK from the data generation unit 1 is modulated with the additional data Da and jitter is transmitted to the transmission unit 2 Modulator 4 that outputs a clock MCK with It is constructed from. A jitter generation unit that generates additional data as jitter is composed of an additional data generation unit (device for adding jitter) 3, a modulation unit 4 and the like (FIG. 2).

  In addition, the receiving side device R obtains the MCK without jitter from the digital audio interface device (receiving unit) 5 in which the primary PLL unit 5a is incorporated or externally attached and the LRCK with jitter from the receiving unit 5. Additional data from the PLL unit 6, the receiving unit 5 and the secondary PLL unit 6, the audio data using unit 7 including the DAC, DSP, etc. to which DATA, BCK, LRCK, MCK, etc. are input, It comprises a demodulator 8 that demodulates and a data processing / use unit 9 that comprises a microcomputer or the like that uses the additional data Da from the demodulator 8.

  A jitter detection unit for detecting and demodulating jitter included in the received signal to obtain additional data Da includes a secondary PLL unit 6, a demodulation unit (jitter + or-determination unit) 8, and the like. (FIG. 4).

  Note that jitter is added within an allowable range in the transmission format. In addition, if jitter is added to the data, there are problems such as an adverse effect on the sound and the primary PLL unit 5a of the receiving unit 5 not being locked. Therefore, the jitter band and magnitude can be followed by the primary PLL unit 5a. And Further, since data cannot be reproduced if LRCK, BCK, and DATA deviate by more than half BCK, the jitter is set to be at least that level. In the case of packet communication such as USB or block transfer, the bandwidth of the secondary PLL 6 is determined by the interval between each packet and block.

  Further, when the MCK for DAC or the like (the most important clock in terms of sound quality that determines the time axis of sound) created from the LRCK by the primary PLL unit 5a of the receiving unit 5 as shown in FIG. Therefore, the sound quality is greatly affected. In order to avoid this, an MCK without jitter is produced from the LRCK with jitter using the secondary PLL unit 6. For this reason, the secondary PLL unit 6 uses a characteristic that does not follow the jitter above the audible band, such as a band and a gain.

(Jitter generator)
As shown in FIG. 2, the jitter generation unit includes a jitter addition device 3, a modulation unit 4 for generating a clock MCK with jitter, and the like. The modulation unit 4 is a frequency dividing unit that uses a reference clock A (MCK) from a master clock transmission unit (crystal oscillator or the like) 11 in the data generation unit 1 as a PLL reference clock B obtained by dividing the reference clock A (MCK) to several Hz outside the audible band. 41, the reference clock B and the comparison clock E of the PLL are compared in phase and output a transmission control signal F, a narrow-band, low-gain PLL 42, and the jitter from the jitter addition device 3 to the transmission control signal F A MIX (mixer) 43 that mixes the component G (additional data Da), and a master clock transmission unit that outputs a master clock D including jitter controlled by a transmission control signal C to which the jitter component G from the MIX 43 is added. (VCF such as LC or RC) 44 and the master clock D including this jitter are divided to output a comparison clock signal E of the PLL 42. It is composed of 45. The master clock D including jitter is also supplied to the data original transmission device / clock generation unit 21 in the transmission unit 2.

  The operation of the jitter generator will be described with reference to FIG. The accuracy of the reference clock A (MCK) output from the master clock transmission unit 11 is the crystal transmission accuracy. The frequency is divided by the frequency divider 41 to several Hz outside the audible band, and used as the reference clock B of the PLL 42. Further, the master clock transmission unit 44 has a transmission control signal F that determines the transmission frequency with crystal accuracy output from the PLL 42, and a frequency that does not appear in the table at all if it is divided to several Hz from the jitter adding device 3. Since the master clock transmission unit 44 is controlled by the transmission control signal C in which both the jitter component signals G of the level are mixed by the MIX unit 43, the master clock D output from the master clock transmission unit 44 is a clock having jitter. (MCK). Since the master clock D having this jitter controls the clock generator of the data original transmission device / clock generator 21, all clocks have jitter, and the time axis in the transmitter 2 is all jitter. It operates with a clock with

  Therefore, the data signal H output from the original transmission device / clock generation unit 21 is also a data signal H to which jitter modulated by a clock (LRCK) having jitter is added, and is transmitted from the final output unit 22 as it is. However, the magnitude of this jitter is such that the input device on the receiving side and the device using the signal do not malfunction, that is, the PLL of the input device on the receiving side can be locked, and the output of the input device is set to the receiving side. And within a range (half BCK (128 Fs)) in which the jitter component can be repulsed.

(Jitter detector)
4, the original receiving device / clock generation primary PLL unit 51 is an input device in the receiving unit 2 that receives the input signal I and normally outputs a DATA signal, a BCK signal, an LRCK signal, and an MCK signal. The jitter detection unit is a data signal output from the input device 51 connected between the original receiving device / clock generation primary PLL unit (input device) 51 and the data use device (audio data use unit) 7. The D type FF block 52 for changing J (1-3) to a clean data signal L (1-3), the master clock 256Fs, etc. are divided to operate the FF block 52 with the clock signal K (128Fs). The frequency divider 53, the secondary PLL section 6 that generates the master clock 256Fs and the like from the synchronization signal (LRCK and the like) of the data signal output from the input device 51, and the LRCK or BCK signal M on the input side of the FF block 52 And jitter that detects additional data from the LRCK or BCK signal N on the output side of the FF block 52 + or− Tough and a (demodulator) 8.

  The secondary PLL section 6 is output from a frequency dividing section 61 that divides a synchronous clock (such as LRCK) of a data signal into several Hz, and a frequency dividing section 64 using the divided clock as a reference clock. A narrow-band, low-gain PLL 62 that compares the phases of a number of comparison clocks and outputs a transmission control signal, a CVF 63 that outputs a master clock 256Fs controlled by the transmission control signal, and a number of the master clock 256Fs. And a frequency divider 64 that divides the frequency into Hz and outputs the comparison clock. The configuration of the jitter + or−determination unit 8 will be described later.

  The operation of the jitter detector will be described with reference to FIG. When data including jitter is transmitted from the transmission unit 2, an input signal I including jitter is input to the primary PLL unit (input device) 51 for generating a receiving device clock, and the input signal including this jitter is input. I is locked by the primary PLL section (5a) of the input device 51, and a data signal J (1-3) with jitter (DATA, BCK, LRCK, etc.) is output from the input device 51. When this data signal synchronous clock (such as LRCK) is frequency-divided by the frequency divider 61 to several Hz, since the low frequency is not included in the jitter component from the beginning, a beautiful waveform without jitter is generated from the frequency divider 61. can get. Using this as a reference clock, a master clock (256 Fs, etc.) is created by a narrow-band, low-gain secondary PLL 6 (the master clock from the input device is not used). The main lock 256Fs and the like are frequency-divided by the frequency divider 53 to generate a clock K of 128Fs. With the clock K of 128 Fs, the D-type FF block 52 is latched at the rising edge of the data signal J (1-3) including jitter, and is re-applied to the signal L (1-3) that does not include clean jitter on the time axis. Yes. In this way, the data use device 9 such as a DAC or DSP can supply signals with a clear time axis, and there is no problem in sound quality.

  As can be seen from the waveform diagram of FIG. 5, when the jitter width is 128 Fs (1/2 BCK) or more, it becomes impossible to accurately align the time axis of the data signal, and the accuracy of the data can be guaranteed. Disappear.

  FIG. 6 shows the relationship between the gain and frequency of the primary PLL unit and the secondary PLL unit. Since the primary PLL section 5a is always locked to the input signal, the gain is large as shown by the curve a and the band is wide. Since the secondary PLL 6 is once locked by the primary PLL unit 5a and does not follow the audio signal band, the band is low and its gain is small as shown by the curve b. The hatched portion c is a portion that can be locked by the primary PLL unit 5a and the secondary PLL 6 does not follow, and indicates an area that can be used for transmission of the additional data Da. Note that the modulation method is not limited to the above, and can be used for various modulation methods.

(Jitter + or-judgment part)
7 and 8, the jitter + or−determining unit (demodulating unit) 8 in FIG. 4 is configured such that the LRCK or BCK signal M with jitter on the input side of the D-type FF block 52 and the LRCK or BCK signal without jitter on the output side. A charge pump circuit 81 comprising an exclusive OR circuit 81a that outputs when N is input and the jitter is LOW, and an exclusive OR circuit 81b that outputs a jitter when the jitter is Hi, The LPF (low-pass filter) 82 to which the output O of the charge pump circuit 81 is input and the analog signal P output from the LPF 82 are converted into digital signals based on the center value and output to the microcomputer of the data processing / utilizing unit 9 ADC or comparator 83.

  Regarding the operation of the jitter + or-determination unit 8, when the jitter frequency of the signal M input to the charge pump circuit 81 changes to +,-(high, low) as shown in FIG. 8, the output P of the LPF 82 also changes. Changes to + and-. Since the jitter frequency changes due to the additional data which is a jitter component, the output P of the LPF 82 can be demodulated into the additional data Da by converting it with the ADC 83.

  Note that the signal P of the LPF 82 may be directly input to the ADC of the microcomputer. Also, the higher the clock frequency is, the faster the jitter can be changed. Therefore, the signal M input to the charge pump circuit 81 can increase the transfer rate in the BCK rather than the LRCK. And the PLL of the receiving device is not locked, so the transfer rate is determined by the actual device.

  In order to determine the change direction of the jitter, the signal obtained by averaging the output signal O of the charge pump circuit 81 with the LPF is the center value and is the level of the accuracy of crystal transmission, so the output signal P of the LPF 82 is based on the center value. You can see if the value of is large or small. As a reference after the LPF, an LPF may be produced in a circuit, or an average value of a sufficient time of a signal obtained by converting the signal P by the ADC 83 may be obtained by software using a microcomputer or the like and compared with it. Since the sent data is modulated into LRCK, it may be demodulated back, and the demodulation method is not limited to the above.

  The transmission method of the present invention is not limited to the above embodiment. Further, as shown in FIG. 9, the present invention can be applied to audio data transmission and general data transmission schemes. Moreover, it is applicable to transmissions other than unbalanced transmission.

1 is a schematic configuration diagram of a data transmission system according to an embodiment of the present invention. The block circuit diagram of a jitter generation part. The signal waveform figure of each part of a jitter generation part. The block circuit diagram of a jitter detection part. The signal waveform figure of each part of a jitter detection part. The diagram which shows the relationship between the gain and frequency of a primary PLL and a secondary PLL. The block circuit diagram of a jitter determination part. The signal waveform figure of each part of a jitter judgment part. (A)-(D) is a block diagram showing a transmission method (example) to which the method of the present invention can be applied. The schematic block diagram of the data transmission system which concerns on a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Data generation part 2 ... Digital audio interface (transmission part) 3 ... Additional data generation part, jitter addition device 4 ... Modulation part 5 ... Digital audio interface (reception part) 5a ... Primary PLL part 6 ... Secondary PLL part 7 ... Audio data use unit 8 ... Demodulation unit, jitter + or-determination unit 9 ... Data processing / use unit, data use device DATA ... Original data, digital audio data Da ... Additional data MKC, BCK, LRCK ... Clock

Claims (6)

In a system that transmits digital data with the concept of a reference clock,
A data transmission method characterized in that additional data is sent in addition to the original data by adding the additional data as modulated jitter to the reference clock. The data transmission method according to claim 2,
A data transmission method characterized in that the magnitude and frequency of the jitter are within an allowable range in the format of the transmission system. The data transmission method according to any one of claims 1 and 2,
A data transmission method, wherein jitter of the reference clock is limited to a range that does not directly affect performance. The data transmission method according to any one of claims 1 to 3,
Even when the jitter component is within the allowable range of the transmission format, the reference clock generated by the receiving device is passed through the narrow-band, low-gain secondary PLL unit, and the jitter component of the reference clock is almost completely removed. Data transmission method. The data transmission method according to any one of claims 1 to 4,
A data transmission method comprising an error correction circuit for additional data. The data transmission method according to any one of claims 1 to 5,
A data transmission method characterized in that the modulation method of the additional data does not have a DC component and / or a low frequency component so that the jitter is concentrated on one of + and-and the frequency of the reference clock is not shifted.

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