JPH10322171A - Automatic frequency control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a circuit constitution, to reduce phase noise, and to improve code error ratio. SOLUTION: A frequency converter 1 supplies an IFQPSK signal obtained by correcting the frequency deviation of a received IF signal to a QPSK signal demodulating circuit 10, and an AFC controller 3 obtains frequency deviation (+, -) information and bit error information from the QPSK signal demodulating circuit 10 and estimates the frequency deviation value of the received IF signal as correction information 8, and a PLL circuit 4 which inputs the correction information 8 and a master reference signal preliminarily set generates a local oscillation signal for correcting the frequency deviation in the received IF signal and supplies it to the frequency converter 1. As a result, it is not necessary to provide a local oscillator, frequency converter, or detector circuit for a pilot reference signal, and digital/analog converters of a PLL circuit supply variable voltage so that the generation of a noise or a code error is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency control (AFC) for correcting a frequency deviation when demodulating a received signal having a frequency deviation caused by drift which is likely to occur in satellite communications and mobile communications. ) Regarding the circuit,
In particular, the present invention relates to an automatic frequency control circuit capable of simplifying a circuit configuration, reducing phase noise and improving a bit error rate.

[0002]

2. Description of the Related Art Conventionally, in an automatic frequency control circuit of this kind, a reception IF (intermediate frequency) signal input from an input terminal is input to a frequency converter 1 and input, as in a satellite communication device shown in FIG. The converted frequency is down-converted to a predetermined frequency. Further, in the frequency converter 1, as described later, the deviation of the output signal after the frequency conversion is corrected by the local oscillation signal subjected to the deviation correction supplied from the AFC (automatic frequency control) circuit 200.

[0003] The output signal of the frequency converter 1 is input to a distributor 9, and one of the divided signals distributed by the distributor 9 is
The corrected IFQPSK signal is supplied to a QPSK (four-phase phase shift keying) signal demodulation circuit 100. The other distribution signal output from the frequency converter 1 and distributed by the distributor 9 is supplied to the AFC circuit 200.

The distributor 9 distributed to the AFC circuit 200
Is input to the frequency converter 201, the frequency of the output signal is low-frequency-converted by the pilot reference signal received from the local oscillator 220 for receiving the pilot reference signal, and an unnecessary wave removing BPF (band-pass filter) 202 is used to reduce the frequency of the output signal. Unnecessary waves are removed and input to the frequency error detector 203.

[0005] The frequency error detector 203 has
The signal input from the PF 202 is compared with a separately set master reference signal, and the difference information is used as error information by the AFC.
Output to the controller 204.

The AFC controller 204 compares the received error information again with the master reference signal and outputs correction information 211 based on a digital signal as correction data. This correction information 211 is stored in a DA (digital / analog) converter 2
05 is converted to an analog signal, and the voltage-controlled oscillator 2
06 is supplied as a variable voltage.

The frequency oscillated by the voltage controlled oscillator 206 changes up to its dynamic range in accordance with the supplied variable voltage, and the oscillated signal is a stable local oscillation signal supplied to the signal demodulation frequency converter 1. P to generate
LL (Phase Locked Loop) circuit 207
Supplied to

The PLL circuit 207 includes a PLLIC (integrated circuit) 208, VCOs (voltage controlled oscillators) 209 and 1
/ N frequency divider 210 and the voltage controlled oscillator 20
6 is supplied from the PLLIC 208 to V
A local oscillation signal is supplied to the frequency converter 1 via the CO 209 and the local oscillation signal is fed back to the PLLIC 208 via the 1 / N frequency divider 210 to generate a stable local oscillation signal.

With the above structure, the received IF signal input to the frequency converter 1 is converted by the AFC circuit 200 together with the low-frequency conversion in the frequency converter 1.
The frequency error is corrected based on the feedback of the stable local oscillation signal generated from the F signal, and the IFQPS
The signal is output as a K signal and supplied to the QPSK signal demodulation circuit 100.

An IFQPS in which this frequency error is corrected
In the QPSK signal demodulation circuit 100, the unnecessary signal such as a harmonic wave is removed by the unnecessary wave removing BPF 11 in the QPSK signal demodulation circuit 100, and then distributed to the in-phase detector 15 and the quadrature detector 16, respectively. The data is output as I data and Q data demodulated through the respective sections.

[0011]

The conventional automatic frequency control circuit described above has the following problems.

First, the first problem is that the circuit configuration is large and complicated.

The reason is that a pilot reference signal is required to estimate the frequency deviation of the received signal, and the pilot reference signal is detected to generate error information from the master reference signal. And a frequency converter, a BPF, and a frequency error detector. Also, in order to control a VCO that feeds back estimated frequency error information to a signal demodulation circuit, a DA that converts correction information of a digital signal output by an AFC controller into an analog signal
This is because a converter is required.

The second problem is that the phase noise of the input signal to the signal demodulation circuit increases and the bit error rate deteriorates.

The reason is that the IFQP to the signal demodulation circuit
The local oscillation signal for correction supplied to the frequency converter that outputs the SK signal is generated by the control circuit including the DA converter, so that it is easily interfered by noise, and the phase noise of the local oscillation frequency is greatly deteriorated. Because.

An object of the present invention is to provide an automatic frequency control circuit capable of solving the above problems, simplifying the circuit configuration, reducing phase noise and improving the bit error rate.

[0017]

SUMMARY OF THE INVENTION An automatic frequency control circuit according to the present invention provides a frequency deviation information from a signal demodulation circuit for demodulating a received signal when correcting the frequency deviation when demodulating the received signal having the frequency deviation. And an AFC controller that obtains bit error information, estimates a frequency deviation value of the received signal, and outputs correction information, and inputs both the correction information and a preset master reference signal to convert the received signal into the signal demodulated signal. A phase locked loop (PL) for generating a local oscillation signal for frequency conversion into an input signal to a circuit
L) circuit.

According to this configuration, the pilot reference signal is not required in the automatic frequency control circuit. Therefore, a local oscillator for reception, a frequency converter and a detection circuit for this signal, and a variable voltage supply to the PLL circuit are provided. No digital-to-analog converter is required.

[0019]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the present invention. The automatic frequency control circuit shown in FIG. 1 is an AFC circuit 2 and receives a signal from an input terminal.
The frequency converter 1 outputs the F signal as an IFQPSK signal together with the low-frequency conversion of the frequency and supplies it to the QPSK signal demodulation circuit 10 by using a frequency deviation code received from the QPSK signal demodulation circuit 10 and correction information obtained from bit error information. The generated stable local oscillation signal is fed back.

Therefore, the frequency converter 1 receives the feedback of the stable local oscillation signal received from the AFC circuit 2 and corrects the frequency error of the input reception IF signal.
It is supplied to the QPSK signal demodulation circuit 10 as an IFQPSK signal.

First, the QPSK signal demodulation circuit 10 for which the AFC circuit 2 automatically controls the frequency will be described.

The QPSK signal demodulation circuit 10 first limits the band of the input IFQPSK signal by an unnecessary wave removing BPF 11 to remove unnecessary waves such as harmonics and pass only a desired wave in consideration of a frequency deviation. Next, the distributor 12
To the in-phase detector 15 and the quadrature detector 16 respectively.

Here, the desired wave taking the frequency deviation into consideration is defined as a condition in which the desired signal bandwidth Ws and the bandwidth Wbpf of the unnecessary wave removing BPF 11 in the maximum frequency deviation Wd satisfy the following equation (1).

_{Wbpf ≧ Ws + 2 · Wd (1) The} local oscillator 13 directly supplies a fixed frequency signal to the in-phase detector 15 via the π / 2 converter 14 and to the quadrature detector 16 on the other hand. The outputs of the in-phase detector 15 and the quadrature detector 16 have a phase shift of 90 degrees with each other.

The outputs of the in-phase detector 15 and the quadrature detector 16 are unnecessary LPFs (low-pass filters) 1
In step 7, unnecessary waves such as harmonics are removed and the AD converter 18
To enter. The AD converter 18 is a digital QPS which is a functional block at the last stage of the QPSK signal demodulation circuit 10.
The input analog signal is converted into a digital value by a clock having a frequency four times the symbol rate supplied from the clock recovery circuit of the K signal demodulator 20.

The signal output from the A / D converter 18 is input to a roll-off LPF 19 having the same frequency transfer characteristic and shaped into a spectrum. The roll-off LPF 19 is
This filter forms a transfer characteristic required for preventing intersymbol interference in digital data transmission, and is generally combined with a filter characteristic on the transmitting and receiving sides, and is designed to obtain a so-called roll-off low-pass filter characteristic.
Therefore, the output of the roll-off LPF 19 is spectrally shaped so that the eye opening ratio becomes sufficiently large in the detection output. Filtering at a quadruple symbol rate is to avoid the effect of aliasing due to frequency deviation.

The digital QPSK signal demodulator 20 has 9
A signal which is phase-shifted by 0 degrees and input from each of the two roll-off LPFs 19 is digitally processed and output as I data and Q data of demodulated data.

The digital QPSK signal demodulator 20
Are frequency deviation (+,-) information detected by a frequency error detection function for frequency control, and bits detected for automatic error correction of a received code. Error information (FEC: Forword Erro
r Correction) to the AFC circuit 2 for supply.

On the other hand, it is assumed that the AFC circuit 2 has an AFC controller 3 and a PLL circuit 4, and the PLL circuit 4 is constituted by a decimal frequency dividing PLLIC 5, a VCO 6, and a 1 / N frequency divider 7.

The AFC controller 3 has a digital QP
The frequency deviation information and the bit error information are input from the SK signal demodulator 20, and the frequency deviation correction information 8 is input to the PLL.
It is estimated as synthesizer data to be supplied to the decimal division PLLIC 5 of the circuit 4.

The decimal-divided PLLIC 5 converts a preset master reference signal, the correction information 8 supplied from the AFC controller 3 and the output of the PLL circuit 4 supplied to the frequency converter 1 by 1 / N. In response to the signal fed back via the frequency divider 7, a variable voltage for controlling the VCO 6 is generated and output.

The local oscillation signal output from the VCO 6 receiving the variable signal is fed back to the decimal point frequency-divided PLLIC 5 via the 1 / N frequency divider 7 as the output of the PLL circuit 4, so that a stable local oscillation signal is generated. Is done.

This local oscillation signal is supplied to the frequency converter 1, which corrects the frequency error of the received IF signal to be inputted, and outputs a QPSK signal demodulation circuit 10.
An IFQPSK signal to be supplied to is generated and output.

In the above description, the bit error information input to the AFC controller is illustrated and described as being obtained from the QPSK signal demodulator.
It may be obtained by detecting using a UW (Unique Word) detector or the like separately provided in the signal demodulation circuit.

[0036]

As described above, according to the present invention, frequency deviation information and bit error information are obtained from a signal demodulation circuit for demodulating a received signal, the frequency deviation value of the received signal is estimated, and correction information is output. An AFC controller and a phase locked loop (PLL) that receives both the correction information and a preset master reference signal and generates a local oscillation signal for frequency-converting the received signal into an input signal to the signal demodulation circuit ( (Ph. PLL) circuit.

With this configuration, since a pilot reference signal is not required, a receiving local oscillator for this signal,
Frequency converter, detection circuit for this signal, and PLL
Since a digital / analog converter for the variable voltage supplied to the circuit is not required, the circuit configuration can be simplified, and the control circuit including the digital / analog converter can be omitted, so that the phase noise can be reduced. Also, the effect that the code error rate can be improved can be obtained.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

FIG. 2 is a functional block diagram showing an example of the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Frequency converter 2 AFC circuit 3 AFC controller 4 PLL circuit 5 Decimal-point frequency division PLLIC (Integrated circuit) 6 VCO (Voltage control oscillator) 7 1 / N frequency divider 10 QPSK signal demodulation circuit 20 Digital QPSK signal demodulator

Claims (1)

[Claims] An automatic frequency control (AF) for correcting a frequency deviation when demodulating a received signal having a frequency deviation.
C) A circuit that obtains frequency deviation information and bit error information from a signal demodulation circuit that demodulates a received signal, estimates a frequency deviation value of the received signal, and outputs correction information.
A phase-locked loop (PLL) that receives a controller and both the correction information and a preset master reference signal and generates a local oscillation signal for frequency-converting the received signal into an input signal to the signal demodulation circuit; A) an automatic frequency control circuit comprising: