JP2009225128A - Carrier wave reproduction circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a carrier wave reproduction circuit which is used as a digital signal processing circuit which generates stable carrier frequency synchronization and demodulated information data under propagation path fading. <P>SOLUTION: The carrier wave reproduction circuit includes: a frequency converter 311 which uses a received signal by multi-level modulation as one input, uses a local oscillation signal as the other input, in which frequency conversion is performed by both inputs to generate an intermediate frequency; a quadrature detection part 313 which performs quadrature detection of the multi-level modulation to a digital signal to generate detection signals of I phase and Q phase; a roll-off filter 314; a propagation path estimation part 315 which calculates a propagation path coefficient; a phase comparator 316 which calculates phase difference of a carrier frequency between the received signal and the local oscillation signal and a modulation phase part of the received signal by the multi-level modulation, by an output signal of the propagation path estimation part; a waveform equalizer 317 which outputs the modulation phase as the demodulated information data; a loop filter 318; and a local oscillator 321 which uses the local oscillation signal whose carrier frequency is synchronized with the received signal as output. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to wireless transmission of digitized information, and more particularly to a carrier recovery circuit suitable for use in a phase-locked loop that synchronizes a receiver with a transmitter.

  These multiple signals, such as wideband audio signals such as broadcast audio program signals, communication signals between broadcasting stations and broadcasting stations, and monitoring / control signals of broadcasting station equipment, are processed digitally at a time, and are sent to remote locations. Digital radio network equipment to be transmitted needs to improve transmission efficiency by adopting multi-level modulation method, etc. due to the efficiency of using radio frequency, the increase of transmission media, and the increase of transmission data capacity and speed accompanying digitalization. It has come out.

  As described above, STL (Studio to Transmitter Link; a radio channel for transmitting a broadcast program or the like from a studio to a transmitting station) and TTL (Transmitter to Transmitter Link; a radio channel for transmitting a broadcast program or the like between transmitting stations) are The digital system is being promoted.

  In addition, as a means for implementing a radio circuit, a digital signal processor (DSP) technique is being developed in which a circuit is replaced with software to realize a flexible functional circuit and a functional circuit with extremely little temporal variation. .

  In particular, in a modulation circuit and a demodulation circuit such as a multi-level modulation scheme (eg, QPSK; Quadrature Phase Shift Keying, 64QAM; 64-level Quadrature Amplitude Modulation), a circuit is realized using a digital signal processing technique.

  When demodulating a multilevel modulation signal, a synchronization circuit (carrier recovery circuit; PLL; Phase Locked Loop) that synchronizes the phase of the reception carrier (reception local oscillation frequency) with the phase of the transmission carrier (reception signal) is indispensable.

  On the other hand, in recent years, as the signal processing capability of DSPs and FPGAs (Field Programmable Gate Arrays), which are devices that actually perform digital signal processing, has improved in recent years, the circuits processed by these digital signal processing devices have been improved. The proportion is increasing. As a result, the processing range in the digital signal processing circuit becomes large, and the adverse effects of software multiplex processing may occur, such as variations in response time.

  In response to sudden changes in the radio channel propagation path such as fading, the digital signal processing circuit responds to the PLL circuit. There may be variations in time, real-time performance may not be ensured, and stable synchronization may not be performed.

  FIG. 4 is a block diagram illustrating a configuration example of a carrier recovery circuit included in a conventional receiving unit.

  Multi-level modulation (QPSK, 64QAM) demodulator circuit, quadrature detection circuit (multipliers 212, 222, 90 ° phase shifter 220, LPF 213, 223), ROF (Roll Off Filter); (Waveform shaping filter that fits in band) 215, 225, propagation path estimation unit 216, phase comparator 217, waveform equalizer 218, and data is demodulated.

  In these configurations, demodulation processing after A / D (Analog Digital Converter) 214, 224 is digital signal processing.

  Furthermore, the phase comparator 217, the loop filter 230, the LPF 232, and a VCXO (Voltage Controlled X′al “crystal” Oscillator) 233 are configured to perform a carrier wave recovery PLL circuit.

  In these configurations, the digital signal processing is used for the synchronization processing up to D / A (Digital Analog Converter) 231.

  The VCXO control voltage v, which is the output of the LPF 232, enters a loop that controls the frequency and phase of the local oscillator (VCXO 233) that oscillates the regenerative carrier b (received carrier; local oscillation signal or local oscillation signal) that is directly supplied to the quadrature detector. This loop is used to control the phase difference between the received signal s and the recovered carrier b to be zero.

  The VCXO may be a VCO (Voltage Controlled Oscillator).

  Although not shown, in recent years, the speed of digital signal processing has further increased, and a high-speed A / D is provided in the input stage of the received signal, and quadrature detectors including multipliers 212 and 222 and VCXO 233 are digitally digitalized. It has become possible to replace it with processing of a digital signal processing device such as a down converter (DDC; Digital Down Converter) or a DSP.

  However, as the transmission data capacity and speed required by the system increases, the amount of data to be received and the processing speed also increase.

  It is necessary to consider the trade-off between the dedicated hardware range (analog circuit) of the receiving circuit and the software processing range of the digital signal processing circuit. That is, considering the content and amount of processing imposed on the digital signal processing circuit, there is a trade-off relationship between device processing performance and cost.

  For this reason, it is important to reduce the processing load on the digital signal processing circuit device and to configure the carrier wave reproduction circuit so as to ensure real-time performance.

  In the case of a radio link, intersymbol interference occurs due to frequency selective fading in the propagation path, so that noise is added to the phase component of the received signal and the phase variation of the carrier wave becomes severe.

  When the above phenomenon occurs in a digital signal processed circuit in the demodulator of the conventional receiver, in the PLL driving operation based on the carrier phase difference information, the synchronization state of the received signal s and the recovered carrier b is maintained. There is a problem that transmission data is erroneously received data.

  Furthermore, in a system that performs high-speed data transmission in a high-speed, wide-range digital signal processing circuit, the time until the detection result of the phase difference of the carrier wave (loop delay amount) is the response time of the software processing. If the delay amount increases due to the difference, the PLL operation within one symbol time becomes difficult.

As a prior art that considers the trade-off between the digital signal processing circuit and the individual hardware circuit, the phase difference between the recovered carrier and the received signal is corrected by a waveform equalizer to reproduce the data, and the carrier frequency of the recovered carrier and the received signal This is a carrier recovery system that corrects the deviation by the phase synchronization circuit and ensures the synchronization of the recovered carrier. In the data demodulation circuit, A / D or later, and in the phase synchronization circuit, D / A (Digital A carrier wave reproduction method that places a circuit function up to (Analog Converter) on a digital signal processing circuit is disclosed. (For example, see Patent Document 1)
JP-A-10-107863 (FIG. 1)

  There is a case where the received signal is disturbed by fading or the like on the propagation path, the intersymbol interference increases, the fluctuation of the modulation phase due to noise becomes severe, and the fluctuation of the phase difference of the carrier frequency also becomes severe. Under such circumstances, in the PLL drive circuit system using the phase difference information provided with the conventional digital signal processing circuit, it becomes difficult to synchronize the carrier frequency of the received signal and the reproduced carrier wave, and also due to the loop delay due to the digital signal processing. The PLL operation within one symbol cannot be completed, that is, the phase difference fluctuation speed cannot be followed, and further, the loop processing of the carrier recovery circuit using a digital signal processing device such as a digital down converter or DSP is incorporated. As a result, there is a problem that the processing capacity of the device increases and the amount of processing program increases, and accordingly, there is a problem that the real-time response time varies.

  An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a carrier recovery circuit composed of a digital signal processing circuit capable of generating stable carrier frequency synchronization and demodulated information data in channel fading. It is to provide.

  In order to achieve this object, the carrier recovery circuit of the present invention performs a frequency conversion using a reception signal subjected to multilevel modulation and a local oscillation signal as input, and generates an intermediate frequency signal, and An A / D converter that converts the intermediate frequency signal into a digital signal, a quadrature detection unit that performs quadrature detection on the digital signal and generates I-phase and Q-phase detection signals, and a spectrum waveform of the detection signal A roll-off filter for shaping, a propagation channel fading unit for estimating a propagation channel fading state from the shaped detection signal and calculating a propagation channel coefficient, and between the received signal and the local oscillation signal from the propagation channel coefficient And a phase comparator for calculating a phase difference of the carrier frequency of the received signal and a modulation phase of the received signal subjected to the multi-level modulation, and a modulation phase error due to the channel fading from the modulation phase Calculating a phase, correcting the phase of the modulation phase based on the modulation phase error, and outputting as demodulated information data, a loop filter for delay correcting the phase difference of the carrier frequency, A D / A converter that converts the output of the loop filter into an analog signal; a low-pass filter that extracts a direct current component from the analog signal; and a phase control of the local oscillation signal based on the phase difference of the carrier frequency that is the direct current component And a local oscillator that outputs the local oscillation signal whose carrier frequency is synchronized with the received signal.

  According to the present invention, the operation of the PLL circuit is performed at the level of the carrier frequency under the situation where the intersymbol interference is increased due to the disturbance of the propagation path, the variation of the modulation phase is severe, and the variation of the phase difference of the carrier frequency is severe. It can follow phase difference fluctuations, can stably synchronize the carrier frequency of the received signal and the recovered carrier wave, and incorporates the loop processing of the carrier wave recovery circuit that imposes on digital signal processing, increasing the processing amount of the digital signal processing device However, the PLL operation is stably completed within the desired real-time response time.

  Hereinafter, a carrier recovery circuit according to an embodiment of the present invention will be shown and described.

  FIG. 3 shows a block diagram of a configuration example of a digital radio network system implementing the present invention, and will be described.

  Reference numeral 111 denotes an encoding unit, 112 denotes a multiplex synthesis unit, 113 denotes a modulation unit, and 114 denotes a transmission amplification unit, which are connected in order to form the transmission unit 10.

  Transmission information signals (t1, t2,... Tn) such as audio signals, warning signals, and control signals are input to the encoding unit 111 for each transmission information signal and converted into digital data.

  The encoding unit 111 encodes each transmission information signal (t1, t2,... Tn). When the transmission information signal t1 is, for example, an analog audio signal, the encoding unit 111 The audio signal is A / D converted, subjected to an encoding process such as compression if necessary, and sent to the multiplex synthesis unit 112.

  Further, the transmission information signal t1 may be a digital signal such as a character code or image data. This is also the case with the transmission information signal t2, and thus several transmission information signals (in different formats) ( t1, t2,... tn) can be input in parallel.

  The encoded parallel data is subjected to multiplex code processing in the multiplex synthesis unit 112 to become one data stream.

  The multiplexed data stream is added with an error correction code by the modulation unit 113 and additional information (hereinafter referred to as a unique word) necessary for code synchronization at the time of demodulation on the receiving side, and interleaving, scrambling, etc. May be added, and a radio frame subjected to predetermined code processing is generated. These encoding processes may be performed by the multiplexing / combining unit 112.

  The added unique word is used for synchronization processing during demodulation and training of the equalizer.

  The radio frame generated by the modulation unit 113 is further subjected to digital modulation processing of multilevel quadrature modulation such as 64QAM, and a transmission modulated wave signal is generated and output.

  The transmission amplification unit 114 performs frequency conversion and power amplification of the transmission modulated wave signal to generate a high frequency signal (RF signal; Radio Frequency; radio frequency signal), and a transmission antenna output signal is transmitted from the antenna to the transmission path.

  Next, a description will be given on the receiving side. 121 is a reception amplifying unit, 122 is a demodulation unit, 123 is a demultiplexing unit, and 124 is a decoding unit, which are connected in order to form the receiving unit 20.

  An RF signal, which is a transmission signal subjected to multi-level orthogonal modulation, propagated through the wireless transmission path is received at the input of the receiving antenna, the reception amplifier 121 amplifies the received signal, and a band pass filter (BPF; Band Pass Filter) at the RF stage. Unnecessary band is removed in a band-pass filter), down-converted to an intermediate frequency (IF), further subjected to BPF processing in the IF stage, and unnecessary waves after conversion are removed, and AGC is removed. Level adjustment for adjusting the gain to a constant level is performed by (Automatic Gain Control; automatic gain control). After that, the demodulation unit 122 performs digital demodulation processing.

  The demodulator 122 detects a unique word that is a known code sequence added to the data frame of the received data and corrects the sampling position of the received data, thereby establishing frame synchronization and symbol synchronization and performing synchronous detection.

  For synchronous detection of QPSK and QAM, it is necessary to regenerate the absolute phase of the transmission carrier on the receiving side. (Carrier synchronization, carrier synchronization).

  The carrier recovery process for establishing the synchronization of the carrier wave is a Costas loop process for generating the phase difference information between the received signal and the recovered carrier wave through a quadrature detection circuit to be described later, and using this to move the PLL loop to synchronize the carrier wave. Etc.

  The digital demodulation processing such as 64QAM performed in the demodulator 122 establishes symbol synchronization necessary for demodulation of multilevel modulation, generates a data sequence sampled by the reproduced symbol clock, and further generates a multiplexed data stream. It is sent to the demultiplexing unit 123.

  The demultiplexing unit 123 demultiplexes each channel data of the information signal and sends the data of each individual channel to the decoding unit 124.

  The decoding unit 124 performs decoding processing by D / A conversion or the like for each channel, generates reception information signals (r1, r2,... Rn), and outputs them as respective outputs.

  FIG. 2 is a block diagram showing a basic configuration example of the carrier recovery circuit of the demodulating unit 122 according to the embodiment of the present invention, which will be described below.

  211 receives the received signal s (first intermediate frequency) as one input and the local signal a (reproduced carrier wave) as the other input, and performs frequency conversion using the two input signals to generate a second intermediate frequency. Output frequency converter. In order to generate the second intermediate frequency, although not shown, a BPF for extracting the second intermediate frequency may be inserted on the output side of the frequency converter 211.

  212 is a quadrature detection means for generating an I-phase detection component using the second intermediate frequency as one input and the output frequency of the OSC 219 shifted by 90 ° (the same frequency as the second intermediate frequency) as the other input. It is a multiplier.

  A multiplier 222 is a quadrature detection unit that generates a Q-phase detection component using the second intermediate frequency as one input and the output frequency of the OSC 219 as the other input.

  Reference numeral 213 denotes an LPF (Low Pass Filter) that receives an I-phase detection component as input and generates only an I-phase detection signal through the low-frequency component.

  Reference numeral 223 denotes an LPF that receives a Q-phase detection component and passes only the low-frequency component thereof to generate a Q-phase detection signal.

  Reference numeral 214 denotes an A / D converter that receives an I-phase detection signal as an input, digitally converts it, and generates an output that can be digitally processed by a DSP or the like.

  Reference numeral 224 denotes an A / D converter that receives a Q-phase detection signal as an input, digitally converts it, and generates an output that can be digitally processed by a DSP or the like.

  Reference numeral 215 denotes an ROF that receives a digitized I-phase detection signal as input, shapes a spectrum waveform by digital filter processing, and generates a desired I-phase detection output.

  Reference numeral 225 denotes an ROF that receives a digitized Q-phase detection signal as input, shapes a spectrum waveform by digital filter processing, and generates a desired Q-phase detection output.

  Reference numeral 216 denotes a propagation path estimator that receives each of the I-phase and Q-phase ROF-processed detection signals, calculates a propagation path coefficient from the input signal, and outputs it.

  217 detects the symbol position (modulation phase) of the modulation signal and outputs it as one output (information data component), and detects the phase difference of the carrier wave between the reception signal s and the local oscillation signal a It is a phase comparator as an output.

  A waveform equalizer 218 receives one output of the phase comparator as input, corrects a modulation phase error, and outputs correctly demodulated information data.

  Reference numeral 219 denotes an OSC (Oscillator) that oscillates at the same frequency as the second intermediate frequency to perform quadrature detection and outputs an oscillation output.

  Reference numeral 233 denotes a VCXO (Voltage Controlled X'al “crystal” Oscillator; voltage-controlled crystal oscillator) that forms a voltage-controlled local oscillator that oscillates the local oscillation signal a and outputs it to the frequency converter 211.

  Reference numeral 220 denotes a 90 ° phase shifter that outputs an output signal delayed (or advanced) by 90 ° with respect to the output signal of the OSC 219.

  230 receives the detection result (phase control signal) of the phase difference of the carrier frequency generated by the phase comparator 217 as input, removes harmonic components contained therein, and positions the response time (delay time) of the PLL loop. It is a loop filter.

  A D / A converter 231 returns the output of the loop filter 230 to an analog value.

  Reference numeral 232 denotes an LPF (Low Pass Filter) that removes harmonic components contained in the output of the D / A converter.

  A PLL loop for performing carrier wave recovery is formed by a circuit from the phase comparator 217 and the loop filter 230 to the VCXO 233.

  The multipliers 212 and 222, the 90 ° phase shifter 220, the LPFs 213 and 223, and the OSC 219 form an orthogonal detection unit 313.

  In FIG. 2, the received signal s is an IF signal (first intermediate frequency), but although not shown, an RF signal which is a signal before being converted to the first intermediate frequency is directly input (direct conversion method). ). Even in such a case, processing such as BPF and AGC is required in the preceding circuit (reception amplifier 121).

  2 according to the present invention, the output from the quadrature detection unit 313 is input to the A / D converters 214 and 224, and is subjected to digital signal processing by the subsequent circuits. This digital signal processing is performed until the output from the loop filter 230 is input to the D / A converter 231, and within this circuit range, the digital signal processing with sufficient time as a digital signal processing unit ( Software, program processing).

  Further, if the circuit system of FIG. 2 according to the present invention is used, a digital signal processing system can be used for a circuit including the quadrature detection unit 313 by using a plurality of digital signal processing LSIs capable of high-speed processing in recent years. It is replaced as a circuit with sufficient time.

  Such a digital signal processing system can be configured by a digital signal converter (LSI) such as a digital down converter (DDC) or FPGA, DSP.

  Therefore, a configuration example in the case where the quadrature detection unit 313 and the subsequent steps are performed by digital signal processing is shown and described below. FIG. 1 is a block diagram showing a configuration example of a carrier recovery circuit of a demodulator 122 according to another embodiment of the present invention.

  In FIG. 1, reference numeral 311 designates a received signal s (first intermediate frequency) by multi-level modulation as one input, a local signal a (regenerated carrier wave) as the other input, and performs frequency conversion by two input signals. This is a frequency converter that generates and outputs an intermediate frequency (second intermediate frequency), and has the same function as the frequency converter 211 of FIG.

  In order to generate the second intermediate frequency, although not shown, a BPF for extracting the second intermediate frequency may be inserted on the output side of the frequency converter 311.

  Reference numeral 312 denotes an A / D converter that converts the second intermediate frequency output from the frequency converter 311 into a digital signal.

  313 receives a multilevel modulation signal converted into a digital signal, which is an output of the A / D converter 312, and performs quadrature detection of the multilevel modulation by a digital signal processing device such as a digital down converter (DDC). It is a quadrature detection unit that generates phase and Q phase detection signals.

  Reference numeral 314 denotes an ROF that receives digitized I-phase and Q-phase detection signals as input, shapes the spectrum waveform of the detection signal by digital filter processing so as to achieve a desired roll-off, and outputs the resulting waveform. This is a digital filter having the same function as the ROFs 215 and 225 shown in FIG.

  Reference numeral 315 denotes a propagation path estimation unit that estimates the state of instantaneously changing propagation path fading from the output signal of the ROF 314 and calculates a propagation path coefficient, and has the same function as the propagation path estimation unit 216.

  316 is a phase comparator that calculates the phase difference of the carrier frequency between the reception signal s and the local oscillation signal a and the modulation phase of the reception signal subjected to multilevel modulation from the output signal of the propagation path estimation unit 315. This has the same function as the phase comparator 217.

  Reference numeral 317 denotes a waveform equalizer that calculates a modulation phase error due to propagation channel fading from the modulation phase, corrects the phase of the modulation phase based on the modulation phase error, and outputs it as demodulated information data of multilevel modulation. Yes, it has the same function as the waveform equalizer 218.

  Reference numeral 318 denotes a loop filter that delay-corrects the phase difference of the carrier frequency, and has the same function as the loop filter 230.

  Reference numeral 319 denotes a D / A converter that converts the output of the loop filter 318 into an analog signal, and has the same function as the D / A converter 231.

  Reference numeral 320 denotes a low-pass filter that extracts a DC component from an analog signal, and has the same function as the LPF 232.

  Reference numeral 321 denotes a VCXO (local oscillator) that performs phase control of the local oscillation signal a based on the phase difference of the carrier frequency that is a direct current component and outputs the local oscillation signal a synchronized with the reception signal s. This is the same function as VCXO233.

  In FIG. 1, an input received signal s is mixed with a frequency from a voltage-controlled VCXO 321 by a frequency converter 311, and an output thereof becomes a second intermediate frequency (2nd IF) signal.

  Therefore, in the present invention, the ranges of the LPF 320, the VCXO 321 and the frequency converter 311 are configured as individual hardware circuits.

  The second intermediate frequency signal is directly input to the A / D converter 312 and converted into a digital signal, and subsequent demodulation processing including quadrature detection of the multilevel modulation signal is performed by digital signal processing by a DDC or DSP device. .

  In other words, in the present invention, the circuit range from A / D 312 to waveform equalizer 317 and D / A 319 is divided into a software processing circuit constituting a digital signal processing unit and an individual hardware circuit as a dedicated circuit. is there.

  Although not shown, the LPF 320 may be included in the range of the digital signal processing unit.

  The carrier recovery circuit configured as a digital signal processing circuit by the above circuit can provide stable carrier frequency synchronization and demodulated information data in propagation channel fading.

  Next, the flow of signal processing in the main part of the circuit of the present invention will be described in detail.

  Although the range of digital signal processing is different between FIG. 1 and FIG. 2, the processing function of the multi-level modulation signal is the same, so the signal processing will be described first with reference to FIG. To proceed.

  In FIG. 2, the I-phase signal and Q-phase signal converted into digital signals by the A / D converters 214 and 224 are subjected to filtering processing such as a roll-off filter (also referred to as a root roll-off filter) for waveform shaping. After being filtered by the digital filters ROF 215 and 225 to be performed, it is sent to the propagation path estimation unit 216.

  The propagation path estimation unit 216 calculates a propagation path coefficient by comparing the unique word added to the received signal with the code of a predetermined unique word stored in advance in the memory inside the receiving apparatus.

  The phase comparator 217 compares the unique word of the received signal with the code of the unique word stored in advance in the memory inside the receiver, and compares the current average phase, the previous average phase, and the same frame period from the code comparison. The average phase difference and the like are obtained, and the phase change amounts for the phase difference and modulation phase error of the carrier frequency are generated from these values.

  Based on the generated phase change amount, the symbol position of the multi-level modulation signal is detected, the information data is demodulated, and the phase difference information (carrier frequency phase difference) between the received signal s and the regenerated carrier wave (local signal a) And the PLL loop circuit is operated to generate a synchronized reproduction carrier wave.

  As described above, the phase change amount generated by the phase comparator 217 generates phase information for reproducing information data as a first phase change amount, and in addition to one frame (one radio frame with additional information added). ) Indicates a phase change amount (phase difference information p) that is an error changed in time, and this becomes a second phase change amount indicating a frequency offset amount (carrier frequency shift) of the regenerated carrier wave, and its output is sent to the loop filter 230. Sent.

  This phase difference information p is sent to the D / A converter 231 through the loop filter 230 and converted into an analog voltage value. The converted analog voltage value removes unnecessary waves other than the DC component generated by the D / A converter 231 by the LPF 232 and is sent as a frequency control voltage (VCXO control voltage v) of the VCXO 233 which is a voltage controlled local oscillator. .

  Due to the PLL loop configuration described above, the received signal (second intermediate frequency) output from the mixer 211 gradually decreases in frequency offset, and finally the recovered carrier is synchronized with the same frequency as the transmitted carrier, and is included in the received signal. This is only the modulation phase error that affects the demodulation of the information data.

  The modulation phase error included in the received signal is mainly a modulation phase error due to fading or the like in the propagation path, and this modulation phase error is obtained as a propagation path coefficient by the propagation path estimation unit 216. Using the path coefficient, the waveform equalizer 218 removes the modulation phase error, and correctly demodulated information data is reproduced.

  According to the circuit configuration of the embodiment of FIG. 2, a carrier recovery loop circuit including a VCXO 233 separately from the OSC 219 supplies a local oscillation signal to the intermediate frequency generation unit for the demodulation circuit having the quadrature detection unit 313 including the OSC 219. Therefore, each local oscillator is dedicated, and this increases processing in the PLL loop and increases processing delay.

  However, the PLL operation only needs to be in time for the time required to correct the frequency difference between the carrier frequencies (delay time), which is not necessarily a short time of one frame or several frames. It is also possible to adopt a configuration in which the detection unit and the subsequent parts are performed by digital processing.

  In addition, since the demodulated signal is lowered to a low frequency, a margin is generated in the signal processing time of the demodulating circuit.

  As described above, even if the number of digital signal processing circuit portions is increased as shown in FIG. 1, the processing load of the digital signal processing device can be reduced by using a loop of an intermediate frequency local oscillator as in the invention.

  According to such a circuit system of the present invention, it is only necessary to divide the demodulation processing time of the information data and the synchronization processing time of the PLL circuit, and to finish the signal processing time within each required time, so that the processing time is afforded. Thus, for example, even if the amount of processing of a device increases in response to an increase in transmission capacity, an increase in transmission speed, an increase in frequency, a multi-level modulation / demodulation process, etc., the phase is increased due to a processing delay due to an increase in processing time. The problem that the correction cannot follow is solved.

  Therefore, since the PLL operation loop does not need to share the local oscillator (OSC 219 shown in FIG. 2) included in the quadrature detection unit, the processing of the device including the quadrature detection unit can be performed by dedicating the loop to the local oscillator of the intermediate frequency. The burden can be reduced.

  As described above, according to the circuit system of the present invention, the frequency converter 311 (211) frequency-converts (down-converts) the received signal s, which is the first intermediate frequency signal, into the second intermediate frequency signal, so that the frequency band is relatively low. Since the signal is generated, there is a margin in the demodulation time of the information data and the processing time of the PLL loop in the digital signal processing.

  In particular, in the VCXO control voltage v for correcting the carrier frequency shift (phase difference information p) due to the phase difference fluctuation between the reproduced carrier wave a (local signal) and the received signal s, there is no delay variation and the digital signal processing response A time-stable PLL loop configuration is obtained.

  Therefore, if the second intermediate frequency signal whose frequency is down-converted is used, data demodulation and digital signal processing for PLL operation can be performed with a margin.

  Note that the waveform equalizer 317 (218) corrects this as a phase difference fluctuation between the reproduced carrier a and the received signal s with respect to disturbance caused on the propagation path such as fading and correct information data. Is demodulated.

  As described above, according to the present invention, the carrier frequency shift (phase difference information p) is generated from the phase comparator 316 (217) in the process of demodulating the information data. As long as it is a circuit that generates the phase difference information p, it is not particularly necessary to use a loop configuration in a quadrature detector, and it may be a PLL loop of a local oscillator in a dedicated circuit that generates an intermediate frequency.

  The present invention is applied to a wireless communication system used for fixed communication, and can be used as a communication line such as an STL as an example.

It is a block diagram which shows the structural example of the carrier wave recovery circuit of the receiver which is an Example of this invention. It is a block diagram which shows the structural example of the carrier wave recovery circuit of the receiver which is the other Example of this invention. It is a block diagram which shows the structural example of the digital radio | wireless circuit system which implements this invention. It is a block diagram which shows the structural example of the carrier wave reproduction circuit of the conventional receiving part.

Explanation of symbols

10 transmitting unit 20 receiving unit 111 encoding unit
112 Multiple synthesizer
113 Modulator
114 Transmission amplifier
121 Receiving amplifier
122 Demodulator
123 Demultiplexer
124 Compounding Department
211, 311 Frequency converter 212, 222 Multiplier 213, 223, 232, 320 LPF (low pass filter)
214, 224, 312 A / D (analog / digital converter)
215, 225, 314 ROF (roll-off filter)
216, 315 Propagation path estimation unit 217, 316 Phase comparator 218, 317 Waveform equalizer 219 OSC (Oscillator)
220 90 ° phase shifter 230, 318 Loop filter 231, 319 D / A (digital / analog converter)
233 VCO (Voltage Controlled Oscillator)
321 VCXO (voltage controlled crystal oscillator)
313 Quadrature detector (DDC)

Claims (1)

A frequency converter that performs frequency conversion using the received signal subjected to multi-level modulation and a local oscillation signal as input, and generates an intermediate frequency signal;
An A / D converter for converting the intermediate frequency signal into a digital signal;
A quadrature detection unit that performs quadrature detection on the digital signal and generates I-phase and Q-phase detection signals;
A roll-off filter for shaping a spectrum waveform of the detection signal;
A propagation path estimator that estimates a propagation path fading state from the shaped detection signal and calculates a propagation path coefficient;
From the propagation path coefficient, a phase comparator that calculates a phase difference of the carrier frequency between the received signal and the local oscillation signal, and a modulation phase of the received signal subjected to the multilevel modulation;
A waveform equalizer that calculates a modulation phase error due to the channel fading from the modulation phase, corrects the phase of the modulation phase based on the modulation phase error, and outputs the demodulated information data;
A loop filter that delay-corrects the phase difference of the carrier frequency, a D / A converter that converts the output of the loop filter into an analog signal, a low-pass filter that extracts a DC component from the analog signal, and the DC component. In addition, phase control of the local oscillation signal is performed based on the phase difference of the carrier frequency, and a local oscillator that outputs the local oscillation signal that is synchronized with the reception frequency of the carrier frequency is provided.
A carrier recovery circuit.

Images