JP2008147788A - Phase locked loop circuit, synchronization detection circuit, and broadcast receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To output the reproducing signals of the same frequency and the same phase as input signals with a simple configuration. <P>SOLUTION: The phase locked loop circuit 1 matches the frequency by a first feedback loop composed of a VCO 13, a mixer 11 and an LPF 12, supplies control signals obtained in the first feedback loop to a second feedback loop composed of a VCO 23, a mixer 21, an LPF 22 and an adder 24, and thus outputs the reproducing signals whose frequency and phase are both same as the ones of the input signals from the second feedback loop. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a phase synchronization circuit that reproduces an output signal having the same frequency and phase as an input signal, a synchronous detection circuit using the same, and a broadcast receiving apparatus. In particular, the period and phase are accurately synchronized with a simple configuration. The present invention relates to a phase synchronization circuit, a synchronous detection circuit using the same, and a broadcast receiving apparatus.

  2. Description of the Related Art Conventionally, a so-called PLL (Phase-locked loop) that outputs a signal having the same frequency and phase synchronization as an input AC signal from another oscillator by feedback control is known.

  As the simplest circuit configuration example of this phase synchronization circuit, there is a configuration in which an input signal and an output of a voltage controlled oscillator (VCO) are mixed, and the mixer output is smoothed and fed back to the VCO.

  However, with such a configuration, the frequency and phase cannot be accurately synchronized. For example, even if the frequency of the output signal is matched to the input signal, a difference is required between the input signal and the output signal in order to obtain a control signal for oscillating the VCO at that frequency. Appeared as.

  Therefore, for example, when a reproduction signal having the same cycle and phase as the input signal is required, as in the case of receiving an AM broadcast, detecting a carrier wave, and extracting the original signal by synchronous detection, Patent Documents 1 to A complicated configuration as disclosed in FIG.

  Specifically, Patent Document 1 discloses a configuration in which a phase pull-in operation is performed after performing a frequency pull-in operation. Similarly, Patent Document 2 discloses a technique for tracking an initial frequency error and compensating for a phase error after frequency lock. Patent Document 3 discloses a configuration having a frequency error estimation circuit and a phase-locked loop circuit.

Japanese Patent Laid-Open No. 11-12099 Japanese Patent Laid-Open No. 11-74940 JP-A-8-191294

  However, since the complexity of the phase synchronization circuit leads to an increase in cost and size, it has been required to simplify the circuit configuration as much as possible and to synchronize the period and phase with a simple configuration with high accuracy.

  The present invention has been made in order to solve the above-described problems in the prior art and to solve the problems. A phase synchronization circuit for accurately synchronizing the period and phase with a simple configuration, and synchronous detection using the same. An object is to provide a circuit and a broadcast receiving apparatus.

  In order to solve the above-described problems and achieve the object, in the phase locked loop, the synchronous detection circuit, and the broadcast receiving apparatus according to the present invention, an error output between the first oscillation output output from the first oscillation means and the input signal is obtained. A first feedback loop that feeds back to the first oscillating means as a first error output and synchronizes the frequency of the first oscillating output with the input signal; a second oscillating output output by the second oscillating means; and the input A second feedback loop that adds the first error output to an error output from the signal and feeds it back to the second oscillating means to synchronize the frequency and phase of the second oscillation output with the input signal. Thus, a reproduction signal having the same frequency and the same phase as the input signal is obtained.

  According to the present invention, since the phase synchronization circuit, the synchronization detection circuit, and the broadcast receiving apparatus can obtain a reproduction signal having the same frequency and phase with a simple configuration, the phase synchronization circuit, the synchronization detection circuit, and the small and low cost can be obtained. There is an effect that a broadcast receiving apparatus can be obtained.

  Exemplary embodiments of a phase locked loop, a synchronous detection circuit, and a broadcast receiving apparatus according to the present invention will be described below in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic configuration diagram showing a schematic configuration of a phase locked loop 1 which is an embodiment of the present invention. As shown in the figure, the phase locked loop 1 has a first feedback loop 10 and a second feedback loop 20 therein.

  Each of the first feedback loop 10 and the second feedback loop 20 has a configuration similar to an existing phase locked loop circuit. First, a specific example of an existing phase synchronization circuit is shown in FIG. The phase synchronization circuit 30 shown in the figure has one feedback loop therein.

  In this feedback loop, a voltage controlled oscillator (VCO) 33, which is an oscillator for controlling the oscillation frequency with a voltage (control voltage), is incorporated. Then, the mixer 31 mixes the output of the VCO 33 and the input signal, and the output of the mixer 31 is smoothed by an LPF (Low-Pass Filter) 32 and fed back as a control voltage of the VCO 33.

  By this feedback loop, the frequency of the signal output from the VCO 33 becomes equal to the frequency of the input signal. However, when the frequency and phase of the output signal of the VCO 33 completely match the input signal and the output of the LPF 32 becomes 0, the VCO 33 cannot be controlled and the VCO 33 diverges, so the VCO 33 oscillates at the same frequency as the input signal. In order to achieve this, a difference is required between the input signal and the output signal, and this difference appears as a difference in phase.

  The first feedback loop 10 shown in FIG. 1 includes a VCO 13, a mixer 11, and an LPF 12 in the same manner as the phase synchronization circuit 30. The mixer 11 mixes the output of the VCO 13 and the input signal, and the LPF 12 smoothes the output of the mixer 11 and feeds it back as a control signal of the VCO 13. The difference is that the output is supplied externally.

  Accordingly, the operation of the first feedback loop 10 is the same as that of the phase synchronization circuit 30, and the VCO 13 outputs a signal having the same frequency as the input signal but shifted in phase.

  On the other hand, the second feedback loop 20 includes an adder 24 in addition to the VCO 23, the mixer 21, and the LPF 22. Then, after the mixer 21 mixes the output of the VCO 23 and the input signal, and the LPF 22 smoothes the output of the mixer 21, the adder 24 outputs the output of the LPF 12 output from the first feedback loop 10 to the output of the LPF 22. Is added. The output of the adder 24 is fed back as a control signal for the VCO 23, and the output of the VCO 23 is supplied to the outside as a reproduction output of the phase synchronization circuit 1.

  In the second feedback loop 20, a control signal for driving the VCO 23 at the same frequency as the input signal is given from the first feedback loop 10. Therefore, even when the frequency and phase of the output signal of the VCO 23 completely match the input signal and the output of the LPF 22 becomes 0, the control signal for the VCO 23 does not become 0, and the divergence of the VCO 23 can be prevented. it can.

  An example of the operation of the phase synchronization circuit 1 is shown in FIG. First, in the first feedback loop 10, the input signal and the VCO 13 have the same frequency and are locked in a phase shifted state. If the output of the LPF at this time is sin (φ), the first feedback loop 10 controls the VCO 13 with this sin (φ) and supplies sin (φ) to the second feedback loop 20. Become.

  In the second feedback loop, sin (φ) is added to the output of the LPF 22 and used as a control signal for the VCO 23. Therefore, the input signal and the output signal of the VCO 23 have the same frequency and the same phase, and the output of the LPF 22 is 0. Lock with.

  Therefore, when the signal output from the VCO 23 is extracted, a reproduction signal having the same frequency and phase as the input signal can be obtained.

  As described above, the phase locked loop 1 has a shape in which two feedback loops corresponding to the conventionally known simple phase locked loop 30 are connected, and the frequency is adjusted by the first feedback loop. It operates to match the phase in the feedback loop.

  A configuration example of a synchronous detection circuit using the phase synchronization circuit 1 is shown in FIG. The synchronous detection circuit shown in the figure has a phase synchronization circuit 1, a mixer 41, and an LPF 42 therein. When the synchronous detection circuit 40 receives, for example, an AM signal, the received signal is input to the mixer 41 and the phase synchronization circuit 1.

  The phase synchronization circuit 1 reproduces the AM signal carrier wave and inputs it to the mixer 41. Therefore, the signal before modulation can be taken out by multiplying the output of the mixer 41 by the LPF 42.

  A configuration example of a broadcast receiving apparatus using the synchronous detection circuit 40 is shown in FIG. In the configuration example shown in the figure, the broadcast receiving apparatus 50 receives a broadcast by an antenna 51, converts a radio frequency to an intermediate frequency by an RF / IF 52, and after passing through an amplifier 53, an oscillator 58, a mixer 54, 56. The I and Q signals are taken out by the analog-digital converters 55 and 57.

  The I signal and the Q signal are input to the signal processing unit 60 and demodulated by the synchronous detection circuit 40 inside the signal processing unit 60 to perform signal processing.

  By the way, in the broadcast reception, the amplitude of the input signal obtained by the change in the reception state changes. In order to cope with such fluctuations of the input signal, it is preferable to provide a normalization circuit for normalizing the input signal as shown in FIG.

  In the synchronous detection circuit 40a shown in FIG. 6, the amplitude of the input signal is calculated, and the smoothed version is sampled and held. Further, the first feedback 10 a and the second feedback 10 b of the phase synchronization circuit 1 a have dividers 15 and 25.

  Then, by dividing the output of the LPFs 12 and 22 by the value held by the normalization circuit 70, the output of the phase synchronization circuit 1a is stabilized with respect to signal amplitude fluctuations.

  As described above, the phase locked loop 1 according to the present embodiment adjusts the frequency in the first feedback loop including the VCO 13, the mixer 11, and the LPF 12, and the control signal obtained in the first feedback loop is the VCO 23, By supplying the second feedback loop including the mixer 21, the LPF 22, and the adder 24, a reproduction signal having the same frequency and phase as the input signal can be output from the second feedback loop.

  Therefore, the configuration of the phase synchronization circuit can be simplified, and the synchronous detection circuit and the broadcast receiving apparatus can be simplified by using this phase synchronization circuit.

  As described above, the phase synchronization circuit, the synchronous detection circuit, and the broadcast receiving apparatus according to the present invention synchronize the period and phase with a simple configuration with high accuracy, and are useful for downsizing and cost reduction of the apparatus.

1 is a schematic configuration diagram showing a schematic configuration of a phase locked loop according to an embodiment of the present invention. It is explanatory drawing explaining the structure of the conventional phase-locked loop circuit. It is explanatory drawing explaining operation | movement of the phase locked loop circuit concerning the Example of this invention. 1 is a schematic configuration diagram showing a schematic configuration of a synchronous detection circuit according to an embodiment of the present invention. It is a schematic block diagram which shows schematic structure of the broadcast receiver concerning the Example of this invention. It is explanatory drawing explaining the synchronous detection circuit which normalizes the amplitude of an input signal.

Explanation of symbols

1, 1a, 30 Phase-locked loop 10.10a First feedback loop 11, 21, 31, 41, 54, 56 Mixer 12, 22, 32, 42 LPF
13, 23, 33 VCO
15, 25 Divider 24 Adder 20, 20a Second feedback loop 40, 40a Synchronous detection circuit 50 Broadcast receiving device 51 Antenna 52 RF / IF
53 Amplifier 59 Oscillator 55, 57 Analog to Digital Converter 60 Signal Processing Unit 70 Normalization Circuit

Claims (6)

An error output between the first oscillation output outputted from the first oscillation means and the input signal is fed back to the first oscillation means as a first error output, and the frequency of the first oscillation output is synchronized with the input signal. 1 feedback loop,
The first error output is added to the error output between the second oscillation output output from the second oscillating means and the input signal and fed back to the second oscillating means. The frequency and phase of the second oscillation output A second feedback loop that synchronizes to the input signal;
And a phase synchronization circuit for outputting the second oscillation output as a reproduction output externally.   The first feedback loop includes a mixer for mixing the first oscillation output and the input signal, a smoothing filter for smoothing the output of the mixer, and the first oscillation means driven by the output of the smoothing filter. The phase locked loop circuit according to claim 1, comprising:   The second feedback loop includes a mixer that mixes the second oscillation output and the input signal, a smoothing filter that smoothes the output of the mixer, and adds the first oscillation output to the output of the smoothing filter. 3. The phase locked loop circuit according to claim 1, further comprising an adder and the second oscillating means driven by the output of the adder. An error output between the first oscillation output outputted from the first oscillation means and the input signal is fed back to the first oscillation means as a first error output, and the frequency of the first oscillation output is synchronized with the input signal. 1 feedback loop,
The first error output is added to the error output between the second oscillation output output from the second oscillating means and the input signal and fed back to the second oscillating means. The frequency and phase of the second oscillation output A second feedback loop that synchronizes to the input signal;
Synchronous detection means for performing synchronous detection using the second oscillation output and the input signal;
A synchronous detection circuit comprising:   5. The synchronous detection circuit according to claim 4, further comprising normalization means for normalizing the input signal. An error output between the first oscillation output outputted from the first oscillation means and the input signal is fed back to the first oscillation means as a first error output, and the frequency of the first oscillation output is synchronized with the input signal. 1 feedback loop,
The first error output is added to the error output between the second oscillation output output from the second oscillating means and the input signal and fed back to the second oscillating means. The frequency and phase of the second oscillation output A second feedback loop that synchronizes to the input signal;
Synchronous detection means for performing synchronous detection using the second oscillation output and the input signal;
A broadcast receiving apparatus, wherein the received broadcast signal is synchronously detected by the synchronous detection means.

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