JP2005123483A - Plasma-etching method of semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma-etching method of a semiconductor for plasma-etching the outer periphery of a flatness applicable region with high flatness. <P>SOLUTION: A value of thickness data of a measurable actually measured outermost periphery of the flatness applicable region multiplied by a coefficient S is to be virtual thickness data of the outer periphery where the measurement of the flatness applicable region is difficult. The outer periphery of the region is plasma-etched while partially controlling a plasma-etched amount according to the thickness of the flatness applicable region based on the data. As a result, reliability in the virtual thickness data is higher than a conventional case where the thickness data of the actually measured outermost periphery of the region is regarded as the virtual thickness data of the region, and the outer periphery of the flatness applicable region can be plasma-etched with high flatness. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a plasma etching method for a semiconductor wafer, and more particularly to a plasma etching method for a semiconductor wafer in which the outer periphery of a flatness application region is plasma etched with high flatness.

In recent years, in order to improve the flatness of the surface on which silicon wafer devices are formed, a method for measuring the thickness of a polished silicon wafer and plasma etching the surface of the wafer based on the thickness data has been developed. ing.
Specifically, for example, the thickness in the flatness application area (FQA: Flatness Quality Area) of the surface of the silicon wafer is measured by a commercially available wafer thickness measuring machine, and a commercially available plasma etching is performed based on the thickness data. Using the apparatus, the flatness application region is plasma etched while controlling the plasma etching amount by adjusting the speed at which the plasma is moved in the surface direction of the silicon wafer. That is, in the thick part of the silicon wafer, the etching amount is increased by moving the plasma at a low speed. On the other hand, in the thin part, the plasma is moved at a high speed to reduce the etching amount.

However, according to the wafer thickness measuring machine, it is possible to measure the thickness of the wafer in the flatness application area of the silicon wafer because of the configuration of the measuring machine. It was limited to a portion from the outermost periphery of the degree application area to the inside 3 mm (measured outermost periphery) in the radial direction. Therefore, the outer peripheral portion of the flatness application area outside it cannot actually measure the thickness of the wafer.
Therefore, at the time of plasma processing, the plate thickness data of the measured outermost circumference of this flatness application region is regarded as the plate thickness data of the outer peripheral portion that is difficult to measure, and based on the virtual plate thickness data with poor reliability, The outer periphery was plasma etched.

  Therefore, as a result of diligent research, the inventors have determined that the virtual plate thickness data obtained by multiplying the measured outermost plate thickness data by a specific coefficient is the virtual plate thickness data of the outer peripheral portion of the flatness application area. As a result, it was found that the outer peripheral portion of the flatness application region can be plasma etched with higher flatness, and the present invention was completed.

  Therefore, an object of the present invention is to provide a plasma etching method for a semiconductor wafer that can perform plasma etching on the outer peripheral portion of the flatness application region with high flatness.

  The invention described in claim 1 is a step of measuring a plate thickness of a portion excluding the outer peripheral portion of the flatness application region in a flatness application region of a surface on which a device of a semiconductor wafer is formed, and the measured plate In the plasma etching method of a semiconductor wafer, comprising the step of plasma etching the flatness application region while controlling the amount of plasma etching based on the thickness data, the plate thickness data of the outermost periphery of the measurement portion of the flatness application region Is multiplied by a predetermined coefficient to obtain virtual plate thickness data of the outer periphery of the flatness application region, and the outer periphery of the flatness application region is controlled while controlling the amount of plasma etching based on the obtained virtual plate thickness data. A method for plasma etching of a semiconductor wafer in which a portion is plasma etched.

According to the first aspect of the present invention, the virtual plate thickness data of the outer peripheral portion of the flatness application region is obtained by multiplying the plate thickness data of the outermost peripheral portion of the measurement portion of the flatness application region by a predetermined coefficient. Based on the plate thickness data, the outer peripheral portion of the flatness application region is processed while partially controlling the plasma etching amount according to the thickness of the flatness application region. As a result of plasma etching, irregularities on the wafer surface are eliminated.
As a result, the virtual plate thickness data is compared with the case where plasma etching is performed by regarding the plate thickness data of the measured outermost circumference of the flatness application region as virtual plate thickness data of the outer periphery of the flatness application region as in the conventional method. Therefore, the outer peripheral portion of the flatness application region can be plasma etched with high flatness.

Examples of the semiconductor wafer include a silicon wafer and a gallium arsenide wafer. Further, the semiconductor wafer may be a polished wafer or other processed wafer.
The flatness application region is a flatness standard application region that does not include a chamfered portion that is an exclusion region on the surface of the semiconductor wafer.
Further, the outer peripheral portion of the flatness application region is an outer peripheral portion of the flatness application region where it is difficult to measure the thickness of the wafer.
A commercially available electrostatic capacitance type or laser type can be adopted as the thickness measuring device for the semiconductor wafer.

Plasma etching is a type of dry etching that uses reactive gas plasma. Chemically active atoms or molecules (radicals) generated in high-frequency or microwave discharge plasma are used as reactive species. It is a chemical reaction.
The etching rate of plasma etching is 0.5 to 1.0 μm / min for a 200 mm wafer. The GBIR of the semiconductor wafer after plasma etching has a high flatness of around 0.2 μm.
As a method for controlling the etching amount, for example, the magnitude of the high frequency or microwave supplied to the etching gas is controlled, or the speed at which the plasma and / or the semiconductor wafer is relatively moved in the wafer surface direction is changed.

A PACE (Plasma Assisted Chemical Etching) method is known as a method suitable for uniformly etching the surface of a semiconductor wafer. This is one of the plasma-assisted chemical etching methods developed by "Heughs Danbury Optical Systems", and the thickness of the semiconductor wafer after plasma etching is fed back by feeding back the wafer shape information before etching to the partial etching cost. This is a method for improving accuracy and flatness accuracy.
The coefficient used when obtaining the virtual plate thickness data of the outer peripheral portion of the flatness application region is not limited. If this coefficient is small, the etching amount of plasma etching becomes large, and the flatness application region tends to sag at the outer periphery. On the contrary, if the coefficient is large, the etching amount of plasma etching becomes small, and the flatness application region tends to stand on the outer periphery.

The invention according to claim 2 is the semiconductor wafer plasma etching method according to claim 1, wherein the coefficient in consideration of the shape of the semiconductor wafer in the measured plate thickness data is 0.5 to 1.5.
A preferable coefficient is 1.0 to 1.5. If it is less than 1.0, the etching amount of plasma etching becomes too large, and the outer periphery sagging of the flatness application region is likely to occur. On the other hand, if it exceeds 1.5, the etching amount of plasma etching becomes too small, and the outer periphery of the flatness application region tends to occur.

  According to the present invention, the product obtained by multiplying the measured outermost plate thickness data that can be measured in the flatness application region by a predetermined coefficient is regarded as the virtual plate thickness data in the outer peripheral portion where it is difficult to measure the flatness application region, Based on this virtual plate thickness data, the outer peripheral portion of the flatness application region is processed while controlling the plasma etching amount. Therefore, the reliability of the virtual plate thickness data is improved, and the outer peripheral portion of the flatness application region has a high flatness. Can be plasma etched.

  Hereinafter, a semiconductor wafer plasma etching method according to an embodiment of the present invention will be described.

  FIG. 1 is a flow sheet showing a semiconductor wafer manufacturing method to which a semiconductor wafer plasma etching method according to one embodiment of the present invention is applied. FIG. 2A is an enlarged view of a main part of a wafer thickness measuring machine used in a semiconductor wafer plasma etching method according to one embodiment of the present invention. FIG. 2B is an enlarged view of a main part of another wafer thickness measuring machine used in the semiconductor wafer plasma etching method according to one embodiment of the present invention. FIG. 3 is a schematic view of a plasma etching apparatus used in a semiconductor wafer plasma etching method according to an embodiment of the present invention. FIG. 4 is an enlarged sectional view of the main part of the semiconductor wafer during plasma etching in the semiconductor wafer plasma etching method according to one embodiment of the present invention. FIG. 5 is a perspective view showing contour lines of a semiconductor wafer manufactured by using the semiconductor wafer plasma etching method according to one embodiment of the present invention.

As shown in FIG. 1, in this embodiment, the surface is subjected to the steps of slicing, chamfering, lapping, etching, primary surface polishing, wafer plate thickness measurement, surface plasma etching, final polishing, and cleaning. A mirror-finished semiconductor wafer is produced.
Hereinafter, each process will be described in detail.
The silicon ingot pulled up by the CZ method is sliced into an 8-inch silicon wafer having a thickness of about 860 μm in the slicing step (S101).
Next, this sliced wafer is chamfered into a predetermined shape by pressing a chamfering grindstone on its outer peripheral portion in the subsequent chamfering step (S102). The chamfering grindstone is a # 600 metal bond cylindrical grindstone. Thus, the outer peripheral portion of the silicon wafer is processed into a predetermined rounded shape (for example, a MOS type chamfered shape).

Next, a wrapping step (S103) is performed. In this step, the silicon wafer is placed between lap surface plates parallel to each other, and thereafter, a wrap liquid that is a mixture of alumina abrasive grains, a dispersant, and water is poured between the wrap surface plates. Then, the front and back surfaces of the silicon wafer are mechanically lapped by rotating and sliding under pressure. At that time, the amount of wrapping of the silicon wafer is about 40 to 100 μm in total on both the front and back surfaces of the wafer.
Then, the wrapped wafer is etched (S104). Specifically, the silicon wafer is immersed for a predetermined time in a mixed acid solution (normal temperature to 50 ° C.) in which hydrofluoric acid and nitric acid are mixed. For example, alkaline etching using NaOH, KOH or the like may be used. When etching is performed, a large amount of bubbles are generated on both sides of the silicon wafer. As a result, undulations with a period of about 0.5 to 20 mm appearing on both the front and back surfaces of the silicon wafer, with minute irregularities having a height of about several nm to 200 nm.
After this etching, the outer peripheral portion of the silicon wafer may be subjected to PCR processing. In this processing, a known PCR processing apparatus is used. For example, a device that rotates a cylindrical urethane buff with a motor.

Next, the lapped silicon wafer surface is first polished (S105).
Specifically, only the surface of the silicon wafer is subjected to primary polishing by using a polishing apparatus having a polishing head and a lower surface plate that are arranged to face each other and having a polishing cloth spread only on the upper surface of the lower surface plate. That is, the silicon wafer is fixed to the carrier plate with the surface facing downward, and the surface of the wafer is primarily polished with a polishing cloth in which a nonwoven fabric is impregnated and cured with urethane resin while supplying a slurry containing loose abrasive grains. The polishing amount is about 5 to 20 μm.

Subsequently, the plate thickness in the flatness application region on the surface of the silicon wafer is inspected (S106). For this inspection, a capacitance type plate thickness measuring machine A shown in FIG. 2A is used. This measuring machine A measures the thickness of the wafer by detecting the positions of the front and back surfaces of the wafer using two capacitance sensors arranged on both front and back sides of the wafer. Further, a plate thickness measuring machine A that also functions as a flatness measurement shown in FIG. 2B can be used. In this type, the front and back surfaces of a silicon wafer are respectively irradiated with laser light, and by receiving this, the flatness of each surface and the thickness of the wafer are measured.
However, here, a portion from the outermost periphery of the flatness application region to the inner side 3 mm in the radial direction (measured outermost periphery) is measured, and the outer peripheral portion d of the flatness application region outside the flatness application region is a part of the measured outermost periphery. The plate thickness data multiplied by a coefficient S = 1.0 to 1.5 is used as partial virtual plate thickness data of the outer peripheral portion d of the flatness application region. This outer peripheral part d is an area where plate thickness cannot be measured.

Thereafter, based on the obtained thickness data (including virtual thickness data) of the silicon wafer, the flatness application region on the wafer surface is plasma-etched (S107).
That is, plasma assisted chemical etching is performed by the plasma etching apparatus 20 shown in FIG. This plasma etching is performed at a frequency of 2 with an etching gas SF ₆ flowing in the etching reaction furnace at a rate of 100 to 1000 cc / min using a microwave power source 21 in an etching reaction furnace that is made negative by suction pumps P1 and P2. A microwave of .45 GHz and a power of 300 to 600 watts is continuously applied. As a result, the etching gas SF ₆ is excited from the plasma discharge tube 22 to generate plasma. That is, the etching gas SF ₆ is chemically activated in the plasma discharge tube 22 by receiving plasma energy.

Thereafter, the chuck 23 holding the silicon wafer W is moved along the surface of the silicon wafer W while changing the moving speed in accordance with the thickness of the waviness (undulation) on the surface of the wafer (see FIG. 4). As a result, the radical species 25 excited by the plasma are sequentially supplied to a predetermined position of the silicon wafer W. As a result, the silicon under the plasma region is etched at an etching rate of about 1 μm / second and an etching amount of 1 to 5 μm according to the thickness of the waviness (for example, 1 to 5 μm).
At that time, the outer peripheral portion d of the flatness application region is plasma etched in series with other portions of the flatness application region based on virtual plate thickness data obtained by multiplying the measured outermost periphery by a coefficient. Thereby, the unevenness is completely removed from the entire flatness application region including the outer peripheral portion d (see FIG. 5).

In the conventional method, the plate thickness data of the measured outermost circumference of the flatness application area is regarded as the virtual plate thickness data of the outer circumference of the flatness application area as it is, and plasma etching is performed. The sex was low. On the other hand, in this embodiment, since the virtual plate thickness data is obtained by multiplying the measured outermost circumference by a coefficient, the reliability of the virtual plate thickness data is increased, and the outer peripheral portion d of the flatness application region is high. Plasma etching can be performed with flatness.
In addition, since plasma etching is performed after the primary polishing here, the amount of polishing necessary for mirroring is reduced, and the flatness of the surface of the silicon wafer W (GBIR 0.2 μm or less) is increased.
Thereafter, finish polishing is performed on the surface of the silicon wafer W (S108). The polishing cloth used is a suede type in which a urethane resin is foamed on a non-woven base cloth for final polishing. The polishing amount is about 0.1 to 2 μm.
Next, the silicon wafer W is finished and cleaned (S109). This cleaning is RCA cleaning based on two types of cleaning liquids, SC-1 and SC-2.

Here, referring to FIG. 6 and FIG. 7, when the plasma etching method of this embodiment is adopted and the outer peripheral portion of the flatness application region of the silicon wafer is actually plasma etched, the site flatness of the outer peripheral portion is obtained. Degree result is shown.
FIG. 6 is a schematic diagram showing the site number of the outer periphery of the flatness application region. FIG. 7 is a graph showing the relationship between the coefficient and the flatness at each site in the outer peripheral portion of the flatness application region.
As is apparent from the graph of FIG. 7, the SBIR value in the outer peripheral portion of the flatness application region is particularly small when the coefficient S = 1.0, the coefficient S = 1.2, and the coefficient S = 1.5. Thereby, the flatness of this outer peripheral part increased more than the time of other coefficients (S = 0.5, S = 0.8, S = 2.0).

It is a flow sheet which shows the manufacturing method of the semiconductor wafer to which the plasma etching method of the semiconductor wafer concerning one example of this invention was applied. (A) It is a principal part enlarged view of the wafer board thickness measuring machine used for the plasma etching method of the semiconductor wafer concerning one Example of this invention. (B) It is a principal part enlarged view of the other wafer board thickness measuring machine used for the plasma etching method of the semiconductor wafer which concerns on one Example of this invention. It is a schematic diagram of the plasma etching apparatus used for the plasma etching method of the semiconductor wafer concerning one Example of this invention. It is a principal part expanded sectional view of the semiconductor wafer during the plasma etching in the plasma etching method of the semiconductor wafer concerning one Example of this invention. It is the perspective view which showed the semiconductor wafer produced using the plasma etching method of the semiconductor wafer concerning one Example of this invention with the contour line. It is a schematic diagram which shows the site number of the outer peripheral part of a flatness application area | region. It is a graph which shows the relationship between the coefficient in each site of the outer peripheral part of a flatness application area | region, and flatness.

Explanation of symbols

W Silicon wafer (semiconductor wafer),
S factor.

Claims (2)

Measuring the plate thickness of the portion excluding the outer peripheral portion of the flatness application region in the flatness application region of the surface on which the device of the semiconductor wafer is formed;
In the plasma etching method of a semiconductor wafer comprising the step of plasma etching the flatness application region while controlling the plasma etching amount based on the measured plate thickness data,
Multiplying a predetermined coefficient to the outermost plate thickness data of the measurement portion of the flatness application region to obtain virtual plate thickness data of the outer peripheral portion of the flatness application region,
A plasma etching method for a semiconductor wafer, in which an outer peripheral portion of the flatness application region is plasma etched while controlling a plasma etching amount based on the obtained virtual plate thickness data.   The plasma etching method for a semiconductor wafer according to claim 1, wherein the coefficient in consideration of the shape of the semiconductor wafer in the measured plate thickness data is 0.5 to 1.5.

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