JP2002299290A - Manufacturing method for semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor wafer which can remove damages to an outer circumference of a wafer, caused by friction in a wafer-holding hole in a rough polishing process, in a PCR process thereafter. SOLUTION: The PCR process is inserted between the rough polishing process and a finish polishing process. As a result, even if the beveled surface of a silicon wafer is brought into contact with, for instance, the wafer-holding hole forming part of a carrier plate and flaws caused by friction are produced on an outermost circumference (beveled surface) in the rough polishing process, the flaws and damages on the outermost circumference can be removed in the PCR process thereafter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor wafer, and more particularly, to a method for producing a semiconductor wafer by using a wafer holding plate in a rough polishing process, which damages an outer peripheral portion of the semiconductor wafer due to contact with an inner wall of a wafer holding hole. And a method of manufacturing a semiconductor wafer to be removed by the method.

[0002]

2. Description of the Related Art An example of a conventional standard wafer processing process will be described with reference to FIG. FIG. 2 is a flowchart showing a method for manufacturing a semiconductor wafer according to a conventional means. First, in a slicing step (S201), a silicon wafer is sliced from a block-cut ingot. In the next primary chamfering step (S202), rough chamfering is performed on the outer peripheral portion of the silicon wafer. In the following lapping step (S203), both sides of the silicon wafer are lapped by a lapping machine. In the case of this lapping step, usually, the processing is about 20 to 40 μm on one side and about 40 to 80 μm on both sides.

Thereafter, a finishing chamfering step (S204) is performed as required. Here, the outer peripheral surface of the primary chamfered silicon wafer is finish chamfered. Subsequently, the silicon wafer is immersed in a predetermined etching solution (mixed acid or alkali + mixed acid) to remove distortion in the lapping process, distortion in the chamfering step, and the like (S205).
In this case, usually, 10 to 20 μm on one side and 20 to 20 μm on both sides.
Etch 40 μm. Next PCR (Polish
Step (S20)
In 6), PCR processing is performed on the outer peripheral portion of the silicon wafer in a state where the front and back surfaces of the silicon wafer are attracted to the chuck. In the PCR processing, the chamfered surface is mirror-finished with a polishing cloth.

In the subsequent primary polishing step (S207), both sides of the silicon wafer are primarily polished using a double-side polishing apparatus. At this time, both sides of the silicon wafer are
Each is polished by 5 to 10 μm. Thereby, the unevenness of the silicon wafer after the etching is removed, and the flatness is improved. In the subsequent finish polishing step (S208),
Finish polishing is performed with a polishing amount of 1 μm or less. Then, they are subjected to final cleaning and inspection, and then shipped to a device maker of the order receiving party.

Here, the primary polishing step using the double-side polishing apparatus will be specifically described with reference to FIGS. FIG.
FIG. 1 is a plan view showing a use state of a general semiconductor wafer double-side polishing apparatus. FIG. 4 is an enlarged cross-sectional view of S4-S4 of FIG. The conventional double-side polishing apparatus 100 for semiconductor wafers shown in FIGS. 3 and 4 inserts and holds a silicon wafer W into a plurality of wafer holding holes 102 formed in a carrier plate (wafer holding plate) 101 and polishes from above. This is a configuration in which the front and back surfaces of each silicon wafer W are simultaneously polished while supplying a polishing liquid containing abrasive grains to the silicon wafer W. That is, a carrier plate 101 having an outer gear 103 on an outer peripheral portion is provided between a rotatable sun gear 110 and an internal gear 111 so as to rotate and revolve, and the silicon wafer W held by the carrier plate 101 is rotated. Both the front and back surfaces (upper and lower surfaces) are polished by pressing and sliding with an upper surface plate 106 and a lower surface plate 107 having polishing cloths 104 and 105 spread on opposing surfaces, respectively.

[0006]

However, according to such a conventional method of manufacturing a double-side polished wafer, the PC
The R step (S206) was performed before the primary polishing step (S207). Therefore, as shown in the partial enlarged view of FIG. 4, during the first polishing, the outer peripheral chamfered surface of the silicon wafer W mirror-finished in the immediately preceding PCR step comes into contact with the inner peripheral surface of the wafer holding hole 102 of the carrier plate 101. Rubbing may damage the outermost peripheral portion of the silicon wafer W.

[0007] Then, as a result of earnest research, the inventor found that PC
If the rough polishing step is performed before the R step, even if the outermost peripheral portion of the semiconductor wafer is rubbed during the rough polishing, the subsequent wafer is not provided with a new step of removing damage due to the rubbing. In the PCR step, which is one of the basic steps in the production, it has been found that it is possible to remove the scratch on the outermost peripheral portion due to this rubbing, and completed the present invention.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to remove, in a polishing step, damage caused on an outer peripheral portion of a semiconductor wafer due to contact with a formation portion of a wafer holding hole formed in a wafer holding plate in a subsequent PCR step. It is an object of the present invention to provide a method for manufacturing a semiconductor wafer that can be used.

[0009]

According to the first aspect of the present invention, a chamfered semiconductor wafer is inserted and held in a wafer holding hole formed in a wafer holding plate, and the semiconductor wafer is roughly polished. Rough polishing process and after rough polishing,
Mirror finish for chamfered surface of semiconductor wafer
This is a method for manufacturing a semiconductor wafer, comprising a CR process and a finish polishing process of finish polishing the polished surface of the semiconductor wafer after PCR processing. Semiconductor wafers include silicon wafers and gallium arsenide wafers.

The semiconductor wafer subjected to the rough polishing may be an etched wafer which has been etched after chamfering. This etching step may be an acid etching using a mixed acid obtained by mixing hydrofluoric acid and nitric acid. NaOH, K
Alkali etching using an aqueous solution such as OH may be used.

Rough polishing is performed on one side of a semiconductor wafer (usually,
It may be applied only to the surface on which the device is mounted) or may be applied to both front and back surfaces. This rough polishing may be performed only once (primary polishing) or divided into two or more times (primary polishing, secondary polishing ...). That is, the rough polishing means all polishing steps before the final polishing for final mirror finish. The polishing apparatus for rough polishing is not limited. A single wafer type in which only one semiconductor wafer is polished, or a batch type in which a plurality of semiconductor wafers are polished at once may be used.
Further, a single-side polishing apparatus for polishing only one side of a semiconductor wafer, or a double-side polishing apparatus for polishing both front and back surfaces of a semiconductor wafer may be used. However, a wafer holding plate having a wafer holding hole capable of holding a semiconductor wafer must be provided. For example, a double-side polishing apparatus having a planetary gear structure shown in FIG. 3 may be used. Further, only one side of the semiconductor wafer may be polished by the double-side polishing apparatus. Further, there is provided a polishing surface plate and a polishing head disposed opposite thereto, and a waxless type single-side polishing device for filling a semiconductor wafer with water via a back pad on a surface of the polishing head facing the polishing surface plate. May be. In the single-side polishing apparatus, a template having a wafer holding hole is provided on a surface of a polishing head facing a polishing platen. Inside the wafer holding hole of the template, the semiconductor wafer is sucked and held by the surface tension of the water impregnated in the back pad. Examples of the polishing cloth for rough polishing include a porous nonwoven cloth polishing cloth in which polyester felt is impregnated with polyurethane. Further, a foaming urethane type polishing cloth obtained by slicing a foamed urethane block may be used.

During polishing, a slurry containing free abrasive grains such as colloidal silica (silica sol) is usually supplied to the polishing surface of the polishing cloth. The polishing of the notch portion or the orientation flat portion of the semiconductor wafer may be performed simultaneously with the rough polishing, or may be performed before the rough polishing as a separate step. Prior to the rough polishing, the semiconductor wafer can be heat-treated to form an oxide film on the entire silicon wafer to increase the strength of the chamfered portion and prevent generation of oxygen donors. For example, heat treatment using a diffusion furnace (WH
At the time of T (Wafer Heat Treatment), a large number of silicon wafers are inserted into a quartz heat treatment boat and heated in an inert gas. In addition, ozone oxidation may be performed on the entire silicon wafer. That is, an ozone gas may be added to the dry oxygen gas introduced into the quartz reaction tube to form an oxide film having low trap and high reliability over the entire wafer.

In the PCR step, one side or both sides of the semiconductor wafer is adsorbed to the holding plate. However, even if the adsorption and holding of only one side is more effective, even if the adsorption surface has an effect on the adsorption surface, by finishing and polishing the adsorption surface,
It can be eliminated. Further, as a PCR processing apparatus, for example, a cylindrical urethane buff is rotated, and the outer peripheral surface of the semiconductor wafer sucked and held on the holding plate is brought into contact with the outer peripheral surface of the rotating buff, and the outer peripheral surface is rotated. Mirror finishing can be used. Then, when finish-polishing the suction / holding surface of the semiconductor wafer, a finish polishing apparatus is used. As this apparatus, a single-side polishing apparatus can be employed. The wafer surface to be finish-polished is a suction / holding surface in the PCR step when the suction surface has an influence on the suction surface, and is a non-suction surface when there is no effect.

[0014]

According to the present invention, the PCR step is arranged between the rough polishing step and the finish polishing step.
Even if the chamfered surface of the semiconductor wafer comes into contact with the formation portion of the wafer holding hole of the wafer holding plate provided in the polishing apparatus and scratches the outermost peripheral portion of the semiconductor wafer by rubbing, the semiconductor Damage due to rubbing of the outermost peripheral portion of the wafer can be removed. Also,
During the PCR processing, the semiconductor wafer is held on a holding plate of the PCR processing apparatus. At this time, even if the holding surface of the semiconductor wafer is damaged, it is removed in the next finish polishing step.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing a method for manufacturing a semiconductor wafer according to one embodiment of the present invention. As shown in FIG. 1, in this embodiment, the surface is processed through the steps of slicing, primary chamfering, lapping, finishing chamfering (when necessary), etching, primary polishing, PCR, finishing polishing, and cleaning. A mirror-finished semiconductor wafer is manufactured. Hereinafter, each step will be described in detail. The silicon ingot pulled up by the CZ method is sliced into an 8-inch silicon wafer having a thickness of about 860 μm in a slicing step (S101). Next, in the primary chamfering step (S102), the outer periphery of the sliced wafer is roughly chamfered into a predetermined shape by using a # 600 metal chamfering grindstone. Thus, the outer peripheral portion of the silicon wafer is formed into a predetermined rounded shape (for example, a MOS type chamfered shape).

Next, a lapping step (S103) is performed. In this step, a silicon wafer is placed between lapping plates parallel to each other, and a lapping liquid, which is a mixture of alumina abrasive grains, a dispersant, and water, is poured between the lapping plates.
Then, by rotating and sliding under pressure, the front and back surfaces of the silicon wafer are mechanically wrapped. Next, a finishing chamfering step (S104) is performed on the wrapped wafer as necessary. Here, the finish chamfering of the outer peripheral surface of the silicon wafer which has been primarily chamfered is performed. Subsequently, the finished chamfered silicon wafer is etched (S105). Specifically, a silicon wafer is immersed for a predetermined time in a mixed acid solution (normal temperature to 50 ° C.) in which hydrofluoric acid and nitric acid are mixed.

[0017] The etched wafer is subjected to a heat treatment step. In the heat treatment step, the etched wafer is heat-treated. As a result, an oxide film is formed on the entire silicon wafer, the strength of the chamfer is increased, and the generation of oxygen donors is prevented. For example, at the time of heat treatment using a diffusion furnace, a large number of silicon wafers are inserted into a quartz heat treatment boat and heated at 650 to 700 ° C. for about 15 minutes in an inert gas. In some cases, only the notch portion or only the orientation flat portion may be subjected to PCR processing on the etched wafer by a dedicated device.

Thereafter, the surface of the etched wafer is subjected to primary polishing using a double-side polishing machine (S106). Specifically, a silicon wafer is inserted into each wafer holding hole of the carrier plate, and a slurry containing free abrasive grains is supplied, and a nonwoven fabric is impregnated with a urethane resin and cured using two upper and lower polishing cloths. Next polishing. For example, the apparatus shown in FIGS. 3 and 4 is used. At the time of the first polishing, there is a concern that the chamfered surface of the silicon wafer comes into contact with the portion (peripheral wall surface) of the carrier plate where the wafer holding hole is formed, causing rubbing and damaging the outermost peripheral portion of the silicon wafer.

Next, the outer peripheral portion of the silicon wafer after the double-side polishing is subjected to PCR (S107). At the time of this processing, a well-known PCR processing apparatus is used. That is, here, a device for rotating a cylindrical urethane buff with a motor is employed. The urethane buff is rotated by the motor, and the outer peripheral surface of the silicon wafer is brought into contact with the outer peripheral surface of the rotating buff. Thereby, the outer peripheral surface of the wafer is mirror-finished. At this time, the silicon wafer has only one surface adsorbed and held by the holding plate. The suction source is a negative pressure generator connected to the holding plate via a hose or the like. Note that by performing this PCR processing, damage due to rubbing remaining on the outermost peripheral portion of the wafer is removed.

Thereafter, the surface of the silicon wafer is subjected to finish polishing (S108). As the polishing apparatus for the final polishing, a known polishing apparatus for polishing one side is used.
Use nonwoven fabric for final polishing. Polishing amount is 0.1 ~
It is about 2 μm. Also, at the time of this finish polishing, PC
Even if the holding surface of the silicon wafer sucked and held during the R processing is damaged, it is removed. On the other hand, if there is no damage due to adsorption, there is no particular problem. Next, finish cleaning of the silicon wafer is performed (S1).
09). This cleaning is RCA cleaning based on two types of cleaning liquids, SC-1 and SC-2.

As described above, since the primary polishing step is performed before the PCR step, if the chamfered surface of the silicon wafer has been damaged by the contact with the formation portion of the wafer holding hole during the primary polishing, However, even if a separate step for removing this damage is not newly provided, the outermost peripheral portion of the silicon wafer due to the rubbing can be removed by the subsequent PCR step.

[0022]

According to the present invention, since the semiconductor wafer is subjected to the PCR processing after the rough polishing, even if the outermost peripheral portion of the wafer may be rubbed by the rough polishing, the rubbing is performed in the subsequent PCR step. Scratches and damage at the outermost periphery can be removed. Mirroring of the chamfered surface can be maintained only by changing the process order.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a method for manufacturing a semiconductor wafer according to one embodiment of the present invention.

FIG. 2 is a flowchart showing a method for manufacturing a semiconductor wafer according to a conventional means.

FIG. 3 is a schematic plan view of a conventional semiconductor wafer double-side polishing apparatus in use.

FIG. 4 is an enlarged sectional view of S4-S4 of FIG. 3;

[Explanation of symbols]

 101 carrier plate (wafer holding plate), 102 wafer holding hole, W semiconductor wafer.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Etsuro Morita 1-5-1 Otemachi, Chiyoda-ku, Tokyo F-term in Mitsubishi Materials Silicon Corporation (reference) 3C058 AA07 CA01 DA06 DA17

Claims (1)

[Claims] 1. A rough polishing step of inserting and holding a chamfered semiconductor wafer into a wafer holding hole formed in a wafer holding plate and performing rough polishing on the semiconductor wafer; A method of manufacturing a semiconductor wafer, comprising: a PCR step of mirror-finishing a chamfered surface of a part;