JP2003229385A - Method for manufacturing semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor wafer capable of attaining a highly flat semiconductor wafer, in which a grinding amount can be decreased and grinding streaks do not exist. <P>SOLUTION: From the start of a spark-out in a surface grinding step to the end thereof, the number of times of rotations of a silicon wafer is set to six times or more, and the speed of the rotation of the silicon wafer is set to 10 rpm or smaller, while after surface grinding, since the silicon wafer is secondarily light-dried (an etching amount of 2 to 4 μm), a grinding amount can be decreased and reduction in a wafer planarity degree is suppressed. Further, it is possible to attain the high planarity silicon wafer in which grinding scars hardly exist even for a small grinding amount. For example, this may be 0.5 to 0.8 μm through TTV. A solution having higher selectivity to damages than primary etching is used in secondary etching. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor wafer, and more particularly, to a small amount of polishing during mirror polishing,
The present invention relates to a method for manufacturing a semiconductor wafer, which is capable of obtaining a semiconductor wafer having high flatness without grinding marks.

[0002]

2. Description of the Related Art In general silicon wafer manufacturing,
After slicing the ingot to produce a silicon wafer, the silicon wafer is sequentially subjected to steps of chamfering, lapping, etching and mirror polishing.
In this etching step, the wrapped wafer is immersed in an acidic etching solution such as mixed acid or an alkaline etching solution such as KOH to remove the distortion in the lapping process, the distortion in the chamfering step, and the like.

In the next mirror surface polishing step, the unevenness of the wafer surface generated in the etching step is removed by polishing to make it a mirror surface. Normally, the polishing amount of the silicon wafer surface is a dozen μ
m. In this case, it is generally known that if the polishing amount is large, the flatness of the polishing surface is deteriorated. That is, when the wafer surface, which was originally high in flatness, is further polished, a phenomenon in which the flatness greatly decreases when the polishing amount exceeds 10 μm occurs.
As a result, the TTV of the etched wafer is 1.5 to 3 μm.
However, the flatness of the surface of the silicon wafer after polishing was improved only to about 1.2 to 1.5 μm. The polishing cloth used is a soft polishing cloth such as SUBA600 (manufactured by Rodel Nitta).

Therefore, conventionally, in order to reduce the polishing amount at the time of mirror polishing, for example, # 20 is formed on the surface of the etched wafer.
With a resinoid grinding wheel of No. 00, a surface grinding of about 7 to 8 μm is performed (TTV is about 0.5 to 1.0 μm), and then the surface is mirror-polished with a soft polishing cloth, and processing damage during this surface grinding (about 2 μm) is known. According to this, the polishing amount is reduced to 7 to 8 μm, and the wafer flatness after polishing is 0.8 to 10 in TTV.
It is improved to 1.2 μm.

[0005]

However, the conventional silicon wafer manufacturing method including the surface grinding step has the following problems. That is, in the surface grinding with the # 2000 grinding wheel, the roughness of the grinding mark (grinding mark) was large. Therefore, it was not possible to completely remove the grinding marks during polishing. That is, conventionally, a soft polishing cloth is used, and such a soft polishing cloth results in polishing following the grinding mark, and the grinding mark cannot be completely removed no matter how much the polishing amount is increased.

[0006]

An object of the present invention is to produce a semiconductor wafer having a high flatness, which can reduce the amount of polishing at the time of mirror polishing, and even if the amount of polishing is small, almost no grinding marks are left on the polished surface. It is an object of the present invention to provide a method of manufacturing a semiconductor wafer that can be manufactured.

[0007]

According to a first aspect of the present invention, there is provided a primary etching step of etching a semiconductor wafer after lapping with a primary etching solution, and a surface of the semiconductor wafer after the primary etching step. After the surface-grinding step of grinding with a grinding wheel, the secondary-etching step of etching the surface-ground semiconductor wafer with a secondary etching solution more lightly than in the case of the above-described primary-etching step, and after the secondary-etching step And a mirror polishing step of polishing the surface of the semiconductor wafer with a polishing cloth. In the surface grinding step, the number of rotations of the semiconductor wafer during spark-out is set to 6 or more, while the semiconductor wafer during spark-out. Is a method for manufacturing a semiconductor wafer, in which the rotation speed is 10 rpm or less. The invention according to claim 2 is
In the above-mentioned primary etching step, an etching solution that chemically removes the damage after lapping is used, and in the above-mentioned secondary etching step, the grinding damage after grinding and the roughness of grinding marks are reduced and the unground surface The method of manufacturing a semiconductor wafer according to claim 1, wherein an etching solution that does not affect the above is used.

The semiconductor wafer in this case includes a silicon wafer and a gallium arsenide wafer. The primary etching process may be acid etching or alkali etching, like the secondary etching process. As the etching solution used in the primary etching step and the etching solution used in the secondary etching step, for example, in the case of acid etching, an acidic etching solution such as HF / HNO ₃ mixed acid can be used. On the other hand, in the case of alkali etching, an alkaline etching solution such as KOH or NaOH can be used. 1
The etching solution used in the next etching step and that used in the secondary etching step may be the same etching solution. Alternatively, different etching solutions may be used. The etching amount in the primary etching step is about 5 to 20 μm on one surface of the wafer, and about 10 to 40 μm for both front and back surfaces of the wafer. Lightly etching in the secondary etching step means performing etching in an amount smaller than the etching amount in the primary etching. Etching is 2 to 4 μm for both front and back surfaces. A feature of the secondary etching is that it employs an etching solution having higher selectivity for damage than the primary etching. For example, in the case of acid etching, a reaction-controlled composition is applied. When using an alkaline etching solution, an oxidizing agent such as H ₂ O ₂ (hydrogen peroxide solution) or O ₃ (ozone) may be added to the solution.

In the surface grinding step, the surface grinding may be carried out at a plurality of stages having different grinding accuracy. For example, a combination of relatively rough primary surface grinding and finish surface grinding. Furthermore, between the primary surface grinding and the finish surface grinding, 2
Secondary grinding may be carried out, or surface grinding of tertiary grinding or more may be carried out. It is preferable to perform low-damage surface grinding at least during finishing. Of course, this finishing surface grinding alone may be sufficient. As the grinding wheel for the surface grinding step, for example, a resinoid grinding wheel can be used. However, in the finishing surface grinding step, it is preferable to use a high-count grinding wheel (for example, # 2000 resinoid grinding wheel) that is hard to roughen the wafer surface and can grind even on a non-damaged surface. The rotation speed of the grinding wheel used is 5500-6000 rpm. Grinding amount at the time of surface grinding is about 7-8 μm, damage after processing is about 2 μm
m.

The term "spark out" as used herein means a state in which the surface of the grinding wheel is finished and the feed of the grinding wheel is stopped, but the grinding wheel and the semiconductor wafer are still rotating. The number of rotations of the semiconductor wafer during spark-out (the number of revolutions from the start to the end of spark-out) is 6 to 8 times. If the number of rotations is less than 6, the inconvenience that the ground surface roughness is rough occurs. By the way, the number of rotations in the conventional method is four. Further, the preferable rotation speed of the semiconductor wafer at the time of this spark-out is 5 to 10 rpm.
If it exceeds 10 rpm, the roughness of the ground surface becomes rough. By the way, the rotation speed in the conventional method is 20 rpm.

The type of polishing cloth used in the mirror polishing step is not limited. For example, a hard polishing cloth may be used, or a conventional soft polishing cloth may be used. In the case of a hard polishing cloth, for example, a hard foam urethane foam pad, a pad obtained by impregnating and hardening a high-concentration urethane resin in a non-woven fabric, or the like can be adopted.

[0012]

According to the present invention, the wrapped wafer is subjected to the primary etching using the primary etching solution, and then the surface of the semiconductor wafer is ground to remove the unevenness of the wafer surface in the primary etching to obtain a mirror surface. Reduce the amount of polishing during polishing.
In this surface grinding, the number of rotations of the semiconductor wafer during spark-out is set to 6 times or more and the rotation speed is set to 10 rpm or less. When the rotation speed of the semiconductor wafer is slowed down, the cycle of grinding marks appearing on the wafer surface becomes shorter. The smaller the cycle, the more the copying of the polishing cloth against the grinding marks is suppressed during mirror polishing. That is, the convex portion of the grinding mark is pressed against the polishing cloth more strongly than the concave portion. As a result, the unevenness of the grinding trace is easily lost. The cycle of grinding marks is expressed by the following equation. Grinding mark cycle = 2πr / (grinding stone rotation speed / wafer rotation speed) (1) In the formula (1), r is the radius of the semiconductor wafer. Also,
At the time of this spark-out, the semiconductor wafer is rotated six times or more. This is more than the conventional four times. Therefore, the convex portion of the grinding mark is crushed and the surface roughness is reduced.

Next, the surface-polished semiconductor wafer is divided into 2
Secondary etching is lightly performed with a second etching solution to remove the processing damage due to the surface grinding. At this time, grinding marks are also reduced. After that, the surface of the semiconductor wafer is pressed against a polishing cloth and mirror-polished to remove grinding marks. in this way,
After the primary etching, the grinding conditions at the time of surface grinding are controlled, and then the semiconductor wafer is subjected to a light secondary etching, so that the overall effect of these is to reduce the polishing amount from the conventional dozens of μm to about 5 μm. be able to. This is because even if the amount of polishing is comparatively small, the unevenness of the wafer surface in the primary etching is removed by the surface grinding and the surface of the wafer in which the roughness of the grinding mark is reduced by the secondary etching is mirror-polished. This is because the wafer surface can be mirror-finished. This makes it possible to reduce the amount of polishing, suppress a decrease in wafer flatness, and
It is possible to obtain a semiconductor wafer having high flatness with almost no grinding marks (for example, TTV of 0.5 to 0.8 μm).
m).

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flow sheet showing a method for manufacturing a semiconductor wafer according to an embodiment of the present invention.
FIG. 2 is a perspective view showing a usage state of a surface grinding apparatus used in a method for manufacturing a semiconductor wafer according to an embodiment of the present invention. As shown in FIG. 1, in this embodiment, each step of slicing, chamfering, lapping, primary etching, surface grinding, secondary etching, light back polishing, PCR, donor killer heat treatment, mirror polishing, and final cleaning. After that, a semiconductor wafer is manufactured. Hereinafter, each step will be described in detail. The single crystal silicon ingot pulled up by the CZ (Czochralski) method is sliced (S10).
In 1), it is sliced into a large number of 8-inch wafers having a thickness of about 860 μm. Next, the silicon wafer is chamfered (S102). That is, the outer peripheral portion of the wafer is a # 600 to # 1500 metal chamfering grindstone,
It is chamfered to a predetermined shape. As a result, the outer peripheral portion of the wafer has a predetermined rounded shape (for example, MOS
The chamfered shape of the mold).

Next, the chamfered silicon wafer is lapped in a lapping step (S103). In this lapping process, silicon wafers are placed between lapping plates that are kept parallel to each other, and a lapping liquid that is a mixture of alumina abrasive grains, a dispersant, and water is placed between the lapping plates and the silicon wafer. Pour. And
Rotate and rub under pressure to mechanically wrap the front and back surfaces of the wafer. The lapping amount is about 40 to 80 μm for both front and back surfaces of the wafer. Then, the silicon wafer after lapping is subjected to 1
Next, etching is performed (S104). Here, an alkaline etching solution is used as the primary etching solution. As the alkaline etching solution, NaO having a weight concentration of 45 wt% is used.
H solution is used. Etching is performed at an etching temperature of 90 ° C. and an etching time of 5 to 15 minutes. Due to this primary etching, the front and back sides of the silicon wafer will be 1
About 0 to 40 μm (eg, 27 μm) is etched.

Next, the silicon wafer after the primary etching is subjected to surface grinding for grinding the wafer surface using the surface grinding apparatus shown in FIG. 2 (S105). The surface grinding device 10 mainly includes a lower surface plate 11 and a grinding head 12 arranged above the lower surface plate 11. Silicon wafer W
Is fixed to the upper surface of the lower surface plate 11 by vacuum suction. On the outer periphery of the lower surface of the grinding head 12, an annular grinding wheel 13 is provided.
Is fixed. The grinding wheel 13 is a ring-shaped arrangement and combination of many grinding tips 13a made of resinoid grinding wheels. The grain count of this resinoid grinding wheel is # 4000. 6000 grinding head 12
While rotating at rpm, this is gradually lowered at 0.3 μm / sec to grind the surface of the silicon wafer W on the lower surface plate 11. At this time, the rotation speed of the lower surface plate 11 is 40 r
pm. When the silicon wafer W is ground by 10 μm, the lowering of the grinding head 12 is stopped. However,
The rotation of the grinding head 12 and the rotation of the lower surface plate 11 (silicon wafer W) continue as they are (spark out).
The rotation speed of the silicon wafer W at that time is set to 10 rpm, which is slower than 20 rpm in the conventional method.

As described above, when the rotation speed of the wafer W at the time of spark-out is slowed down, the cycle of the grinding mark a appearing on the wafer surface in FIG. 2 becomes as small as 1.0 mm (see formula (1)). By the way, conventionally, the rotation speed of the silicon wafer W (same 8 inches) at the spark-out is 20r.
At pm, the cycle of grinding marks was 2.0 mm. The smaller the cycle, the more the tracing of the polishing cloth with respect to the grinding mark a is suppressed during mirror polishing. This is because the convex portion of the grinding mark a is more strongly pressed against the polishing cloth than the concave portion and is polished. Further, the number of rotations of the silicon wafer W at the time of spark-out is 6 times, which is more than 4 times in the conventional method. As a result, the effect that the convex portion of the grinding mark is crushed is obtained. The processing damage after surface grinding is 0.5 to 0.8 μm.

Next, the silicon wafer W after surface grinding
Is secondarily lightly etched with a second etching solution (S1
06). Here, as the secondary etching liquid, an alkaline etching liquid of a NaOH solution having the same weight concentration of 45 wt% as the primary etching liquid is used. In this case, the etching temperature is 90 ° C. and the etching time is 40 seconds to 1 minute. Alternatively, when etching with an HF-based etching solution containing a carbonate or an oxidizing agent such as H ₂ O ₂ or O ₃ , the solution temperature is 40 to 80.
C., etching time 30 to 50 minutes. This allows
A secondary etch that is lighter than the primary etch is applied. The etching amount at this time is 1 to 2 μm on one surface of the wafer and 2 to 4 μm (for example, 3 μm) on both front and back surfaces. This secondary etching removes processing damage during surface grinding. Moreover, the grinding marks become smaller. The TTV of the silicon wafer obtained by the secondary etching is 0.8 to 1.0 μm.

Then, the back surface light polish is applied to the silicon wafer W after the secondary etching (S10).
7). The back surface light polishing polishes the back surface of the silicon wafer W lightly, and a gettering layer for removing impurities, heavy metals and the like contained in the wafer is formed in this part. Then, PCR (Polishing) is performed on the outer peripheral portion of the back surface lightly polished silicon wafer W.
Conor Rounding processing is performed, and the chamfered surface of the silicon wafer W is mirror-finished (S10).
8). Here, a known PCR processing device with a polishing cloth is used. That is, the polishing liquid containing no polishing abrasive is
While supplying at 00 ml / min, the polishing cloth is rotated around the axis at 5 rpm by the rotation motor. The chamfered surface of the silicon wafer W rotating at 500 rpm is pressed against the outer peripheral surface of the rotating polishing cloth with a polishing pressure of 1.5 kg / cm ² . In this way, this chamfered surface is mirror-polished.
Then, a donor killer heat treatment is applied to the silicon wafer W that has been subjected to this PCR processing (S109). This donor killer heat treatment prevents the generation of oxygen donors. During the heat treatment using this diffusion furnace, a large number of silicon wafers W are inserted into a quartz heat treatment boat,
Heat in an inert gas at 650 to 700 ° C. for about 15 minutes. At that time, impurities contained in the silicon wafer W are gettered to the back surface of the silicon wafer W.

Next, the surface of the silicon wafer W is mirror-polished using a single-wafer mirror-polishing device (S11).
0). As a mirror polishing device, a polishing platen having a hard polishing cloth spread on the upper surface, and a polishing platen arranged above the polishing platen,
The polishing head has a silicon wafer W adhered to the lower surface by wax. SUBA120 for hard polishing cloth
0 (manufactured by Rodernitta Co., Ltd.) is adopted. During mirror polishing, the polishing platen is rotated at high speed at 40 rpm. On the other hand, the polishing head is rotated at a predetermined rotation speed. While maintaining this state, the polishing liquid is supplied at a predetermined flow rate onto the hard polishing cloth, and the surface of the silicon wafer W is pressed against the hard polishing cloth for polishing. The polishing amount at this time is 4 to 7 μm, which is smaller than the conventional ten and several μm. The TTV of the silicon wafer W after polishing is 0.5 to 0.8 μm. This is smaller than the conventional value of 0.8 to 1.2 μm.

In this way, the surface of the silicon wafer W that has been primarily etched is subjected to surface grinding, and the number of rotations of the wafer W at the time of spark-out is 6 times and the rotation speed is 10 rpm.
Then, since the silicon wafer W after the surface grinding is subjected to the secondary etching lighter than the primary etching, the polishing amount can be reduced, and the reduction of the flatness of the wafer surface can be prevented. Moreover, even if the polishing amount is as small as 4 μm, the grinding marks a are almost absent. This is because the unevenness of the wafer surface generated during the primary etching in the surface grinding step is removed, and the processing damage during the surface grinding is removed in the subsequent secondary etching step, and the roughness of the grinding trace a is reduced. . Therefore, in the polishing step, the grinding mark a is removed even with a relatively small polishing amount, which results in high flatness (TT).
A silicon wafer W having a V of about 0.5 μm) is stably obtained. Further, since the polishing amount is small, the polishing time can be shortened. Then, a cleaning step (S111) is performed. Specifically, RCA cleaning is performed. The total machining allowance from chamfering to mirror polishing in this embodiment is, for example, 117 μm.
m. This indicates that the polishing amount could be reduced by 3 μm as compared with 120 μm when the surface grinding condition in the conventional method and only the primary etching were used (other conditions were the same).

[0022]

According to the present invention, the number of rotations of the wafer is set to 6 times or more and the rotation speed of the wafer is set to 10 rpm or less at the spark-out of the surface grinding step after the primary etching, while the wafer after the surface grinding is performed. Since a lighter secondary etch with a smaller stock removal than the primary etch is applied to
The polishing amount in mirror polishing can be reduced. At the same time, with this small amount of polishing, it is possible to manufacture a semiconductor wafer having high flatness with almost no grinding marks.

[Brief description of drawings]

FIG. 1 is a flow sheet showing a method for manufacturing a semiconductor wafer according to an embodiment of the present invention.

FIG. 2 is a perspective view of a usage state of the surface grinding apparatus used in the method for manufacturing a semiconductor wafer according to the embodiment of the present invention.

[Explanation of symbols]

10 surface grinding equipment, 13 grinding wheel, W Silicon wafer (semiconductor wafer).

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Katsuyoshi Murakami             1-2-1 Shibaura, Minato-ku, Tokyo Sumitomo Mitsubishi             Inside Silicon Co., Ltd. (72) Inventor Akira Adachi             1-2-1 Shibaura, Minato-ku, Tokyo Sumitomo Mitsubishi             Inside Silicon Co., Ltd. (72) Inventor Susumu Okudo             1-2-1 Shibaura, Minato-ku, Tokyo Sumitomo Mitsubishi             Inside Silicon Co., Ltd. (72) Inventor Hideyuki Otani             1-2-1 Shibaura, Minato-ku, Tokyo Sumitomo Mitsubishi             Inside Silicon Co., Ltd. F-term (reference) 3C043 BB00 CC02                 5F043 AA02 AA03 BB02 BB30 DD07                       FF07 GG10

Claims (2)

[Claims] 1. A primary etching step of etching a semiconductor wafer after lapping with a primary etching solution; a surface grinding step of grinding the surface of the semiconductor wafer with a grinding wheel after the primary etching step; The ground semiconductor wafer is subjected to a secondary etching process in which it is lighter than the above-described primary etching process with a secondary etching solution, and after the secondary etching process, the surface of the semiconductor wafer is mirror-polished with a polishing cloth. In the surface grinding step, the number of rotations of the semiconductor wafer during spark-out is set to 6 times or more, while the rotation speed of the semiconductor wafer during spark-out is set to 10 rpm or less. . 2. The first etching step uses an etchant for chemically removing damage after lapping, and the second etching step reduces grinding damage after grinding and roughness of grinding marks, and The method of manufacturing a semiconductor wafer according to claim 1, wherein an etching solution that does not affect the unground surface is used.