CN115446670B - Wafer polishing method - Google Patents
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- CN115446670B CN115446670B CN202210403873.1A CN202210403873A CN115446670B CN 115446670 B CN115446670 B CN 115446670B CN 202210403873 A CN202210403873 A CN 202210403873A CN 115446670 B CN115446670 B CN 115446670B
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- 238000005498 polishing Methods 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 title claims abstract description 45
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 50
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 44
- 230000007306 turnover Effects 0.000 claims abstract description 29
- 238000007517 polishing process Methods 0.000 claims abstract description 16
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 33
- 229910052799 carbon Inorganic materials 0.000 claims description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 235000012431 wafers Nutrition 0.000 description 68
- 239000013078 crystal Substances 0.000 description 14
- 230000000052 comparative effect Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 4
- 238000004943 liquid phase epitaxy Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000002109 crystal growth method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
Abstract
The invention provides a method for grinding a wafer, which comprises the following steps. A silicon carbide wafer is provided having a first surface and an opposite second surface. The silicon carbide wafer is subjected to a polishing process to polish and remove a predetermined amount X from the first surface and the second surface. The polishing process includes performing a number N of turn-over polishing to remove a predetermined amount X, where N is an integer greater than 2 and less than 5, and each turn-over polishing includes polishing a first surface of the silicon carbide wafer, then turning over the silicon carbide wafer and polishing a second surface.
Description
Technical Field
The present invention relates to a polishing method, and more particularly, to a polishing method for a silicon carbide wafer.
Background
The silicon carbide crystal growth method is characterized by physical vapor transport (physical vapor transport; PVT), high temperature chemical vapor deposition (high temperature chemical vapor deposition; HT-CVD), or liquid phase epitaxy (liquid phase epitaxy; LPE), and if the thermal field design, the temperature control during growth, the various gas flows and collocations, and the pressure in the cavity are not well controlled, instability during growth is likely to occur, and a large number of defects may occur, resulting in uneven stress distribution of the crystal.
Conventionally, when performing grinding processing on a crystal/wafer of good quality, the removal amount of the wafer can be arbitrarily set so as to be thinned to a specified thickness, and the wafer geometry can be optimized. However, when a crystal of poor quality is encountered, the crystal has residual internal stress, and therefore, when the crystal/wafer is directly polished on both sides, the wafer geometry is not optimized, and the geometry is easily degraded, resulting in a large degree of wafer bending.
Accordingly, how to reduce the geometrical degradation and wafer warpage during the polishing process of the crystal/wafer is a problem to be solved.
Disclosure of Invention
The invention provides a method for polishing a wafer, which can reduce the problems of geometric degradation, wafer bending and the like of the wafer during polishing processing.
Some embodiments of the present invention provide a method for polishing a wafer, comprising the following steps. A silicon carbide wafer is provided having a first surface and a second surface opposite the first surface. The silicon carbide wafer is subjected to a polishing process to polish and remove a predetermined amount X from the first surface and the second surface. The grinding process comprises the following steps: the turn-up grinding is performed N times to remove a predetermined amount X, where N is an integer greater than 2 and less than 5. Each turn-over grinding includes grinding a first surface of a silicon carbide wafer, then turning over the silicon carbide wafer and grinding the second surface.
In some embodiments, the first surface is a silicon surface and the second surface is a carbon surface, and in the predetermined amount X, the total removal of the silicon surface is different from the total removal of the carbon surface.
In some embodiments, the total removal of the silicon face is greater than the total removal of the carbon face.
In some embodiments, the amount of removal of the first surface and the second surface is less than X/N added when the last of the N number of turn-ups is performed.
In some embodiments, the first one of the N number of turn-up grinds is greater than X/N after the first and second surface removal amounts are added.
In some embodiments, the first one of the N number of turn-up grinds is less than 40% x after the first and second surface removal amounts are added.
In some embodiments, the N-1 th of the N number of turn-over grinds is less than 40% x after the first surface and the second surface are removed.
In some embodiments, performing the N number of turn-ups includes at least: performing a first turn-up polish to remove a specified amount A from the first surface polish 1 Removing a specific amount B from the second surface finish 1 The method comprises the steps of carrying out a first treatment on the surface of the Performing the N-1 th turn-up polish to remove a specified amount A from the first surface polish (N-1) Removing a specific amount B from the second surface finish (N-1) The method comprises the steps of carrying out a first treatment on the surface of the And performing the last turn-up polish of the nth time to remove a specified amount a from the first surface polish N Removing a specific amount B from the second surface finish N Wherein, a specific amount A N Greater than a specific amount A (N-1) Specific amount A 1 And a specific amount B N Less than a specific amount B (N-1) Specific amount B 1 。
In some embodiments, the specific amount A N With the specific amount B N Is less than the specified amount A 1 With the specific amount B 1 And less than the specified amount A (N-1) With the specific amount B (N-1) Is a sum of (3).
In some embodiments, the specific amount A 1 Equal to the specific amount A (N-1) And the specific amount B 1 Equal to a specific amount B (N-1) 。
In some embodiments, the N number of turn-ups is 3 number of turn-ups.
In some embodiments, the N number of turn-ups is 4 number of turn-ups.
Based on the above, by the wafer polishing method of the embodiment of the present invention, even if a crystal having internal stress residues is encountered, the geometry of the wafer can be optimized and the flatness of the wafer can be maintained.
Drawings
FIG. 1 is a flow chart of a wafer polishing method according to an embodiment of the invention;
fig. 2A to 2D are three-dimensional schematic diagrams illustrating stages of a wafer polishing method according to an embodiment of the invention.
Description of the reference numerals
102A first surface
102B second surface
104 grinding wheel
S10, S20, S202A, S202B step
WF silicon carbide wafer
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1 is a flow chart of a wafer polishing method according to an embodiment of the invention. Fig. 2A to 2D are three-dimensional schematic diagrams illustrating stages of a wafer polishing method according to an embodiment of the invention. The wafer polishing method according to some embodiments of the present invention will be described below with reference to the flowchart of fig. 1 in conjunction with the three-dimensional schematic diagrams of fig. 2A to 2D.
Referring to step S10 of fig. 1 and fig. 2A, a silicon carbide wafer WF is provided. The silicon carbide wafer WF includes a first surface 102A and a second surface 102B opposite to the first surface 102A. For example, the first surface 102A is a carbon face and the second surface 102B is a silicon face. In some embodiments, the silicon carbide wafer WF may be a silicon carbide ingot formed by a physical vapor transport method, a high temperature chemical vapor deposition method, a liquid phase epitaxy method, or the like, and is formed by dicing the silicon carbide ingot. For example, the ingots of silicon carbide include 3C-silicon carbide, 4H-silicon carbide, 6H-silicon carbide, and the like. 3C-silicon carbide belongs to the cubic system, while 4H-silicon carbide and 6H-silicon carbide belong to the hexagonal system. In some examples, the silicon carbide wafer WF may be a crystal having internal stress residue or a crystal having no internal stress residue, to which the present invention is not limited. That is, crystals having internal stress residues or having little to no internal stress residues may be suitable for use in the wafer polishing method of the present invention.
Then, referring to step S20 of fig. 1 and fig. 2B and 2C, a polishing process is performed on the silicon carbide wafer WF to polish and remove the predetermined amount X from the first surface 102A and the second surface 102B of the silicon carbide wafer WF. The predetermined amount X is the total amount expected to be removed from the first surface 102A and the second surface 102B after the polishing process. For example, when the predetermined amount X is 20 μm, then a total amount of 20 μm is expected to be abraded from the first surface 102A and the second surface 102B of the silicon carbide wafer WF. Although 20 μm is used as the predetermined amount X here, it should be understood that the predetermined amount X may be adjusted according to the process requirements. The silicon carbide wafers WF prepared for different methods may also have different or the same predetermined amount X as the total amount of the polishing removal.
Referring to step S202 of fig. 1, in some embodiments, the grinding process (i.e., step S20) actually includes performing a turn-over grinding N times to remove the predetermined amount X, where N is an integer greater than 2 and less than 5. In some embodiments, N number of turn-ups is 3 or 4. Each turn-up grinding includes grinding the first surface 102A of the silicon carbide wafer WF, then turning up the silicon carbide wafer WF and grinding the second surface 102B.
More specifically, as shown in step S202A of fig. 1 and fig. 2B, the first surface 102A (carbon surface) of the silicon carbide wafer WF is polished to remove a specific amount a from the first surface 102A 1 . Next, as shown in step S202B of fig. 1 and fig. 2C, the silicon carbide wafer WF is turned over and the second surface 102B (silicon surface) is polished to remove a specific amount B from the second surface 102B 1 . In fig. 2B and 2C, the first surface 102A and the second surface 102B of the silicon carbide wafer WF are polished by using the polishing wheel 104.
In some embodiments, performing the N number of turn-ups includes repeatedly performing step S202A and step S202B of fig. 1. That is, as shown in fig. 2D, the first surface 102A (carbon surface) of the silicon carbide wafer WF is polished again, then the silicon carbide wafer WF is turned over and the second surface 102B (silicon surface) is polished, and the above-described polishing steps are repeatedly performed to remove the predetermined amount X.
In the illustrated embodiment, each turn-up polishing is performed by polishing the first surface 102A (carbon surface) and then polishing the second surface 102B (silicon surface), but the present invention is not limited thereto. In other embodiments, each turn-up polishing may be performed by polishing the second surface 102B (silicon surface) and then polishing the first surface 102A (carbon surface).
In an embodiment of the present invention, a first turn-up polish is performed to remove a specified amount A from the first surface 102A polish 1 And abrades and removes a specific amount B from the second surface 102B 1 At least the (i.e. the second last) N-1 turn-over polishing and the last N-th turn-over polishing are then performed. For example, the N-1 turn-up polish is performed by removing a specified amount A from the first surface 102A polish (N-1) Abrasive removal of a specified amount B from the second surface 102B (N-1) . Then, during the last turn-up polish of the nth time, a specific amount a is removed from the first surface 102A polish N Abrasive removal of a specified amount B from the second surface 102B N 。
In the above embodiment, the specific amount A N Less than the specified amount A (N-1) Said specific amount A 1 And the specific amount B N Greater than the specified amount B (N-1) Said specific amount B 1 . In other words, the last carbon surface (first surface 102A) is polished by a specified amount A removed N Is a specific amount A removed than the first or second last carbon face grinding 1 With a specific amount A (N-1) But also to a lesser extent. In addition, the last polishing of the silicon surface (second surface 102B) removes a specific amount BN that is greater than the first or second last polishing of the silicon surface 1 And a specific amount B (N-1) But much more so.
In some embodiments, a specific amount A N And a specific amount B N The sum of (a) is less than a certain amount A 1 With the specific amount B 1 And less than a certain amount A (N-1) And a specific amount B (N-1) Is a sum of (3). That is, the last turn-up grinding to remove the total amount from the carbon and silicon faces (i.e., A N +B N ) Will be less than the first turn-over polish and the penultimate polishThe total amount removed from the carbon and silicon faces during the next turn-up grinding. Further, in some embodiments, a specific amount A 1 Is equal to a specific amount A (N-1) And a specific amount B 1 Is equal to a specific amount B (N-1) 。
In some embodiments, in the predetermined amount X, the total removal of the second surface 102B (silicon side) is different from the total removal of the first surface 102A (carbon side). For example, the total removal of the second surface 102B (silicon side) is higher than the total removal of the first surface 102A (carbon side). More specifically, since the stress distribution of the carbon surface opposite to the silicon surface is more uneven during the growth of the crystal and the hardness of the carbon surface is high, the carbon surface cannot be removed uniformly during the surface mechanical processing. Accordingly, the problem of uneven stress caused by the carbon surface can be reduced by reducing the total removal amount of the carbon surface. In other words, in the polishing process of the silicon carbide wafer WF, when the removal amounts of the silicon face and the carbon face meet the above conditions, the geometry of the wafer (such as thickness variation (TTV), local Thickness Variation (LTV), bow (bow), bow (warp), site front reference minimum square/range (SFQR), etc.) can be further optimized, and the flatness of the wafer can be maintained.
In some embodiments, the removal amounts of the first surface 102A and the second surface 102B are added (a particular amount a N +specific amount B N ) And will then be less than X/N. For example, if the predetermined amount X is set to 100% and N is 3 times of turn-over polishing, the sum of the removal amounts of both surfaces at the time of the last turn-over polishing is less than 33.33% (i.e., 100%/3 times). In addition, in some embodiments, the first of the N number of turn-ups may be greater than X/N after the first and second surfaces 102A, 102B are removed. For example, if the predetermined amount X is set to 100% and N is 3 times of turn-over polishing, the amount of removal of both surfaces at the time of the first turn-over polishing is greater than 33.33% (i.e., 100%/3 times) after the addition.
In some embodiments, the first one of the N number of turn-ups is performed after the removal rates of the first surface 102A and the second surface 102B are added (i.e., a 1 +B 1 ) Will be less than 40% x. In addition, in the N-1 th turn-over polishing of the N-th turn-over polishing, the removal amounts of the first surface 102A and the second surface 102B are added (i.e., a (N-1) +B (N-1) ) Will be less than 40% x.
In some other embodiments, in addition to performing N number of turn-up grinds, an additional grind of the second surface 102B (silicon side) may be included to achieve the predetermined amount X. For example, when N is 3, the predetermined amount X is achieved by performing 3 turn-up grinding (i.e., grinding of the carbon/silicon surface) and then performing the last grinding of the silicon surface.
Based on the above conditions, by controlling and reducing the removal amount in each turn-up polishing and increasing the number of times of polishing, it is possible to reduce the variation to which the wafer is subjected during processing and to make the surface stress of the silicon carbide wafer WF more uniform.
In order to demonstrate that the wafer polishing method of the present invention can optimize the geometry of the wafer and maintain the flatness of the wafer, the following experimental examples will be described:
experimental example
In the experimental example described below, the wafer having internal stress remaining therein was subjected to polishing processing, wherein each polishing includes polishing both sides of the silicon carbide wafer as shown in fig. 2D described above. In experimental examples, the grinding effect of each process is determined by measuring pits (points) on the surface of the ground wafer and the geometric shapes (such as thickness variation (TTV), local Thickness Variation (LTV), bow (bow), curvature (warp), position front reference minimum square/range (SFQR), and the like) of the pits by an optical instrument. Polishing performance is judged to be "good" when the values of pits and geometry on the surface of the wafer are within a desired range, such as bow (bow) of less than 300 μm or bow (warp) of less than 500 μm. If the values of pits and geometric shapes on the surface of the wafer are too high, the polishing effect is judged to be poor. The results of the processes and polishing results for each of the experimental examples and comparative examples are presented in tables 1 to 8 below.
TABLE 1 Experimental example A
TABLE 2 Experimental example B
TABLE 3 Experimental example C
TABLE 4 Experimental example D
TABLE 5 Experimental example E
TABLE 6 comparative example F
TABLE 7 comparative example G
TABLE 8 comparative example H
From the above examples a to E, when the number of times of the flip-chip polishing is controlled to be 3 or 4 and the total amount of silicon surface removal is controlled to be higher than the total amount of carbon surface removal, the geometry of the wafer can be optimized and the flatness of the wafer can be maintained. In addition, as shown in examples a to E, the removal amount of the silicon surface is higher than that of the carbon surface during the last turn-over polishing to achieve the effect of optimizing the wafer geometry.
In contrast, with reference to comparative example F, although the turn-over polishing was performed three times, the polishing process of comparative example F had poor results because the total amount of silicon surface removed was lower than the total amount of carbon surface removed, and the amount of carbon surface removed was higher at the time of the last turn-over polishing. Referring to comparative example G, if the number of times of the turn-over polishing is 5 and each turn-over polishing is uniformly removing the same specific amount from the carbon face and the silicon face, the polishing process is similarly not good. In addition, with reference to comparative example H, if the number of times of turn-over polishing is 2, since the number of times of polishing is not appropriately increased to reduce the variation to which wafer processing is subjected, the polishing process of comparative example H is similarly poor in performance.
In addition, as shown in the experimental results, the removal amount of the silicon surface needs to be controlled within the range of 10% -25% and the removal amount of the carbon surface needs to be controlled within the range of 0% -15% when the final turn-over grinding is performed, and the technical effects of further optimizing the wafer geometry and maintaining the flatness of the wafer can be achieved when the removal amount of the silicon surface is higher than the removal amount of the carbon surface.
In summary, by the wafer polishing method according to the embodiment of the present invention, the geometry of the wafer can be optimized and the flatness of the wafer can be maintained even when the wafer is subjected to the crystals having the internal stress residues. Therefore, the crystal which is judged to have internal stress after the inspection in the past can be saved or discarded without being detained, and part of the wafer with internal stress residue can be saved by the method for grinding the wafer in the embodiment of the invention, so that the waste of crystal materials is avoided.
Claims (12)
1. A method for polishing a wafer, comprising:
providing a silicon carbide wafer having a first surface and a second surface opposite the first surface; and
performing a polishing process on the silicon carbide wafer to polish and remove a predetermined amount X from the first surface and the second surface, wherein the polishing process comprises:
performing N number of turn-over polishes to remove the predetermined amount X, wherein N is an integer greater than 2 and less than 5, and each of the turn-over polishes includes polishing the first surface of the silicon carbide wafer, then turning over the silicon carbide wafer and polishing the second surface, the performing N number of turn-over polishes including at least:
performing the first turn-up polish to remove a specified amount A from the first surface polish 1 Removing a specific amount B from the second surface finish 1 ；
Performing the turn-up polish N-1 to remove a specified amount a from the first surface polish (N-1) Removing a specific amount B from the second surface finish (N-1) The method comprises the steps of carrying out a first treatment on the surface of the And
performing the last turn-up polish of the nth time to remove a specified amount a from the first surface polish N And abrading to remove a specified amount B from the second surface N Wherein the specific amount A N Less than the specified amount A (N-1) Said specific amount A 1 And the specific amount B N Greater than the specified amount B (N-1) Said specific amount B 1 The method comprises the steps of carrying out a first treatment on the surface of the And
the first surface is a carbon surface and the second surface is a silicon surface, and in the predetermined amount X, a total removal amount of the silicon surface is different from a total removal amount of the carbon surface.
2. The method of claim 1, wherein the total removal of the silicon face is greater than the total removal of the carbon face.
3. The method of claim 1, wherein the amount of removal of the first surface and the second surface added to the last of the N number of turn-ups is less than X/N.
4. The method of claim 1, wherein the first one of the N number of turn-ups is performed with a removal amount of the first surface and the second surface added to be greater than X/N.
5. The method of claim 1, wherein the first one of the N number of turn-ups is performed with less than 40% x added to the removal of the first surface and the second surface.
6. The method of claim 1, wherein the N-1 th of the N-th turn-over polishes is performed with less than 40% x added to the removal of the first surface and the second surface.
7. The method according to claim 1, characterized in that the specific amount a N With the specific amount B N Is less than the specified amount A 1 With the specific amount B 1 And less than the specified amount A (N-1) With the specific amount B (N-1) Is a sum of (3).
8. The method according to claim 1, characterized in that the specific amount a 1 Equal to the specific amount A (N-1) And the specific amount B 1 Equal to the specific amount B (N-1) 。
9. The method of claim 1, wherein the N number of turn-ups is 3 number of turn-ups.
10. The method of claim 1, wherein the N number of turn-ups is 4 number of turn-ups.
11. A method for polishing a wafer, comprising:
providing a silicon carbide wafer having a first surface and a second surface opposite the first surface; and
performing a polishing process on the silicon carbide wafer to polish and remove a predetermined amount X from the first surface and the second surface, wherein the polishing process comprises:
performing N number of turn-over polishes to remove the predetermined amount X, wherein N is an integer greater than 2 and less than 5, and each of the turn-over polishes includes polishing the first surface of the silicon carbide wafer, then turning over the silicon carbide wafer and polishing the second surface, the performing N number of turn-over polishes including at least:
performing the first turn-up polish to remove a specified amount A from the first surface polish 1 Removing a specific amount B from the second surface finish 1 ；
Performing the turn-up polish N-1 to remove a specified amount a from the first surface polish (N-1) Removing a specific amount B from the second surface finish (N-1) The method comprises the steps of carrying out a first treatment on the surface of the And
performing the last turn-up polish of the nth time to remove a specified amount a from the first surface polish N And abrading to remove a specified amount B from the second surface N Wherein the specific amount A N Less than the specified amount A (N-1) Said specific amount A 1 And the specific amount B N Greater than the specified amount B (N-1) Said specific amount B 1 The method comprises the steps of carrying out a first treatment on the surface of the And
the first surface is a carbon surface and the second surface is a silicon surface, and in the predetermined amount X, the total removal amount of the silicon surface is higher than the total removal amount of the carbon surface.
12. A method for polishing a wafer, comprising:
providing a silicon carbide wafer having a first surface and a second surface opposite the first surface; and
performing a polishing process on the silicon carbide wafer to polish and remove a predetermined amount X from the first surface and the second surface, wherein the polishing process comprises:
performing a turn-up polish N times to remove the predetermined amount X, wherein N is an integer greater than 2 and less than 5, and each of the turn-up polishes includes polishing the first surface of the silicon carbide wafer, then turning over the silicon carbide wafer and polishing the second surface; and
the performing of the N times of turn-over grinding at least includes:
performing the first turn-up polish to remove a specified amount A from the first surface polish 1 Removing a specific amount B from the second surface finish 1 ；
Performing the turn-up polish N-1 to remove a specified amount a from the first surface polish (N-1) Removing a specific amount B from the second surface finish (N-1) The method comprises the steps of carrying out a first treatment on the surface of the And
performing the last turn-up polish of the nth time to remove a specified amount a from the first surface polish N And abrading to remove a specified amount B from the second surface N Wherein the specific amount A N Less than the specified amount A (N-1) Said specific amount A 1 And the specific amount B N Greater than the specified amount B (N-1) Said specific amount B 1 。
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| CN115446670A (en) | 2022-12-09 |
| TW202249099A (en) | 2022-12-16 |
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