CN115446670A - Method for grinding wafer - Google Patents
Method for grinding wafer Download PDFInfo
- Publication number
- CN115446670A CN115446670A CN202210403873.1A CN202210403873A CN115446670A CN 115446670 A CN115446670 A CN 115446670A CN 202210403873 A CN202210403873 A CN 202210403873A CN 115446670 A CN115446670 A CN 115446670A
- Authority
- CN
- China
- Prior art keywords
- specific amount
- amount
- wafer
- grinding
- removal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000227 grinding Methods 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims abstract description 49
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 42
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 36
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 31
- 229910052799 carbon Inorganic materials 0.000 claims description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 28
- 239000010703 silicon Substances 0.000 claims description 28
- 238000007517 polishing process Methods 0.000 claims description 8
- 235000012431 wafers Nutrition 0.000 description 68
- 238000005498 polishing Methods 0.000 description 31
- 239000013078 crystal Substances 0.000 description 14
- 230000007306 turnover Effects 0.000 description 13
- 230000000052 comparative effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 3
- 238000004943 liquid phase epitaxy Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
Abstract
The invention provides a method for grinding a wafer, which comprises the following steps. A silicon carbide wafer is provided having a first surface and an opposing second surface. A grinding process is performed on the silicon carbide wafer to abrasively remove a predetermined amount X from the first surface and the second surface. The lapping process includes performing N times of lapping to remove a predetermined amount X, where N is an integer greater than 2 and less than 5, and each lapping includes lapping a first surface of a silicon carbide wafer, then lapping the silicon carbide wafer and lapping a second surface.
Description
Technical Field
The invention relates to a grinding method, in particular to a grinding method of a silicon carbide wafer.
Background
Whether the growth method of silicon carbide crystal is Physical Vapor Transport (PVT), high temperature chemical vapor deposition (HT-CVD), or Liquid Phase Epitaxy (LPE), the thermal field design, temperature control during growth, various gas flows and arrangements, and the pressure in the chamber are not well controlled, the growth method is prone to instability during growth, and a large number of defects and crystals with non-uniform stress distribution may be generated.
Conventionally, when a grinding process is performed on a good quality crystal/wafer, the amount of removal of the wafer can be arbitrarily set to be thinned to a prescribed thickness, and the wafer geometry can be optimized. However, when a crystal with poor quality is encountered, because the crystal has residual internal stress, when the crystal/wafer is directly subjected to the grinding processing of the front and back surfaces, not only the geometry of the wafer is not optimized, but also the geometry is easily deteriorated, and the wafer is greatly bent.
Accordingly, how to reduce the geometric deterioration and the wafer warpage when polishing the crystal/wafer is a problem to be solved.
Disclosure of Invention
The invention provides a method for polishing a wafer, which can reduce the problems of geometric deterioration, wafer bending and the like during the polishing process of the wafer.
Some embodiments of the present invention provide a method for grinding a wafer, including the following steps. A silicon carbide wafer is provided having a first surface and a second surface opposite the first surface. A grinding process is performed on the silicon carbide wafer to abrasively remove a predetermined amount X from the first surface and the second surface. The grinding process comprises the following steps: and performing N times of turn-over grinding to remove the preset amount X, wherein N is an integer which is more than 2 and less than 5. Each of the double side grinds includes grinding a first surface of the silicon carbide wafer, and then reversing the silicon carbide wafer and grinding the second surface.
In some embodiments, the first surface is a silicon face and the second surface is a carbon face, and the total amount of removal of the silicon face is different from the total amount of removal of the carbon face in the predetermined amount X.
In some embodiments, the total removal of the silicon side is higher than the total removal of the carbon side.
In some embodiments, the last of the N double side grinds is performed with a removal amount of the first surface plus the removal amount of the second surface that is less than X/N.
In some embodiments, the first of the N double side grinds and the second of the N double side grinds are added to remove an amount greater than X/N.
In some embodiments, the first of the N double side grindings is performed with less than 40% by weight of the amount of removal of the first surface plus the amount of removal of the second surface added.
In some embodiments, the removal of the first surface plus the removal of the second surface when performing the N-1 th of the N double face grindings is less than 40% by volume.
In some embodiments, performing the N number of turn-ups comprises at least: performing a first lapping operation to remove a specific amount A from the first surface 1 And abrasively removing a specific amount B from the second surface 1 (ii) a Performing N-1 times of turn-over grinding to remove a specific amount A from the first surface grinding (N-1) And abrasively removing a specific amount B from the second surface (N-1) (ii) a And performing an Nth final lapping to remove a specified amount A from the first surface N And abrasively removing a specific amount B from the second surface N Wherein, a specific amount A N Greater than a specific amount A (N-1) And a specific amount A 1 And a specific amount B N Less than a specific amount B (N-1) And a specific amount B 1 。
In some embodiments, the particular amount A N With the specified amount B N Is less than the specific amount A 1 With the specific amount B 1 And less than the specific amount A (N-1) With the specified amount B (N-1) The sum of (a) and (b).
In some embodiments, the particular amount a 1 Is equal to the specific amount A (N-1) And the specific amount B 1 Is equal to a specific quantity B (N-1) 。
In some embodiments, the N double face grindings are 3 double face grindings.
In some embodiments, the N double face grindings are 4 double face grindings.
Based on the above, by the method for grinding a wafer according to the embodiment of the present invention, even if a crystal having residual internal stress is encountered, the geometry of the wafer can be optimized and the flatness of the wafer can be maintained.
Drawings
FIG. 1 is a flow chart of a wafer polishing method according to an embodiment of the present invention;
fig. 2A to 2D are three-dimensional schematic diagrams illustrating stages of a wafer polishing method according to an embodiment of the invention.
Description of the reference numerals
102A first surface
102B second surface
104 grinding wheel
S10, S20, S202A, S202B
WF silicon carbide wafer
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
FIG. 1 is a flow chart of a wafer polishing method according to an embodiment of the invention. Fig. 2A to 2D are three-dimensional schematic diagrams illustrating stages of a wafer polishing method according to an embodiment of the invention. Hereinafter, a wafer polishing method according to some embodiments of the present invention will be described with reference to the flowchart of fig. 1 and the three-dimensional schematic diagrams of fig. 2A to 2D.
Referring to step S10 of fig. 1 and fig. 2A, a silicon carbide wafer WF is provided. The silicon carbide wafer WF includes a first surface 102A and a second surface 102B opposite the first surface 102A. For example, the first surface 102A is a carbon plane and the second surface 102B is a silicon plane. In some embodiments, the silicon carbide wafer WF may be a silicon carbide ingot formed by a physical vapor transport method, a high temperature chemical vapor deposition method, a liquid phase epitaxy method, or the like, and formed by cutting the silicon carbide ingot. For example, ingots of silicon carbide include 3C-silicon carbide, 4H-silicon carbide, 6H-silicon carbide, and the like. 3C-silicon carbide belongs to the cubic system, while 4H-silicon carbide and 6H-silicon carbide belong to the hexagonal system. In some examples, the silicon carbide wafer WF may be a crystal with or without residual internal stress, to which the present invention is not limited. That is, crystals having residual internal stress or having little to no residual internal stress can be applied to the wafer polishing method of the present invention.
Then, referring to step S20 of fig. 1 and fig. 2B and 2C, the silicon carbide wafer WF is subjected to a grinding process to grind and remove a predetermined amount X from the first surface 102A and the second surface 102B of the silicon carbide wafer WF. The predetermined amount X is the total amount of removal desired from the first surface 102A and the second surface 102B after the polishing process. For example, when the predetermined amount X is 20 μm, a total amount of 20 μm is expected to be abrasively removed from the first surface 102A and the second surface 102B of the silicon carbide wafer WF. Although 20 μm is used as the predetermined amount X, it should be understood that the predetermined amount X can be adjusted according to the process requirements. The silicon carbide wafers WF prepared for different processes may also have different or the same predetermined amount X as the total amount of abrasive removal.
Referring to step S202 of fig. 1, in some embodiments, the grinding process (i.e., step S20) actually includes performing N times of flip grinding to remove the predetermined amount X, where N is an integer greater than 2 and less than 5. In some embodiments, the N number of double-side grindings is 3 double-side grindings, or 4 double-side grindings. Each of the turn-over grindings includes grinding the first surface 102A of the silicon carbide wafer WF, and then turning over the silicon carbide wafer WF and grinding the second surface 102B.
More specifically, as shown in step S202A of fig. 1 and fig. 2B, the first surface 102A (carbon surface) of the silicon carbide wafer WF is ground to remove a specific amount a from the first surface 102A 1 . Next, as shown in step S202B of FIG. 1 and FIG. 2C, the silicon carbide wafer WF is turned over and the second surface 102B (silicon face) is polished to remove a specific amount B from the second surface 102B 1 . In FIGS. 2B and 2C, the silicon carbide is polished using the polishing wheel 104The first surface 102A and the second surface 102B of the wafer WF are polished.
In some embodiments, performing the N-times lapping includes repeatedly performing step S202A and step S202B of fig. 1. That is, as shown in fig. 2D, the first surface 102A (carbon face) of the silicon carbide wafer WF is ground again, then, the silicon carbide wafer WF is turned over and the second surface 102B (silicon face) is ground, and the above-described grinding step is repeatedly performed to achieve removal of the predetermined amount X.
In the illustrated embodiment, each of the turn-over polishes is performed by first polishing the first surface 102A (carbon side) and then polishing the second surface 102B (silicon side), but the invention is not limited thereto. In other embodiments, each of the flip-chip grinding processes may be performed after the second surface 102B (silicon surface) is ground, and then the first surface 102A (carbon surface) is ground.
In an embodiment of the present invention, a first lapping is performed to remove a specific amount A from the first surface 102A 1 And abrasively removing a specific amount B from the second surface 102B 1 And then at least performing the N-1 (namely, the penultimate) turn-over grinding and performing the last turn-over grinding of the Nth turn-over grinding. For example, the N-1 st lapping is performed to remove a specific amount A from the first surface 102A (N-1) And abrasively removing a specific amount B from the second surface 102B (N-1) . Then, a certain amount A is removed from the first surface 102A during the N-th final turn-over grinding N And abrasively removing a specific amount B from the second surface 102B N 。
In the above examples, the specific amount A N Less than the specific amount A (N-1) And the specific amount A 1 And the specific amount B N Greater than the specific amount B (N-1) And the specific amount B 1 . In other words, the last grinding of the carbon face (first surface 102A) removed a certain amount A N Is removed a specific amount A that is greater than the first or penultimate carbon face grind 1 With a specific amount A (N-1) But also needs to be less. In addition, the last oneThe specific amount BN removed by the second silicon face (second surface 102B) grinding is greater than the specific amount B removed by the first or last silicon face grinding 1 With a specific amount B (N-1) Much more so.
In some embodiments, the particular amount A N With a specific amount B N Is less than the specific amount A 1 With the specified amount B 1 And less than a specific amount A (N-1) With a specific amount B (N-1) The sum of (a) and (b). That is, the last lapping is performed to remove the total amount of the carbon side and the silicon side (i.e., A) N +B N ) Less than the total amount removed from the carbon and silicon surfaces during the first and penultimate lapping. Further, in some embodiments, a specific amount A 1 Is equal to the specific amount A (N-1) And a specific amount B 1 Is equal to a specific quantity B (N-1) 。
In some embodiments, the total amount removed of the second surface 102B (silicon side) is different from the total amount removed of the first surface 102A (carbon side) in the predetermined amount X. For example, the total removal of the second surface 102B (silicon side) is higher than the total removal of the first surface 102A (carbon side). More specifically, since the stress distribution of the carbon surface is more uneven as opposed to the silicon surface during crystal growth and the hardness of the carbon surface is higher, it is not possible to uniformly remove the carbon surface during surface machining. Accordingly, the problem of stress unevenness caused by the carbon surface can be reduced by reducing the total amount of the carbon surface removed. In other words, in the polishing process of the silicon carbide wafer WF, when the removal amounts of the silicon surface and the carbon surface are satisfied as described above, the geometry of the wafer (e.g., thickness variation (TTV); local Thickness Variation (LTV); bow (bow); bow (warp); site front surface reference minimum square/range (SFQR); etc.) can be further optimized, and the flatness of the wafer can be maintained.
In some embodiments, the removal amounts of the first surface 102A and the second surface 102B are added (by a certain amount a) when the last of the N double-side grindings is performed N + specific amount B N ) Then it will be less than X/N. For example, if the predetermined amount X is set to 100% and N is 3 times of face-over grinding, the last timeThe amount of both sides removed during the double side grinding process is less than 33.33% (i.e., 100%/3 times). In addition, in some embodiments, the removal amount of the first surface 102A and the removal amount of the second surface 102B are greater than X/N when the first flip-grinding of the N times of flip-grindings is performed. For example, if the predetermined amount X is set to 100% and N is 3 times of turn-over polishing, the sum of the removal amounts of both sides in the first turn-over polishing is greater than 33.33% (i.e., 100%/3 times).
In some embodiments, the first surface 102A and the second surface 102B are removed in a sum (i.e., a) when the first of N double-side grinds is performed 1 +B 1 ) Will be less than 40% by weight. In addition, when N-1 times of flip-chip grinding is performed, the removal amounts of the first surface 102A and the second surface 102B are added (i.e. A) (N-1) +B (N-1) ) Will be less than 40% by weight.
In some other embodiments, in addition to performing N times of the face-over grinding, an additional grinding of the second surface 102B (silicon side) may be included to reach the predetermined amount X. For example, when N is 3, 3 times of flip-chip polishing (i.e., polishing of the carbon/silicon surface) is performed first, and then the silicon surface is polished for the last time to reach the predetermined amount X.
Based on the above conditions, by controlling and reducing the removal amount per one turn-over grinding and increasing the number of times of grinding, it is possible to reduce the deformation received at the time of wafer processing and make the surface stress of the silicon carbide wafer WF more uniform.
In order to demonstrate that the wafer polishing method of the present invention can optimize the geometry of the wafer and maintain the flatness of the wafer, the following experimental examples will be described:
examples of the experiments
In the following experimental examples, wafers having residual internal stress were subjected to polishing processing, wherein each polishing includes polishing both surfaces of a silicon carbide wafer as shown in fig. 2D. In the experimental examples, the polishing results of the respective processes were judged by measuring pits (pits) on the surface of the polished wafer and the geometric shapes (for example, thickness variation (TTV), local Thickness Variation (LTV), bow (bow), bow (warp), site front surface standard minimum square/range (SFQR), etc.) thereof by an optical instrument. When the value of the pits and the geometrical features on the surface of the wafer is in a desired range, such as bow (bow) of less than 300 μm or bow (warp) of less than 500 μm, the polishing efficiency is judged to be "good". If the values of the pits and the geometric features on the surface of the wafer are too high, the polishing result is judged to be "poor". The process and polishing results of the experimental examples and comparative examples are shown in tables 1 to 8 below.
TABLE 1 Experimental example A
TABLE 2 Experimental example B
TABLE 3 Experimental example C
TABLE 4 Experimental example D
TABLE 5 Experimental example E
TABLE 6 comparative example F
TABLE 7 comparative example G
TABLE 8 comparative example H
In the above-mentioned experimental examples a to E, when the number of times of the flip-chip polishing is controlled to be 3 or 4 times and the total amount of the silicon surface removed is controlled to be higher than that of the carbon surface removed, the geometry of the wafer can be optimized and the flatness of the wafer can be maintained. In addition, as shown in experiments a to E, the amount of silicon removed is higher than the amount of carbon removed during the last flip-chip grinding process to optimize the wafer geometry.
In contrast, in the comparative example F, although the flip-over polishing was performed three times, the polishing process of the comparative example F was not successful because the total amount of silicon surface removed was lower than the total amount of carbon surface removed and the amount of carbon surface removed was higher during the last flip-over polishing. Referring to comparative example G, if the number of the turn-over polishing was 5 times and each turn-over polishing was only uniformly removing the same specific amount from the carbon side and the silicon side, the polishing process was also not good. In addition, referring to comparative example H, if the number of times of the face-over polishing is 2, since the number of times of the polishing process is not increased appropriately to reduce the deformation received during the wafer processing, the polishing process of comparative example H is also not good.
In addition, from the above experimental results, when the last flip-chip grinding is performed, the silicon surface removal amount needs to be controlled within a range of 10% to 25%, and the carbon surface removal amount needs to be controlled within a range of 0% to 15%, and when the silicon surface removal amount is higher than the carbon surface removal amount, the technical effects of further optimizing the wafer geometry and maintaining the wafer flatness can be achieved.
In summary, according to the method for polishing a wafer of the embodiments of the present invention, even if the wafer is subjected to a crystal with residual internal stress, the geometry of the wafer can be optimized and the flatness of the wafer can be maintained. Therefore, the crystal which is judged to have internal stress after being checked in the prior art does not need to be detained or discarded, and the grinding method of the wafer can save part of the wafer with residual internal stress, thereby avoiding the waste of crystal materials.
Claims (12)
1. A method of polishing a wafer, comprising:
providing a silicon carbide wafer having a first surface and a second surface opposite the first surface; and
subjecting the silicon carbide wafer to a lapping process to lap remove a predetermined amount X from the first surface and the second surface, wherein the lapping process comprises:
performing N double face grindings to remove the predetermined amount X, wherein N is an integer greater than 2 and less than 5, and each of the double face grindings includes grinding the first surface of the silicon carbide wafer, then reversing the silicon carbide wafer and grinding the second surface.
2. The method of claim 1, wherein the first surface is a carbon face and the second surface is a silicon face, and wherein a total amount of removal of the silicon face is different from a total amount of removal of the carbon face in the predetermined amount X.
3. The method of claim 2, wherein the total removal of the silicon side is higher than the total removal of the carbon side.
4. The method of claim 1, wherein the last of the N double side grinds is performed with a removal of the first surface plus the second surface that is less than X/N.
5. The method of claim 1, wherein the first of the N double side grinds has a combined removal of the first surface and the second surface that is greater than X/N.
6. The method of claim 1, wherein the first of the N double face grindings is performed with less than 40% x added to the removal of the first and second surfaces.
7. The method of claim 1, wherein the N-1 th of said turn-ups is performed with less than 40% x added to the removal of said first surface and said second surface.
8. The method of claim 1, wherein performing the N number of face-ups comprises at least:
performing a first of said face-over grindings to remove a specific amount A from said first surface grinding 1 And abrasively removing a specific amount B from the second surface 1 ；
Performing the reverse grinding for the N-1 th time to remove a specific amount A from the first surface grinding (N-1) And abrasively removing a specific amount B from the second surface (N-1) (ii) a And
performing the N-th last lapping to remove a specific amount A from the first surface lapping N And removing a specific amount B from the second surface by grinding N Wherein the specific amount A N Less than the specific amount A (N-1) And the specific amount A 1 And the specific amount B N Greater than the specific amount B (N-1) And the specific amount B 1 。
9. The method of claim 8, wherein the specified amount a N With the specified amount B N Is less than the specific amount A 1 With the specific amount B 1 And less than the specific amount A (N-1) With the specified amount B (N-1) The sum of (a) and (b).
10. The method of claim 8, wherein the specific amount a 1 Is equal to the specific amount A (N-1) And the specific amount B 1 Is equal to the specific amount B (N-1) 。
11. The method of claim 1, wherein the N number of double face grindings is 3 double face grindings.
12. The method of claim 1, wherein the N double face grinds are 4 double face grinds.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW110120939 | 2021-06-09 | ||
| TW110120939A TWI786672B (en) | 2021-06-09 | 2021-06-09 | Method of wafer grinding |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115446670A true CN115446670A (en) | 2022-12-09 |
| CN115446670B CN115446670B (en) | 2023-12-08 |
Family
ID=84295876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210403873.1A Active CN115446670B (en) | 2021-06-09 | 2022-04-18 | Wafer polishing method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115446670B (en) |
| TW (1) | TWI786672B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0745564A (en) * | 1993-08-02 | 1995-02-14 | Mitsubishi Materials Shilicon Corp | Manufacture of wafer in high flatness |
| JP2003229385A (en) * | 2001-11-27 | 2003-08-15 | Sumitomo Mitsubishi Silicon Corp | Method for manufacturing semiconductor wafer |
| CN1787181A (en) * | 2004-12-08 | 2006-06-14 | 中国电子科技集团公司第四十六研究所 | Method for processing chip capable of improving semiconductor chip geometric parameter |
| JP2009105127A (en) * | 2007-10-22 | 2009-05-14 | Denso Corp | Manufacturing method of silicon carbide wafer |
| US20140263176A1 (en) * | 2013-03-14 | 2014-09-18 | Applied Materials, Inc. | Electrostatic chuck refurbishment |
| US20150004799A1 (en) * | 2013-06-26 | 2015-01-01 | Sumco Corporation | Machining process for semiconductor wafer |
| JP2015213120A (en) * | 2014-05-02 | 2015-11-26 | 信越半導体株式会社 | Processing method of wafer |
| US20160288291A1 (en) * | 2015-03-30 | 2016-10-06 | Strasbaugh, Inc. | Method for grinding wafers by shaping resilient chuck covering |
| CN109643650A (en) * | 2016-08-31 | 2019-04-16 | 胜高股份有限公司 | The grinding method and semiconductor wafer of semiconductor wafer |
| JP2020172434A (en) * | 2015-10-15 | 2020-10-22 | 住友電気工業株式会社 | Silicon carbide single crystal substrate and method of manufacturing silicon carbide epitaxial substrate |
| CN114207777A (en) * | 2019-05-23 | 2022-03-18 | 阿斯卡顿股份公司 | Crystal efficient SIC device wafer production |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3271658B2 (en) * | 1998-03-23 | 2002-04-02 | 信越半導体株式会社 | Method for lapping or polishing semiconductor silicon single crystal wafer |
| CN111300259A (en) * | 2020-02-18 | 2020-06-19 | 北京芯之路企业管理中心(有限合伙) | Grinding and polishing device for silicon carbide wafer and manufacturing process method thereof |
-
2021
- 2021-06-09 TW TW110120939A patent/TWI786672B/en active
-
2022
- 2022-04-18 CN CN202210403873.1A patent/CN115446670B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0745564A (en) * | 1993-08-02 | 1995-02-14 | Mitsubishi Materials Shilicon Corp | Manufacture of wafer in high flatness |
| JP2003229385A (en) * | 2001-11-27 | 2003-08-15 | Sumitomo Mitsubishi Silicon Corp | Method for manufacturing semiconductor wafer |
| CN1787181A (en) * | 2004-12-08 | 2006-06-14 | 中国电子科技集团公司第四十六研究所 | Method for processing chip capable of improving semiconductor chip geometric parameter |
| JP2009105127A (en) * | 2007-10-22 | 2009-05-14 | Denso Corp | Manufacturing method of silicon carbide wafer |
| US20140263176A1 (en) * | 2013-03-14 | 2014-09-18 | Applied Materials, Inc. | Electrostatic chuck refurbishment |
| US20150004799A1 (en) * | 2013-06-26 | 2015-01-01 | Sumco Corporation | Machining process for semiconductor wafer |
| JP2015213120A (en) * | 2014-05-02 | 2015-11-26 | 信越半導体株式会社 | Processing method of wafer |
| US20160288291A1 (en) * | 2015-03-30 | 2016-10-06 | Strasbaugh, Inc. | Method for grinding wafers by shaping resilient chuck covering |
| JP2020172434A (en) * | 2015-10-15 | 2020-10-22 | 住友電気工業株式会社 | Silicon carbide single crystal substrate and method of manufacturing silicon carbide epitaxial substrate |
| CN109643650A (en) * | 2016-08-31 | 2019-04-16 | 胜高股份有限公司 | The grinding method and semiconductor wafer of semiconductor wafer |
| CN114207777A (en) * | 2019-05-23 | 2022-03-18 | 阿斯卡顿股份公司 | Crystal efficient SIC device wafer production |
Non-Patent Citations (1)
| Title |
|---|
| 胡安琪: "《Ⅲ族氮化物半导体材料及其在光电和电子器件中的应用》", 北京邮电大学出版社, pages: 3 - 4 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115446670B (en) | 2023-12-08 |
| TWI786672B (en) | 2022-12-11 |
| TW202249099A (en) | 2022-12-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2912681B1 (en) | Method of fabricating flat sic semiconductor substrate | |
| JP5159824B2 (en) | Method for manufacturing a wafer comprising a silicon single crystal substrate having a front surface and a back surface and a layer of SiGe deposited on said front surface | |
| JP5014737B2 (en) | Method for manufacturing SiC single crystal substrate | |
| CN110079862B (en) | Silicon carbide single crystal substrate, silicon carbide epitaxial substrate, and methods for producing these | |
| US20090130960A1 (en) | Method For Producing A Semiconductor Wafer With A Polished Edge | |
| CN110010458B (en) | Method for controlling surface morphology of semiconductor wafer and semiconductor wafer | |
| CN110383427B (en) | Method for manufacturing wafer | |
| Pei et al. | An experimental investigation into soft-pad grinding of wire-sawn silicon wafers | |
| CN1795545A (en) | Production method for semiconductor wafer | |
| CN112585724A (en) | Method for manufacturing SiC chip | |
| CN115446670B (en) | Wafer polishing method | |
| JP4492293B2 (en) | Manufacturing method of semiconductor substrate | |
| US6211088B1 (en) | Manufacturing method for semiconductor gas-phase epitaxial wafer | |
| US5580500A (en) | Method of manufacturing carbon substrate | |
| EP4328958A1 (en) | Method for producing silicon wafer | |
| JP2014040339A (en) | Method for manufacturing piezoelectric oxide single crystal wafer | |
| JP2014213403A (en) | Method for reducing warpage of substrate, method for manufacturing substrate, and sapphire substrate | |
| JP6471686B2 (en) | Silicon wafer chamfering method, silicon wafer manufacturing method, and silicon wafer | |
| JP2004006997A (en) | Manufacturing method of silicon wafer | |
| JP5515253B2 (en) | Manufacturing method of semiconductor wafer | |
| JP2005209862A (en) | Method for manufacturing semiconductor epitaxial wafer | |
| CN106711018B (en) | semiconductor wafer surface processing method | |
| JP2001007064A (en) | Grinding method of semiconductor wafer | |
| JP2007013012A (en) | Beveling method of end face of silicon wafer for solar cell | |
| JP7472546B2 (en) | Method for manufacturing piezoelectric oxide single crystal substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |