JP2005101652A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with FET having high hot carrier resistance. <P>SOLUTION: A semiconductor device 100 is provided with a silicon substrate 102 and a MOSFET 110 formed in the substrate 102. In the device 100, sidewalls 122 for a SAC, which is constituted of a silicon nitride film, are respectively formed on the side parts of a gate electrode 116 of the MOSFET 110 and a diffusion inhibition film 126 to inhibit hydrogen or nitrogen contained in the sidewalls 122 from diffusing to the side of the substrate 102 is formed between the sidewalls 122 and the substrate 102. Accordingly, in the device 100, the diffusion of the hydrogen or the nitrogen to the side of the substrate 102 is suppressed or prevented by the film 126, generation of a trap-interfacial level under the sidewalls 122 is suppressed, and the hot carrier resistance of the MOSFET 110 is improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  MOSFETs (Metal-Oxide Semiconductor Field-Effect-Transistors) formed in LSIs (Large Scale Integrated Circuits) are being miniaturized with the progress of microfabrication technology. In particular, the size of a MOSFET applied to a DRAM (Dynamic Random Access Memory) memory cell is reduced by 40% for each generation. On the other hand, in the MOSFET, it is necessary to provide an alignment margin between the gate electrode and the contact hole. As a result, at present, it has become extremely difficult to appropriately secure the hole diameter of the contact hole and the alignment margin between the gate electrode and the contact hole.

Conventionally, SAC (Self-Aligned Contact) technology has been proposed as a solution to such a problem. Since the SAC technology does not require an alignment margin between the gate electrode and the contact hole, MOSFETs using the SAC technology are mainly used at present.
Regarding the above circumstances, for example, “K. P. Lee et al.,“ A Process Technology for 1 Giga-Bit DRAM ”, IEDM Tech. Dig. , Pp907-910, 1995 ".

  Conventionally, as a SAC process, a SiN-SW method using a high etching selectivity between silicon oxide and silicon nitride has been generalized. Here, the SiN-SW method is a method in which a gate electrode is covered with a sidewall (SW) made of silicon nitride, and a contact hole is formed using the sidewall as an etching stopper film.

  Hereinafter, a conventional SiN-SW SAC process will be described with reference to FIG. FIG. 23 schematically shows a cross-sectional structure of a conventional MOSFET 800 manufactured using SiN-SW SAC technology.

  In the method for manufacturing MOSFET 800, a gate oxide film 824 and a gate electrode 816 are sequentially formed on a silicon substrate 802. Here, the gate oxide film 824 is formed with a substantially uniform film thickness on the entire surface of the silicon substrate 802. Next, a cap film 820 made of silicon nitride is formed on the gate electrode 816. Next, a sidewall 822 made of silicon nitride is formed on the gate oxide film 824 on the side of the gate electrode 816. The sidewalls 822 are formed by LP-CVD (Low Pressure Chemical Vapor Deposition) under a temperature condition of about 720 ° C. and RIE (Reactive Ion Etching) etch back. As a result, the gate electrode 816 is completely covered by the sidewall 822 and the cap film 820 made of silicon nitride.

  However, the conventional MOSFET 800 has lower hot carrier reliability than a conventional MOSFET having a sidewall made of silicon oxide.

  When the hot carrierless test is performed, in the case of a conventional MOSFET, the characteristics (IDs.GM) of the MOSFET are greatly deteriorated in the initial stage of stress. Such a circumstance is described in, for example, “Y-Sambongi et al.,“ Hot-Carrier Degradation Mechanism and Providing Device Design of nMOSFETs with Nitride Sidespace ”, 18:18, p.

  Further, when a silicon nitride film is present in the vicinity of the MOSFET, the characteristics of the MOSFET are greatly deteriorated under a stress condition in which the gate voltage is lower than 1/2 of the source / drain voltage. This situation is described in, for example, “S. Tokyoh et al.,“ Enhancement of Hot-Carrier Induced Degradation under Low Gate Voltage Stress due to Hydrogen for NMOSFETs p. 3 ”.

  This may be because the hot carrier resistance in the region under the sidewall is extremely lower than that in the region under the gate electrode in the structure in which the gate electrode is covered with silicon nitride. If some of the hot carriers generated near the drain are injected under the sidewall having low hot carrier resistance, the characteristics of the MOSFET are greatly deteriorated when stress is applied.

  Further, the gate oxide film under the gate electrode is also in a state where the interface order is likely to be generated due to the diffusion of hydrogen in the sidewall by annealing for activating the source region / drain region. As a result, traps are generated in the vicinity of the gate oxide film, and the characteristics of the MOSFET may be greatly deteriorated.

As described above, the conventional MOSFET has a structure in which the gate electrode is covered with silicon nitride with a configuration in which countermeasures against hot carriers are insufficient, so that the resistance to hot carriers is lowered and the characteristics of the MOSFET are easily deteriorated. .
The present invention has been made in view of the above-described other problems of conventional semiconductor devices and semiconductor device manufacturing methods.

In order to solve the above problems, the invention according to the present application employs the following configuration in a semiconductor device including a semiconductor substrate and an FET formed on the semiconductor substrate.
A side wall for SAC formed mainly on the gate electrode side of the FET and mainly containing nitrogen and silicon in the composition, and an element formed between the side wall and the semiconductor substrate and contained in the side wall toward the semiconductor substrate side A configuration including a diffusion suppression film that suppresses diffusion is employed.

  Here, it is possible to adopt a configuration in which the film thickness of the diffusion suppression film is set to such a size that the diffusion of the element does not reach the vicinity of the boundary between the diffusion suppression film and the semiconductor substrate. Furthermore, a structure formed by CVD can be employed as the diffusion suppression film. Furthermore, the diffusion prevention film can be configured to be formed by thermal oxidation of the semiconductor substrate surface. Furthermore, a configuration including an oxidation wall formed by thermal oxidation on the side surface of the gate electrode can be employed. Furthermore, a configuration in which the diffusion suppression film is a silicon oxide film can be employed. Further, a configuration in which hydrogen is contained in the element can be employed. Furthermore, a configuration in which nitrogen is contained in the element can be employed.

  A configuration is adopted that includes a sidewall for SAC formed on the side of the gate electrode of the FET and mainly containing nitrogen and silicon in the composition and formed by LP-CVD at 850 ° C. or higher.

  In addition, a sidewall for SAC formed mainly on the gate electrode side of the FET and containing mainly nitrogen and silicon in the composition is provided. The sidewall is composed of two or more layers, and the lowermost layer is an LP having an upper layer of 850 ° C. or more. -The structure formed by CVD is adopted.

  Furthermore, the FET has an LDD structure, and the LDD portion of the FET adopts a structure formed by ion implantation of two or more times with different implantation energies.

  In order to solve the above problems, the invention according to the present application employs the following configuration in a method of manufacturing a semiconductor device including a semiconductor substrate and an FET formed on the semiconductor substrate.

  Side wall forming step for forming side wall for SAC mainly including nitrogen and silicon in composition on side of gate electrode of FET, and semiconductor substrate of element contained in side wall before the side wall forming step And a diffusion suppression film forming step of forming a diffusion suppression film for suppressing side diffusion at a portion where the sidewall is to be formed. Here, the structure formed by CVD can be employ | adopted for a diffusion suppression film | membrane. Further, the diffusion suppressing film can be formed by thermal oxidation of the semiconductor substrate surface.

  Further, a side wall forming step for forming a side wall for SAC mainly containing nitrogen and silicon in the composition on the side of the gate electrode of the FET, and a semiconductor of an element contained in the side wall after the side wall forming step A structure including a diffusion suppression film forming step of forming a diffusion suppression film for suppressing diffusion to the substrate side between the sidewall and the semiconductor substrate is adopted. Here, a structure formed by thermal oxidation of the surface of the semiconductor substrate can be adopted as the diffusion suppression film.

  Further, a sidewall forming step for forming a sidewall for SAC mainly containing nitrogen and silicon in the composition on the side of the gate electrode of the FET, and an interlayer insulating film made of BPSG covering the FET and the sidewall Forming an interlayer insulating film on the semiconductor substrate, and forming a diffusion inhibiting film for suppressing diffusion of elements contained in the sidewall into the semiconductor substrate side by heat-treating the wafer on which the interlayer insulating film is formed. And a diffusion suppression film forming step formed between the semiconductor substrate and the semiconductor substrate.

  In the above configuration, before the sidewall forming step, a gate insulating film forming step for forming a gate insulating film covering at least a portion where the sidewall is to be formed and a portion where the gate electrode is to be formed on the semiconductor substrate; A gate electrode forming step of forming a gate electrode on the gate insulating film, and adopting a configuration in which the diffusion suppression film is formed by increasing the thickness of the gate insulating film covering the portion where the sidewall is to be formed Can do.

  Further, a side wall forming step for forming a side wall for SAC mainly containing nitrogen and silicon in the composition on the side of the gate electrode of the FET, and when an element contained in the side wall diffuses on the surface of the semiconductor substrate, the semiconductor And a thermal oxidation process that thermally oxidizes the substrate surface.

  Furthermore, for the gate insulating film forming step for forming the gate insulating film on the surface of the semiconductor substrate, the gate electrode forming step for forming the gate electrode of the FET on the gate insulating film, and the SAC mainly containing nitrogen and silicon in the composition. Forming a sidewall on the side of the gate electrode of the FET, and thermally oxidizing the gate insulating film and the semiconductor substrate when elements contained in the sidewall diffuse to the semiconductor substrate surface through the gate oxide film And a thermal oxidation process.

  In the above configuration, a configuration in which hydrogen is included in the element can be employed. Furthermore, a configuration in which nitrogen is contained in the element can be employed.

  It is composed of silicon nitride by forming a film mainly containing nitrogen and silicon in the composition by LP-CVD at 850 ° C. or higher and covering the top and side surfaces of the gate electrode of the FET, and etching back the film by RIE. And a sidewall forming step of forming a sidewall for SAC on the side of the gate electrode.

  Furthermore, a step of forming a first film mainly containing nitrogen and silicon by LP-CVD at 850 ° C. or higher and covering the upper surface and side surfaces of the gate electrode of the FET, and mainly containing nitrogen and silicon on the first film A step of forming a second film, and a step of forming a sidewall for SAC mainly containing nitrogen and silicon on the side of the gate electrode by etching back the first and second films by RIE. Adopt a configuration that includes.

  Furthermore, the FET has an LDD structure, and the LDD portion of the FET adopts a configuration formed by two or more ion implantations having different implantation energies.

The invention according to the present invention having the above-described configuration improves the hot carrier resistance of the FET by suppressing the generation of traps or interface states near the surface of the semiconductor substrate by at least one of the following first to fourth aspects. Can be made.
First aspect: A diffusion suppression film that suppresses diffusion of an element (for example, hydrogen or nitrogen) from the sidewall to the semiconductor substrate is formed between the sidewall and the semiconductor substrate.
Second viewpoint: The vicinity of the surface of the semiconductor substrate where hydrogen or nitrogen may be diffused is oxidized by thermal oxidation.
(3) Third aspect: By forming the sidewall material in a high temperature atmosphere, the amount of hydrogen released from the sidewall, at least the amount of hydrogen released from the sidewall to the semiconductor substrate side is reduced. .
(4) Fourth aspect: The hot carrier generation position is moved to the deep part of the semiconductor substrate by forming the LDD part by multiple ion implantations with different implantation energies.

  In each of the embodiments described later, a MOSFET having an LDD structure is mainly exemplified as an FET, a silicon substrate is exemplified as a semiconductor substrate, and a gate insulating film made of silicon oxide is exemplified as a diffusion suppression film. As an example, the gate electrode is composed of polysilicon doped with a predetermined impurity, and the sidewall is composed of silicon nitride.

  ADVANTAGE OF THE INVENTION According to this invention, a semiconductor device provided with MOSFET with high hot carrier tolerance can be provided.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
The first embodiment will be described with reference to FIGS. Here, FIG. 1 is a schematic cross-sectional view for explaining a main configuration of the semiconductor device 100 according to the present embodiment. FIG. 2 is a schematic flowchart for explaining the semiconductor device manufacturing method 150 according to the present embodiment. FIG. 3 is a schematic cross-sectional view for supplementing the explanation of FIG.

In this embodiment, diffusion of hydrogen or nitrogen contained in the sidewall into the silicon substrate is suppressed or prevented by the diffusion prevention film.
As shown in FIG. 1, the semiconductor device 100 includes a silicon substrate 102, an interlayer insulating film 104, and a MOSFET 110. In the semiconductor device 100, the MOSFET 110 is formed on the silicon substrate 102. The interlayer insulating film 104 is laminated on the silicon substrate 102 and covers the MOSFET 110. The interlayer insulating film 104 is made of a predetermined insulating material such as silicon oxide.

  The MOSFET 110 includes a source region 112, a drain region 114, a gate electrode 116, and a channel region 118. Here, the source region 112 includes an LDD portion 112a, and the drain region 114 includes an LDD portion 114a. In the MOSFET 110, the source region 112, the drain region 114, and the channel region 118 are included in the silicon substrate 102. The gate electrode 116 is provided on the silicon substrate 102. The source region 112 and the drain region 114 are formed in the vicinity of two sides of the gate electrode 116 facing each other. The channel region 118 is formed under the gate electrode 116, that is, between the source region 112 and the drain region 114.

  The source region 112 and the drain region 114 are made of a predetermined conductive semiconductor, for example, silicon doped with a predetermined impurity, and have the same conductivity. The gate electrode 116 is made of a predetermined conductive material, for example, polysilicon doped with a predetermined impurity. The channel region 118 is made of a predetermined conductive semiconductor, for example, silicon doped with a predetermined impurity. When the MOSFET 110 is an enhancement type, the channel region 118 has conductivity opposite to that of the source region 112 and the drain region 114. On the other hand, when MOSFET 110 is a depletion type, channel region 118 has the same conductivity as source region 112 and drain region 114.

  Further, the MOSFET 110 includes a cap film 120 and sidewalls 122. In the MOSFET 110, the cap film 120 is formed on the upper surface of the gate electrode 116. The sidewall 122 is formed on the silicon substrate 102 on the side of the gate electrode 116 and covers the side surface of the gate electrode 116. Therefore, in the MOSFET 110, the vicinity of the gate electrode 116 in the source region 112 and the drain region 114 is covered with the sidewall 122. The cap film 120 and the sidewall 122 are made of a material different from that of the interlayer insulating film 104. The cap film 120 and the sidewall 122 are made of, for example, silicon nitride.

  The MOSFET 110 further includes a gate oxide film 124 and a diffusion suppression film 126. In the MOSFET 110, the gate oxide film 124 and the diffusion suppression film 126 are formed on the surface of the silicon substrate 102. The gate oxide film 124 is formed under the gate electrode 116, and the diffusion suppression film 126 is formed under the sidewall. That is, the gate oxide film 124 is formed between the gate electrode 116 and the channel region 118, and the diffusion suppression film 126 is formed between the sidewall 122 and the source region 112 and between the sidewall 122 and the drain region 114. It is formed.

The diffusion suppression film 126 suppresses diffusion of hydrogen and nitrogen contained in the sidewall 122 into the silicon substrate 102. In this embodiment, the diffusion suppressing film 126 has such a thickness that hydrogen or nitrogen in the sidewall 122 does not reach the vicinity of the boundary with the silicon substrate 102 even if hydrogen or nitrogen diffuses. Here, the thickness of the diffusion suppression film 126 is designed in consideration of the width of the sidewall 122 in particular.
In the present embodiment, the diffusion suppression film 126 is made of a predetermined insulating material such as silicon oxide.

  Furthermore, the semiconductor device 100 includes a first contact hole 106a formed by SAC technology and a first embedded wiring 108a embedded in the first contact hole 106a. The first contact hole 106 a is formed by utilizing the etching rate difference between the cap film 120, the sidewall 122, and the interlayer insulating film 104. The first contact hole 106a penetrates the interlayer insulating film 104 and exposes the surface of the source region 112 or the drain region 114 at the bottom thereof. The first buried wiring 108a is contact-connected to the source region 112 or the drain region 114 at the bottom of the first contact hole 106a.

  Further, the semiconductor device 100 includes a second contact hole 106b and a second embedded wiring 108b that is embedded in the second contact hole 106b. The second contact hole 106b penetrates the interlayer insulating film 104 and exposes the surface of the gate electrode 116 at the bottom. The second buried wiring 108b is contact-connected to the gate electrode 116 at the bottom of the second contact hole 106b.

  In the semiconductor device 100, the source region 112, the drain region 114, and the gate electrode 116 are connected to other components provided in the semiconductor device 100, respectively. For example, when the semiconductor device 100 is a semiconductor memory and the MOSFET 110 is a memory cell transistor, the source region 112 is connected to the bit line via the first buried wiring 108a, and the drain region 114 is another first buried region. The storage electrode is connected to the storage capacitor through the buried wiring 108a, and the gate electrode 116 is connected to the word line through the second buried wiring 108b.

  Next, a semiconductor device manufacturing method 150 according to the present embodiment applicable to the semiconductor device 100 will be described with reference to FIGS. As shown in FIG. 2, the manufacturing method 150 includes at least steps S1 to S8. In the manufacturing method 150, steps S1 to S8 are performed in this order.

  In step S1, a gate oxide film 124 is formed. The gate oxide film 124 is formed on the entire surface of the silicon substrate 102. The gate oxide film 124 can be formed, for example, by oxidizing the surface of the silicon substrate 102.

  In step S2, the gate electrode 116 and the cap film 120 are formed. The gate electrode 116 is formed on the gate oxide film 124 where the channel region 118 is to be formed. The cap film 120 is formed on the gate electrode 116. In step S2, the gate electrode 116 and the cap film 120 are formed, for example, by sequentially forming the material film of the gate electrode 116 and the material film of the cap film 120 as shown in FIG. As shown in (b), it can be formed by patterning the material film by photolithography and etching.

  In step S3, LDD portions 112a and 114a are formed. The LDD portions 112a and 114a can be formed by ion implantation using the cap film 120 as a mask, for example.

  In step S4, the diffusion suppression film 126 is formed. The diffusion suppression film 126 is formed at least at a portion where the sidewall 122 is to be formed on the side of the gate electrode 124. For example, as shown in FIG. 3C, the diffusion suppression film 126 can be formed by increasing the thickness of the corresponding gate oxide film 124 while controlling the film formation rate in CVD. As a result, the diffusion suppression film 126 has a thickness larger than that of the gate oxide film 124. The film thickness of the diffusion suppression film 126 can be set to be twice or more that of the gate oxide film 124, for example. The film thickness of the diffusion suppressing film 126 can be set to, for example, 10 μm to 20 μm (100 Å to 200 Å).

  In step S5, the sidewall 122 is formed. The sidewall 122 is formed on the diffusion suppression film 126 on the side of the gate electrode 116. The sidewall 122 can be formed, for example, by first forming a silicon nitride film with a predetermined thickness on the entire surface of the wafer by LP-CVD, and then performing etch back by RIE on the silicon nitride film. The thickness of the silicon nitride film used as the sidewall 122 can be set to, for example, 100 μm to 200 μm (1000 Å to 2000 Å).

  In step S6, the source region 112 and the drain region 114 are formed. As a result, the FET 110 is formed on the silicon substrate 102. The source region 112 and the drain region 114 can be formed, for example, by first performing ion implantation using the sidewall 122 as a spacer and then performing activation by annealing.

  In step S7, an interlayer insulating film 104 is formed. The interlayer insulating film 104 is laminated on the silicon substrate 102 so as to cover the MOSFET 110. The interlayer insulating film 104 can be formed by, for example, CVD. The interlayer insulating film 104 is made of an insulating material different from that of the sidewalls 122 and the cap film 120, for example, silicon oxide.

  In step S8, the first contact hole 106a is formed. The first contact hole 106a is formed in the interlayer insulating film 104 by etching using SAC technology. That is, the first contact hole 106 a is formed on the predetermined source region 112 or the drain region 114 using the difference in etching rate between the interlayer insulating film 104, the sidewall 122, and the cap film 120.

  In addition to the steps S1 to S8, the manufacturing method 150 includes a process for forming the first embedded wiring 108a, a process for forming the second contact hole 106b, a process for forming the second embedded wiring 108b, and other processes. However, detailed explanations thereof are omitted.

  As described above, in the semiconductor device according to the present embodiment, the diffusion suppression film made of silicon oxide exists under the sidewall. The diffusion suppression film 126 suppresses diffusion of hydrogen and nitrogen contained in the sidewall 122 to the silicon substrate 102 side.

  Therefore, according to the present embodiment, a high-quality silicon / silicon oxide interface is formed on the surface of the silicon substrate, and a silicon / silicon nitride interface that easily traps hot carriers is not formed. As a result, according to the present embodiment, it is possible to suppress the generation of traps and interface states under the sidewall, and the hot carrier resistance of the MOSFET can be improved.

  Furthermore, in the semiconductor device manufacturing method according to the present embodiment, after the gate electrode is patterned, the conditions for the oxide film CVD can be tuned to form the diffusion suppression film. Furthermore, in the method for manufacturing a semiconductor device according to the present embodiment, since the diffusion suppression film can be formed without using thermal oxidation, the process temperature can be lowered. Therefore, according to the present embodiment, the thickness of the diffusion suppression film can be controlled with high accuracy, and the characteristics of the MOSFET can be easily controlled.

(Second Embodiment)
The second embodiment will be described with reference to FIGS. Here, FIG. 4 is a schematic cross-sectional view for explaining a main configuration of the semiconductor device 200 according to the present embodiment. FIG. 5 is a schematic flowchart for explaining the semiconductor device manufacturing method 250 according to the present embodiment. FIG. 6 is a schematic cross-sectional view for supplementing the explanation of FIG.

In the present embodiment, diffusion of hydrogen and nitrogen contained in the sidewall to the silicon substrate side is suppressed or prevented by the diffusion suppression film.
As shown in FIG. 4, the semiconductor device 200 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment shown in FIG. 1 in that it has an oxidation wall 216a. The semiconductor device 200 is substantially in common with the semiconductor device 100 shown in FIG.

  In the semiconductor device 200, the oxidation wall 216 a is formed on the side surface of the gate electrode 216 by oxidizing the side surface of the gate electrode 216. The oxide wall 216a is made of, for example, silicon oxide.

  Next, a semiconductor device manufacturing method 250 according to this embodiment applicable to the semiconductor device 200 will be described with reference to FIGS. As shown in FIG. 5, the manufacturing method 250 according to the present embodiment includes at least steps S11 to S18. In the manufacturing method 250, step S11 to step S18 are performed in this order.

  In the manufacturing method 250, steps S11 to S13 and steps S15 to S18 are substantially the same as the corresponding steps of the manufacturing method 150 according to the first embodiment shown in FIG. Here, step S11 corresponds to step S1, step S12 corresponds to step S2, step S13 corresponds to step S3, step S15 corresponds to step S5, step S16 corresponds to step S6, and step S17. Corresponds to step S7, and step S18 corresponds to step S8.

  In the manufacturing method 250, in step S14, the wafer in the state shown in FIG. As a result, as shown in FIG. 6B, the surface of the silicon substrate 202 on the side of the gate electrode 216 is oxidized to increase the thickness of the gate insulating film 224, thereby forming a diffusion suppression film 226. . At the same time, the side surface of the gate electrode 216 is oxidized, and an oxidation wall 216a is formed on the side surface of the gate electrode 216. The thermal oxidation process in step S14 is performed in an oxygen atmosphere at about 850 ° C., for example.

  In the method for manufacturing the semiconductor device 200 described above, as shown in FIG. 6C, the diffusion suppression film 226 exists under the sidewall 222 in step S6. Therefore, even when annealing is performed to activate the source region 212 and the drain region 214, the diffusion suppression film 226 suppresses or prevents diffusion of hydrogen or nitrogen contained in the sidewall 222 into the silicon substrate 202. The As a result, the occurrence of traps under the side wall 222 is prevented, and it is difficult for the manufactured MOSFET 210 to deteriorate in characteristics.

  The manufacturing method 250 according to the present embodiment includes, in addition to steps S11 to S18, a first embedded wiring forming step, a second contact hole forming step, a second embedded wiring forming step, and other steps. However, detailed explanations thereof are omitted.

  As described above, in the semiconductor device according to the present embodiment, the diffusion suppression film made of silicon oxide exists under the sidewall. Therefore, a high-quality silicon / silicon oxide interface is formed on the surface of the silicon substrate, and a silicon / silicon nitride interface that easily traps hot carriers is not formed. As a result, according to the present embodiment, it is possible to suppress the generation of traps and interface states under the sidewall, and the hot carrier resistance of the MOSFET can be improved.

(Third embodiment)
The third embodiment will be described with reference to FIGS. Here, FIG. 7 is a schematic cross-sectional view for explaining a main configuration of the semiconductor device 300 according to the present embodiment. FIG. 8 is a schematic flowchart for explaining the semiconductor device manufacturing method 350 according to the present embodiment. FIG. 9 is a schematic cross-sectional view for supplementing the explanation of FIG.

  In the present embodiment, diffusion of hydrogen and nitrogen contained in the sidewall to the silicon substrate side is suppressed by the diffusion suppression film. Further, in this embodiment, the generation of traps and interface states near the surface of the silicon substrate is suppressed by thermally oxidizing the gate oxide film and the silicon substrate in which hydrogen and nitrogen are diffused.

  As shown in FIG. 7, the semiconductor device 300 according to the present embodiment is structurally substantially the same as the semiconductor device 100 according to the first embodiment shown in FIG. However, the semiconductor device 300 differs from the semiconductor device 100 according to the first embodiment shown in FIG.

  A manufacturing method 350 according to the present embodiment applicable to the semiconductor device 300 will be described with reference to FIGS. As shown in FIG. 8, the manufacturing method 350 according to the present embodiment includes at least steps S21 to S28. In the manufacturing method 350, step S21 to step S28 are performed in this order.

  In the manufacturing method 350, steps S21 to S23 and steps S26 to S28 are substantially the same as the corresponding steps of the manufacturing method 150 according to the first embodiment shown in FIG. Here, step S21 corresponds to step S1, step S22 corresponds to step S2, step S23 corresponds to step S3, step S26 corresponds to step S6, step S27 corresponds to step S7, and step S28. Corresponds to step S8.

  In the manufacturing method 350, at the end of step S23, a wafer in the state shown in FIG. 9A is formed. As shown in FIG. 9B, in step S24, sidewalls 322 are formed on the wafer. The side wall 322 is formed on the gate oxide film 324 on the side of the gate electrode 316. The sidewall 322 can be formed, for example, by first forming a silicon nitride film having a predetermined thickness on the entire wafer surface by LP-CVD and then performing RIE etch back on the silicon nitride film. Note that the thickness of the silicon nitride film to be the sidewall 322 can be, for example, 100 μm to 200 μm (1000 Å to 2000 Å).

  As shown in FIG. 9C, in step S25, a diffusion suppression film 326 is formed under the sidewall 322. The diffusion suppressing film 326 is formed by thermally oxidizing the wafer shown in FIG. 9B to increase the thickness of the gate oxide film 324 under the sidewall 322.

  In this thermal oxidation treatment, the thickening of the gate oxide film 324 under the sidewall 322 starts from the edge portion 322a of the sidewall 322 and gradually extends to the vicinity of the gate electrode 316. In the thermal oxidation process, the surface of the silicon substrate 302 and the gate oxide film 324 in which hydrogen and nitrogen are diffused from the sidewalls 322 are further oxidized in the formation process of the diffusion suppressing film 326. The thermal oxidation treatment is performed in an oxygen atmosphere at about 850 ° C., for example.

  The manufacturing method 350 according to the present embodiment includes a first embedded wiring forming process, a second contact hole forming process, a second embedded wiring forming process, and other processes in addition to the processes S21 to S28. However, detailed explanations thereof are omitted.

  In the semiconductor device according to the present embodiment described above, the diffusion suppression film made of silicon oxide exists under the sidewall. The diffusion suppression film suppresses diffusion of hydrogen and nitrogen from the sidewall to the semiconductor substrate side.

  Therefore, a high-quality silicon / silicon oxide interface is formed on the surface of the silicon substrate, and a silicon / silicon nitride interface that easily traps hot carriers is not formed. As a result, according to the present embodiment, it is possible to suppress the generation of traps and interface states under the sidewall, and the hot carrier resistance of the MOSFET can be improved.

  Furthermore, in the present embodiment, after the sidewall is formed, hydrogen diffused from the sidewall to the gate oxide film can be reduced by the thermal oxidation process at the time of forming the diffusion suppression film. Therefore, the present embodiment has a higher effect of improving the film quality under the sidewall and the gate oxide film than the first and second embodiments.

  Furthermore, in this embodiment, since the diffusion suppression film is formed by the thermal oxidation process after the sidewall formation, the side surface of the gate electrode is not oxidized by the thermal oxidation process. Therefore, according to the present embodiment, fluctuations in the sheet resistance of the gate electrode can be suppressed.

(Fourth embodiment)
The fourth embodiment will be described with reference to FIGS. Here, FIG. 10 is a schematic cross-sectional view for explaining a main configuration of the semiconductor device 400 according to the present embodiment. FIG. 11 is a schematic flowchart for explaining the semiconductor device manufacturing method 450 according to the present embodiment. FIG. 12 is a schematic cross-sectional view for supplementing the explanation of FIG.

  In the present embodiment, diffusion of hydrogen and nitrogen contained in the sidewall to the silicon substrate side is suppressed by the diffusion suppression film. Further, in this embodiment, the generation of traps and interface states near the surface of the silicon substrate is suppressed by thermally oxidizing the gate oxide film and the silicon substrate in which hydrogen and nitrogen are diffused.

  As shown in FIG. 10, the semiconductor device 400 according to the present embodiment is different from the semiconductor device 300 according to the third embodiment shown in FIG. 7 in that it has a diffusion suppressing film instead of the diffusion preventing film. Furthermore, the semiconductor device 400 is different from the semiconductor device 300 shown in FIG. 7 in that the interlayer insulating film is made of BPSG (Boro-Phospho Silicate Glass). The semiconductor device 300 is substantially in common with the semiconductor device 300 shown in FIG. 7 in other configurations.

  Next, a semiconductor device manufacturing method 450 according to this embodiment applicable to the semiconductor device 400 will be described with reference to FIGS. 11 and 12. As shown in FIG. 11, the manufacturing method 450 according to the present embodiment includes at least steps S31 to S38. In the manufacturing method 450, steps S31 to S38 are performed in this order.

  In the manufacturing method 450, steps S31 to S34 and step S38 are substantially the same as the corresponding steps of the manufacturing method 350 according to the third embodiment shown in FIG. Here, step S31 corresponds to step S21, step S32 corresponds to step S22, step S33 corresponds to step S23, step S34 corresponds to step S24, and step S38 corresponds to step S28.

  In the manufacturing method 450, in step S35, a source region 412 and a drain region 414 are formed as shown in FIG. As a result, the FET 410 is formed on the silicon substrate 402. The source region 412 and the drain region 414 can be formed, for example, by first performing ion implantation using the sidewall 422 as a spacer and then performing activation by annealing.

  In step S36, an interlayer insulating film 404 is formed as shown in FIG. In this embodiment, the interlayer insulating film 404 is made of BPSG. The interlayer insulating film 404 is laminated on the silicon substrate 402 so as to cover the MOSFET 410. In step S36, the interlayer insulating film 404 can be formed by, for example, CVD. In step S36, the interlayer insulating film 404 can have a layer thickness of, for example, 300 μm to 500 μm (3000 Å to 5000 Å).

  In step S37, as shown in FIG. 12C, a diffusion suppression film 426 is formed. The diffusion suppression film 426 can be formed by heat-treating the wafer in the state shown in FIG. 12B and thermally oxidizing the surface of the silicon substrate 402 under the sidewall 422. In this step S37, the thermal oxidation of the gate oxide film 424 under the sidewall 422 starts from the edge portion 422a of the sidewall 422 and gradually extends to the vicinity of the gate electrode 416. The heat treatment in step S37 is performed in an oxygen atmosphere at about 850 ° C., for example.

  In this embodiment, the diffusion suppression film 426 does not exist under the sidewall 422 before step S37. Therefore, hydrogen and nitrogen contained in the sidewall 422 are easily diffused to the silicon substrate 402 side through the gate oxide film 424. However, even if hydrogen and nitrogen are diffused in this way, the surfaces of the gate oxide film 424 and the silicon substrate 402 are oxidized in the formation process of the diffusion suppression film 426 in step S37. As a result, in the manufacturing method 450, the generation of traps under the sidewall 422 is prevented, and it is difficult for the manufactured MOSFET 410 to deteriorate in characteristics.

  The manufacturing method 450 according to the present embodiment includes, in addition to steps S31 to S38, a first embedded wiring forming step, a second contact hole forming step, a second embedded wiring forming step, and other steps. However, detailed explanations thereof are omitted.

  According to the present embodiment described above, hydrogen or nitrogen once diffused from the side wall is replaced with oxygen by forming the diffusion suppression film. As a result, according to the present embodiment, it is possible to suppress the generation of traps and interface states under the sidewall, and the hot carrier resistance of the MOSFET can be improved.

  Furthermore, in this embodiment, since the diffusion suppression film is formed by the heat treatment after the sidewall formation, the side surface of the gate electrode is not oxidized by the heat treatment. Therefore, according to the present embodiment, fluctuations in the sheet resistance of the gate electrode can be suppressed.

  Furthermore, according to the present embodiment, the diffusion control film formation flow and the BPSG flow for planarizing the interlayer insulating film can be performed in a single step. Therefore, according to this embodiment, the process can be simplified.

(Fifth embodiment)
The fifth embodiment will be described with reference to FIGS. Here, FIG. 13 is a schematic cross-sectional view for explaining a main configuration of the semiconductor device 500 according to the present embodiment. FIG. 14 is a schematic flowchart for explaining the semiconductor device manufacturing method 550 according to the present embodiment. FIG. 15 is a schematic cross-sectional view for supplementing the explanation of FIG.

In this embodiment, the amount of hydrogen released from the sidewall is reduced overall by forming the sidewall in a high temperature atmosphere.
As shown in FIG. 13, the semiconductor device 500 according to this embodiment is different from the semiconductor device 100 according to the first embodiment shown in FIG. 1 in that it does not have a diffusion prevention film. Further, the semiconductor device 500 has a feature according to the present embodiment in the method of forming the sidewall 522. The semiconductor device 500 is substantially in common with the semiconductor device 100 shown in FIG.

  A semiconductor device manufacturing method 550 that can be applied to the semiconductor device 500 will be described with reference to FIGS. As shown in FIG. 14, the manufacturing method 550 includes at least steps S41 to S47. In the manufacturing method 550, steps S41 to S47 are performed in this order.

  In the manufacturing method 550, steps S41 to S43 and steps S45 to S47 are substantially the same as the corresponding steps of the manufacturing method 150 according to the first embodiment shown in FIG. Here, step S41 corresponds to step S1, step S42 corresponds to step S2, step S43 corresponds to step S3, step S45 corresponds to step S6, step S46 corresponds to step S7, and step S47. Corresponds to step S8.

  In the manufacturing method 550, a wafer shown in FIG. 15A is formed at the end of step S43. In step S44, as shown in FIG. 15B, sidewalls 522 are formed on the wafer. In step S44, the sidewall 522 is formed by first forming a silicon nitride film having a predetermined thickness on the entire surface of the wafer by LP-CVD, and then performing etch back by RIE on the silicon nitride film.

  In the present embodiment, the LP-CVD in step S44 is performed in a high temperature atmosphere of about 850 ° C. or higher (especially 850 ° C. to 900 ° C.). In the manufacturing method 550, the amount of hydrogen released from the sidewall 522 in a later step can be reduced by forming a silicon nitride film by LP-CVD at a temperature of about 850 ° C. or higher in step S44. Therefore, the amount of hydrogen diffused from the sidewall 522 to the silicon substrate 502 via the gate oxide film 524 is reduced, and the generation of traps near the surface of the silicon substrate 502 is suppressed.

  Note that general LP-CVD is performed under a temperature condition of about 780 ° C. The temperature condition of about 850 ° C. or more exceeds the heat resistance limit of the core of a general LP-CVD apparatus.

  The manufacturing method 550 according to the present embodiment includes, in addition to steps S41 to S47, a first buried wiring forming step, a second contact hole forming step, a second buried wiring forming step, and other steps. However, detailed explanations thereof are omitted.

  As described above, according to this embodiment, it is difficult for hydrogen separated in the CVD process to reach the silicon / silicon nitride interface on the surface of the silicon substrate. According to the knowledge of the inventors, the amount of hydrogen can be reduced to about 1/3 of the case where LP-CVD for forming a sidewall is performed at a temperature condition of about 780 ° C.

  Therefore, according to the present embodiment, generation of traps at the silicon / silicon nitride interface is suppressed, and further, diffusion of hydrogen in the sidewall into the gate oxide film and the silicon substrate is suppressed. As a result, according to the present embodiment, the hot carrier resistance of the MOSFET can be improved.

(Sixth embodiment)
The sixth embodiment will be described with reference to FIGS. Here, FIG. 16 is a schematic cross-sectional view for explaining a main configuration of the semiconductor device 600 according to the present embodiment. FIG. 17 is a schematic flowchart for explaining the semiconductor device manufacturing method 650 according to the present embodiment. FIG. 18 is a schematic cross-sectional view for supplementing the explanation of FIG.

In this embodiment, the amount of hydrogen released downward from the sidewall is reduced by forming the sidewall from a plurality of layers and forming the lowermost layer in a high temperature atmosphere.
As shown in FIG. 16, the semiconductor device 600 according to the present embodiment is different from the semiconductor device 500 according to the fifth embodiment shown in FIG. The semiconductor device 600 is substantially in common with the semiconductor device 500 shown in FIG. 13 in other configurations.

  In the semiconductor device 600, the sidewall 622 includes a first film 622a formed on the silicon substrate 602 side and a second film 622b formed on the first film 622a. The first film 622a is formed by LP-CVD in a high temperature atmosphere of about 850 ° C. to 900 ° C., for example, and the second film 622b is formed by LP-CVD under a general temperature condition of about 780 ° C., for example. It has been done.

  A semiconductor device manufacturing method 650 according to the present embodiment that can be applied to the semiconductor device 600 will be described with reference to FIGS. As shown in FIG. 17, the manufacturing method 650 according to this embodiment includes at least steps S51 to S57. In the manufacturing method 650, step S51 to step S57 are performed in this order.

  In the manufacturing method 650, steps S51 to S53 and steps S54 to S57 are substantially the same as the corresponding steps of the manufacturing method 550 according to the fifth embodiment shown in FIG. Here, step S51 corresponds to step S41, step S52 corresponds to step S42, step S53 corresponds to step S43, step S55 corresponds to step S45, step S56 corresponds to step S46, and step S57. Corresponds to step S47.

  In the manufacturing method 650, step S54 is performed as follows. First, as shown in FIG. 18A, a first silicon nitride film 622a 'is formed on the entire wafer surface by LP-CVD in a high temperature atmosphere of about 850 ° C. or higher. Next, as shown in FIG. 18B, a second silicon nitride film 622b 'is formed on the first silicon nitride film 622a' by LP-CVD under a normal temperature condition of about 780 ° C. Next, as shown in FIG. 18C, the first silicon nitride film 622a 'and the second silicon nitride film 622b' are etched back by RIE.

  As a result, a sidewall 622 is formed on the side of the gate electrode 616. Here, the first silicon nitride film 622a ′ remaining on the side of the gate electrode 616 after the etch back becomes the first film 622a, and the second silicon nitride film 622b ′ remaining on the side of the gate electrode 616 after the etch back. Becomes the second film 622b.

  In the present embodiment, the thickness of the first silicon nitride film 622a ′ is, for example, 20 μm to 40 μm (200 Å to 400 Å), and the thickness of the second silicon nitride film 622b ′ is, for example, 80 μm to 160 μm (800 Angstrom to 1600 angstrom).

  The manufacturing method 650 according to the present embodiment includes, in addition to steps S51 to S57, a first buried wiring forming step, a second contact hole forming step, a second buried wiring forming step, and other steps. However, detailed explanations thereof are omitted.

  As described above, according to the present embodiment, the first silicon nitride film makes it difficult for hydrogen deviated in the formation process of the second silicon nitride film to reach the silicon / silicon nitride interface on the silicon substrate surface. Therefore, according to the present embodiment, generation of traps at the silicon / silicon nitride interface is suppressed more than in the sixth embodiment, and further, diffusion of hydrogen in the sidewall into the gate oxide film and the silicon substrate is suppressed. . As a result, according to the present embodiment, the hot carrier resistance of the MOSFET can be improved.

(Seventh embodiment)
The seventh embodiment will be described with reference to FIGS. Here, FIG. 19 is a schematic cross-sectional view for explaining a main configuration of the semiconductor device 700 according to the present embodiment. FIG. 20 is a schematic flowchart for explaining the semiconductor device manufacturing method 750 according to the present embodiment. FIG. 21 is a schematic cross-sectional view for supplementing the explanation of FIG. FIG. 22 is a schematic diagram showing impurity profiles of the LDD portions 712a and 714a of the semiconductor device 700.

In this embodiment, the LDD portion is formed by ion implantation a plurality of times, thereby moving the hot carrier generation position to a deep portion of the semiconductor substrate away from the trap or interface state generation position.
As shown in FIG. 19, the semiconductor device 700 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment shown in FIG. 1 in that it does not have a diffusion prevention film. Further, the semiconductor device 700 is different from the semiconductor device 100 shown in FIG. The semiconductor device 700 is substantially in common with the semiconductor device 100 shown in FIG.

  In the semiconductor device 700, the LDD portion 712a includes a shallow portion 712a1 formed near the surface of the silicon substrate 702 and a deep portion 712a2 formed below the shallow portion 712a1. The LDD portion 714a includes a shallow portion 714a1 formed near the surface of the silicon substrate 702 and a deep portion 714a2 formed under the shallow portion 714a1.

  Next, a manufacturing method 750 according to the present embodiment applicable to the semiconductor device 700 will be described with reference to FIGS. As shown in FIG. 20, the manufacturing method 750 includes at least steps S61 to S67. In the manufacturing method 750, steps S61 to S67 are performed in this order.

  In the manufacturing method 750, steps S61, S62, and S64 to S67 are substantially the same as the corresponding steps of the manufacturing method 150 according to the first embodiment shown in FIG. Here, step S61 corresponds to step S1, step S62 corresponds to step S2, step S64 corresponds to step S5, step S65 corresponds to step S6, step S66 corresponds to step S7, and step S67. Corresponds to step S8.

  In the manufacturing method 750, in step S63, the LDD portion 712 is formed by two ion implantations having different implantation energies. In step S63, shallow portions 712a1 and 714a1 are formed in the first ion implantation, for example, as shown in FIG. 21A, and deep portions 712a2 are formed in the second ion implantation, for example, as shown in FIG. 21B. , 714a2 are formed.

  In the present embodiment, in the first ion implantation, for example, phosphorus is used as an impurity, and the implantation energy can be set to about 20 KeV. In the second ion implantation, for example, phosphorus is used as an impurity, and the implantation energy can be set to about 70 KeV.

  As a result, the LDD portions 712a and 714a according to this embodiment have an impurity profile in the depth direction as shown in FIG. FIG. 22 also shows an impurity profile of a general LDD portion formed by one ion implantation for comparison with the LDD portions 712a and 714a.

  As shown in FIG. 22, the LDD parts 712a and 714a have deeper impurity concentration peaks than the general LDD part. Therefore, in the present embodiment, the hot carrier generation position moves to a deep part of the semiconductor substrate as compared with a configuration having a general LDD part.

  The manufacturing method 750 according to the present embodiment includes, in addition to steps S61 to S67, a first buried wiring forming step, a second contact hole forming step, a second buried wiring forming step, and other steps. However, detailed explanations thereof are omitted.

  As described above, according to the present embodiment, the electric field concentration in the vicinity of the hot carrier generation position is alleviated by forming the LDD portion by two ion implantations. Therefore, the generation probability of hot carriers is lowered and the generation position of hot carriers becomes deeper than usual.

  Therefore, in the present embodiment, the number of hot carriers reaching the silicon / silicon nitride interface formed near the silicon substrate surface is reduced, and the probability of hot carrier trapping at the silicon / silicon nitride interface is reduced. As a result, according to the present embodiment, the hot carrier resistance of the MOSFET can be improved.

  Furthermore, in this embodiment, one of the two ion implantations can keep the implantation energy low. Therefore, according to the present embodiment, hot carrier resistance can be improved while maintaining the current characteristics of the MOSFET.

  The preferred embodiment according to the present invention has been described above, but the present invention is not limited to such a configuration. A person skilled in the art can assume various modifications and changes within the scope of the technical idea described in the claims, and these modifications and changes are also within the technical scope of the present invention. It is understood that it will be included.

  For example, in the above embodiment, the semiconductor device including the gate insulating film made of silicon oxide and the method for manufacturing the semiconductor device have been described, but the present invention is not limited to such a configuration. The present invention can also be applied to a semiconductor device including a gate insulating film made of various other insulating materials such as aluminum oxide and strontium oxide, and a manufacturing method thereof.

  In the above embodiment, the semiconductor device including the oxidation inhibiting film made of silicon oxide and the manufacturing method thereof have been described as examples. However, the present invention is not limited to such a configuration. The present invention can also be applied to a semiconductor device including an oxidation inhibiting film made of various other insulating materials such as aluminum oxide and strontium oxide, and a manufacturing method thereof.

  In the above embodiment, the semiconductor device including the cap film made of silicon nitride and the manufacturing method thereof have been described as examples. However, the present invention is not limited to such a configuration. The present invention can also be applied to a semiconductor device including an oxidation inhibiting film made of various other insulating materials such as aluminum oxide and strontium oxide, and a manufacturing method thereof. In the present invention, the material of the cap film may be an insulating material different from the material of the interlayer insulating film.

  In the above embodiment, the semiconductor device including the gate electrode made of polysilicon doped with the predetermined impurity and the manufacturing method thereof have been described as examples. However, the present invention is not limited to such a configuration. The present invention relates to a semiconductor device including a gate electrode composed of various other conductive materials, for example, silicon doped with a predetermined impurity, polycrystalline silicon, metal silicide, metal, or a laminate thereof, and a method of manufacturing the same. It can also be applied to.

  In the above embodiment, the semiconductor device including the interlayer insulating film made of silicon oxide and the manufacturing method thereof have been described as examples, but the present invention is not limited to such a configuration. The present invention can also be applied to a semiconductor device including an interlayer insulating film made of various other insulating materials and a method for manufacturing the same. Note that the interlayer insulating film is preferably made of a material having an etching rate different from that of the sidewall.

  In the above embodiment, the semiconductor device using a silicon substrate as a semiconductor substrate and the manufacturing method thereof have been described as examples. However, the present invention is not limited to such a configuration. The present invention can also be applied to a semiconductor device to which various other semiconductor substrates, for example, a gallium arsenide (GaAs) substrate and other semiconductor substrates are applied, and a manufacturing method thereof.

  In the above-described embodiment, the semiconductor device including the FET having the LDD structure and the manufacturing method thereof have been described as examples. However, the present invention is not limited to such a configuration. The present invention can also be applied to a semiconductor device including an FET having no LDD structure and a manufacturing method thereof.

  In the above embodiment, the semiconductor device in which the contact hole by the SAC technique is formed on both the source region 112 and the drain region and the manufacturing method thereof are described as examples. However, the present invention is not limited to such a configuration. The present invention provides various other configurations, for example, a semiconductor device having a configuration in which a contact hole by SAC technology is formed only on the drain region, or a configuration in which a contact hole by SAC technology is formed only on the source region, and the like The present invention can also be applied to the manufacturing method.

  In the above embodiment, the insulated gate FET has been described as an example, but the present invention is not limited to such a configuration. The present invention can also be applied to various other FETs such as a junction gate type FET and a Schottky barrier type FET.

  The present invention provides various semiconductor devices including FETs and manufacturing methods thereof, for example, amplifier circuits including FETs, high-frequency circuits including FETs, low-frequency circuits including FETs, digital circuits including FETs, analog circuits including FETs, or The present invention can be applied to a circuit combining them. The present invention is effective when applied to a semiconductor device having a high degree of integration in which it is difficult to secure an alignment margin between a gate electrode such as an LSI and a contact hole, and a manufacturing method thereof.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  The present invention is applicable to a semiconductor device and a semiconductor device manufacturing method.

It is a schematic sectional drawing for demonstrating the principal part structure of the semiconductor device which can apply invention. 6 is a schematic flowchart for explaining a method of manufacturing a semiconductor device to which the present invention is applicable. FIG. 3 is a schematic cross-sectional view for supplementing the explanation according to FIG. 2. It is a schematic sectional drawing for demonstrating the principal part structure of the other semiconductor device which can apply this invention. It is a schematic flowchart for demonstrating the manufacturing method of the other semiconductor device which can apply this invention. FIG. 6 is a schematic cross-sectional view for supplementing the explanation according to FIG. 5. It is a schematic sectional drawing for demonstrating the principal part structure of the other semiconductor device which can apply this invention. It is a schematic flowchart for demonstrating the manufacturing method of the other semiconductor device which can apply this invention. FIG. 9 is a schematic cross-sectional view for supplementing the explanation according to FIG. 8. It is a schematic sectional drawing for demonstrating the principal part structure of the other semiconductor device which can apply this invention. It is a schematic flowchart for demonstrating the manufacturing method of the other semiconductor device which can apply this invention. FIG. 12 is a schematic cross-sectional view for supplementing the explanation according to FIG. 11. It is a schematic sectional drawing for demonstrating the principal part structure of the other semiconductor device which can apply this invention. It is a schematic flowchart for demonstrating the manufacturing method of the other semiconductor device which can apply this invention. It is a schematic sectional drawing for supplementing description by FIG. It is a schematic sectional drawing for demonstrating the principal part structure of the other semiconductor device which can apply this invention. It is a schematic flowchart for demonstrating the manufacturing method of the other semiconductor device which can apply this invention. FIG. 18 is a schematic cross-sectional view for supplementing the description according to FIG. 17. It is a schematic sectional drawing for demonstrating the principal part structure of the other semiconductor device which can apply this invention. It is a schematic flowchart for demonstrating the manufacturing method of the other semiconductor device which can apply this invention. It is a schematic sectional drawing for supplementing description by FIG. FIG. 20 is a schematic diagram showing an impurity profile of an LDD portion of the semiconductor device shown in FIG. 19. It is a schematic sectional drawing for demonstrating the conventional semiconductor device.

Explanation of symbols

100 Semiconductor device 110 MOSFET
102 Silicon substrate 104 Interlayer insulating film 116 Gate electrode 122 Side wall 522 Side wall 622 Side wall 124 Gate oxide film 126 Diffusion suppression film 712a LDD part 714a LDD part

Claims (6)

A semiconductor device comprising a semiconductor substrate and an FET formed on the semiconductor substrate:
A side wall for SAC, which is formed on the side of the gate electrode of the FET and mainly contains nitrogen and silicon in the composition and is formed by LP-CVD (Low Pressure CVD) at 850 ° C. or higher, Semiconductor device. A semiconductor device comprising a semiconductor substrate and an FET formed on the semiconductor substrate:
A sidewall for the SAC formed on the side of the gate electrode of the FET and mainly containing nitrogen and silicon in the composition;
The sidewall is composed of two or more layers, and the lowermost layer is formed by LP-CVD at 850 ° C. or higher;
A semiconductor device characterized by that. A semiconductor device comprising a semiconductor substrate and an LDD-structured FET formed on the semiconductor substrate:
The semiconductor device according to claim 1, wherein the LDD portion of the FET is formed by ion implantation of two or more times having different implantation energies. A method of manufacturing a semiconductor device comprising a semiconductor substrate and an FET formed on the semiconductor substrate, comprising:
Forming a film mainly containing nitrogen and silicon in the composition by LP-CVD at 850 ° C. or higher and covering the upper and side surfaces of the gate electrode of the FET;
Forming a sidewall for SAC mainly containing nitrogen and silicon in the composition by etching back the film by RIE on the side of the gate electrode;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device comprising a semiconductor substrate and an FET formed on the semiconductor substrate, comprising:
Forming a first film mainly containing nitrogen and silicon in the composition by LP-CVD at 850 ° C. or higher and covering the upper and side surfaces of the gate electrode of the FET;
Forming a second film mainly containing nitrogen and silicon in the composition on the first film;
Forming a sidewall for SAC mainly containing nitrogen and silicon in the composition by etching back the first and second films by RIE on the side of the gate electrode;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device comprising a semiconductor substrate and an LDD-structured FET formed on the semiconductor substrate:
The method of manufacturing a semiconductor device, wherein the LDD portion of the FET is formed by two or more ion implantations having mutually different implantation energies.

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