JP2014099551A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which improves device characteristics of a first region by diffusing hydrogen atoms in the first region and which prevents deterioration of device characteristics in a second region by preventing diffusion of excessive hydrogen atoms in the second region.SOLUTION: A semiconductor device comprises: a semiconductor substrate 1 including a first region and a second region; a hydrogen diffusion prevention film 45 which is provided on the first and second regions and has a first opening in the first region; a conductive layer 32b buried in the first opening; an information storage element 48 electrically connected with the conductive layer 32b; a hydrogen supply film 27 which covers the information storage element 48 in the first region and contacts the hydrogen diffusion prevention film 45 in the second region to cover the hydrogen diffusion prevention film 45; and a second opening which is opened through both of the hydrogen supply layer 27 and the hydrogen diffusion prevention film 45 in the second region.

Description

The present invention relates to a semiconductor device and a manufacturing method thereof.

In a DRAM memory cell, hydrogen annealing is performed as an effective process for improving refresh characteristics. In this hydrogen annealing, it is necessary to supply more hydrogen near the surface of the semiconductor substrate in the memory cell region than in the transistor located in the peripheral circuit region.
On the other hand, in a semiconductor substrate having a high-aspect ratio capacitive element and multilayer metal wiring, a sufficient amount of hydrogen necessary for improving the characteristics is supplied to the element formed on the semiconductor substrate by heat treatment in a hydrogen atmosphere. It is difficult.
Therefore, a method of using a film formed by a plasma CVD method containing hydrogen has been proposed. For example, a silicon nitride film formed by a plasma CVD method contains 20 atm% or more of hydrogen, and its composition includes SiN _x H _y (x is about 0.8 to 1.2) and a large amount of N—H bonds. It is. Therefore, the silicon nitride film releases hydrogen by performing heat treatment after the silicon nitride film is formed. Further, during the formation of the silicon nitride film, a large amount of hydrogen generated by the film formation reaction passes through the SiN _x H _y and is supplied to the semiconductor substrate side.

  Patent Document 1 (Japanese Patent Laid-Open No. 6-112453) discloses a phenomenon in which a nitrogen-rich film formed by a plasma CVD method desorbs hydrogen by annealing and terminates dangling bonds on the surface of a semiconductor substrate. ing.

  In Patent Document 2 (Japanese Patent Laid-Open No. 2009-188068), regarding a passivation film formed by a plasma CVD method serving as a hydrogen supply source in a solid-state imaging device, different residuals are present in a pixel portion provided with a light receiving portion and a peripheral circuit portion. A technique for setting the amount of hydrogen is disclosed.

JP-A-6-112453 JP 2009-188068 A

  However, in the method of Patent Document 2, it is necessary to etch and remove a film having a large residual hydrogen amount once, even in a region where the necessary residual hydrogen amount is small. Therefore, when a film having a large amount of residual hydrogen is formed, a certain amount of hydrogen is supplied to the entire area of the semiconductor substrate, and the hydrogen supply amount cannot be controlled for each region.

As a result, the characteristics of the element located in the region where the required amount of residual hydrogen is small are deteriorated. For example, a required amount of hydrogen is small in a region where a transistor is present in a peripheral circuit region of a DRAM. For this reason, if excessive hydrogen annealing is performed in this region, this transistor is used in a BTI (Bias-Temperature Instability) test for measuring the amount of variation in V _t (threshold voltage) before and after applying voltage stress at a high temperature. This is a factor that increases the fluctuation amount of V _t (threshold voltage). The reason for this is thought to be that excessive amounts of (or unstable) Si—H bonds are formed, which increases the amount of hydrogen desorbed while applying voltage stress at high temperatures. ing.

  1, 13 and 14 are diagrams for explaining this phenomenon in detail. 1A and 1B are plan views showing a memory cell region and a peripheral circuit region of a conventional DRAM, respectively, showing only a main structure and omitting a part of the structure. FIGS. 13 and 14 respectively show a part of a cross section corresponding to the B-B ′ direction in FIG. 1A and a cross section corresponding to the A-A ′ direction in FIG. 1B. 13 and 14, the left side of the dotted line represents the memory cell region, and the right side of the dotted line represents the peripheral circuit region.

  First, the structure shown in FIGS. 1 and 13 is formed. As shown in the left region of FIGS. 1A and 13, a plurality of element isolation regions (STI) 2 and active regions 1a are alternately formed at predetermined intervals in the Y direction in the memory cell region of the DRAM. In addition, the embedded gate electrode 30 and the dummy word line 30 ′ serving as word lines extend in the Y direction and are embedded in the semiconductor substrate 1 at predetermined intervals in the X direction so as to cut the active region 1a vertically. Is formed. Further, a plurality of bit lines 31 are arranged at predetermined intervals in the X direction orthogonal to the word lines 30 and the dummy word lines 30 '. Memory cells are formed in regions where the word line 30 and the active region 1a intersect.

  The memory cell includes a third transistor Tr3 and a capacitor 48. Each capacitive element 48 is electrically connected to the capacitive contact region 32a of each third transistor Tr3 via a capacitive contact plug 32b. Each memory cell is connected to the bit line 31 via the bit contact region 33. Each capacitive element 48 includes a capacitor insulating film 48b, a polysilicon film 48c as an upper electrode (plate electrode), and a tungsten film 48d laminated in this order on the inner wall surface and outer wall surface of the lower electrode 48a. ing. A plate mask film 18 is provided so as to cover the tungsten film 48d, and a contact plug 23 is provided so as to penetrate the plate mask film 18.

  As shown in the region on the right side of FIGS. 1B and 13, the peripheral circuit region is provided with a region Cn where an NMOS is formed and a region Cp where a PMOS is formed. The regions Cn and Cp are arranged so as to sandwich the element isolation region (STI) 2 therebetween. In each of the regions Cn and Cp, an active region 1a in which the surface of the semiconductor substrate 1 is exposed is disposed, and the first gate electrode 17a and the second gate insulating film 9b are interposed through the first gate insulating film 9a. The second gate electrodes 17b are provided so as to divide the active region 1a into two. A P well 3 and an N well 4 are provided in the active regions 1a of the regions Cn and Cp, respectively. In the region Cn, the LD well region 19a and the first source and drain 21a are provided in the P well 3 on both sides of the first gate electrode 17a. The first gate insulating film 9a, the first gate electrode 17a, the LDD region 19a, and the first source and drain 21a constitute an N-channel first transistor Tr1. In the region Cp, an LDD region 19b and a second source and drain 21b are provided in the N well 4 on both sides of the second gate electrode 17b. The second gate insulating film 9b, the second gate electrode 17b, the LDD region 19b, and the first source and drain 21b constitute a P-channel type second transistor Tr2. The first source and drain 21a and the second source and drain 21b are connected to contact plugs 24a and 24b, respectively. The contact plugs 24a and 24b are connected to the wiring layers 24c and 24d, respectively. One of the wiring layers 24c and 24d is connected to the through-hole plugs 24e and 24f, respectively.

  Next, as shown in FIG. 14, aluminum wirings 24g, 24h and 24i are formed so as to be connected to the contact plug 23 in the memory cell region and the through-hole plugs 24e and 24f in the peripheral circuit region, respectively. Thereby, the DRAM is completed.

Conventionally, hydrogen annealing is performed after the structure shown in FIGS. 1 and 13 is formed. By this hydrogen annealing, hydrogen atoms diffuse into the semiconductor substrate 1 through the openings for the contact plug 23 and the capacitor contact plug 32b in the memory cell region. Further, in the peripheral circuit region, hydrogen atoms enter the semiconductor substrate 1 through the openings for the through-hole plugs 24e and 24f, the wiring grooves for the wiring layers 24c and 24d, and the openings for the contact plugs 24a and 24b. To spread. However, in the conventional hydrogen annealing, the same amount of hydrogen is supplied to the transistors in the memory cell region and the peripheral circuit region. Therefore, when a large amount of hydrogen necessary and sufficient for improving the refresh characteristics of the memory cell region is supplied, hydrogen is excessively supplied in the peripheral circuit region, and an unstable Si—H bond is formed. As a result, during a long time operation, hydrogen is gradually desorbed from the transistors in the peripheral circuit region, and the V _t (threshold voltage) of the transistors in the peripheral circuit region fluctuates, resulting in a malfunction of the circuit operation. There was a problem.

One embodiment is:
A semiconductor substrate including a first region and a second region;
A hydrogen diffusion prevention film provided in the first and second regions and provided with a first opening in the first region;
A conductive layer embedded in the first opening;
An information storage element electrically connected to the conductive layer;
A hydrogen supply film covering the information storage element in the first region and covering the hydrogen diffusion prevention film in contact with the hydrogen diffusion prevention film in the second region;
A second opening opened through both the hydrogen supply film and the hydrogen diffusion prevention film in the second region;
It is related with the semiconductor device characterized by comprising.

Other embodiments are:
Forming a first element in a first region on a semiconductor substrate;
Forming a second element in a second region on the semiconductor substrate;
Forming a hydrogen diffusion prevention film covering both the first region and the second region;
Forming a first opening in the hydrogen diffusion prevention film above the first element;
Forming a hydrogen supply film that covers both the first opening and the hydrogen diffusion prevention film;
Performing a heat treatment for diffusing hydrogen from the hydrogen supply film;
Forming a second opening penetrating both the hydrogen supply film and the hydrogen diffusion prevention film above the second element;
Performing a heat treatment in an atmosphere containing hydrogen;
The present invention relates to a method for manufacturing a semiconductor device.

  The device characteristics of the first region are improved by diffusing hydrogen atoms in the first region, and the device properties of the second region are deteriorated by preventing excessive diffusion of hydrogen atoms to the second region. Can be prevented.

It is a top view showing the semiconductor device of a prior art and 1st Example. It is sectional drawing showing the semiconductor device of 1st Example. It is sectional drawing showing the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing the manufacturing method of the semiconductor device of 2nd Example. It is sectional drawing showing the manufacturing method of the semiconductor device of a prior art. It is sectional drawing showing the semiconductor device of a prior art.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. This embodiment is a specific example shown for a deeper understanding of the present invention, and the present invention is not limited to this specific example. Moreover, the same code | symbol is attached | subjected to the same member and description is abbreviate | omitted or simplified. Further, the same members will be appropriately omitted. The drawings used in the following description are schematic, and the ratios of length, width, and thickness in each drawing are not necessarily the same as the actual ones, and the length, width, and thickness in each drawing are not the same. The ratios may not match each other. In the following examples, the concretely shown conditions such as materials and dimensions are merely examples.

In the following embodiments, “first region” and “second region” described in the claims correspond to a memory cell region and a peripheral circuit region, respectively.
The “first opening” and the “second opening” recited in the claims correspond to a capacitor contact hole in the memory cell region and a through hole in the peripheral circuit region, respectively.
The “hydrogen diffusion prevention film” and the “hydrogen supply film” described in the claims correspond to the stopper film (silicon nitride film) 45 and the silicon nitride film 27, respectively.
The “conductive film” and the “information storage element” recited in the claims correspond to the capacitive contact plug 32 b and the capacitive element 48, respectively.
The “first element” recited in the claims corresponds to the third transistor Tr3, and the “second element” corresponds to the first and second transistors Tr1 and Tr2.

(First Example)
1. Semiconductor Device This embodiment relates to a DRAM (Dynamic Random Access Memory) which is a semiconductor device to which the structure of the present invention is applied.

  1 and 2 are diagrams showing a semiconductor device of this embodiment. 1A is a plan view of a memory cell region, and FIG. 1B is a plan view of a peripheral circuit region. 1A and 1B show only the main structure, and a part of the structure is omitted. Apparently, in FIGS. 1A and 1B, the prior art and the present embodiment have the same structure, but the structure not shown in FIGS. 1A and 1B differs between the prior art and the present embodiment. 2 is a diagram in which a part of the cross section in the B-B ′ direction in FIG. 1A and the cross section in the A-A ′ direction in FIG. 1B are joined together. In FIG. 2, the left side of the dotted line represents the memory cell region, and the right side of the dotted line represents the peripheral circuit region. The DRAM of this embodiment is composed of a memory cell region shown in FIG. 1A and a peripheral circuit region shown in FIG. 1B, and has a 6F2 cell arrangement (F is the minimum processing size).

(1) Memory cell area (first area)
As shown in FIG. 1A, a plurality of element isolation regions (STI) 2 and active regions 1a are alternately formed at predetermined intervals in the Y direction in the memory cell region of the DRAM. The element isolation region 2 and the active region 1a each extend in the X ′ direction shown in FIG. 1A. In addition, the embedded gate electrode 30 and the dummy word line 30 ′ serving as word lines extend in the Y direction and are embedded in the semiconductor substrate 1 at predetermined intervals in the X direction so as to cut the active region 1a vertically. Is formed. Further, a plurality of bit lines 31 are arranged at predetermined intervals in the X direction orthogonal to the word lines 30 and the dummy word lines 30 ′. Memory cells are formed in regions where the word line 30 and the active region 1a intersect. The memory cell includes a third transistor (first element) Tr3 and a capacitor element (not shown). The third transistor Tr3 includes an active region 1a, a low concentration impurity diffusion layer (not shown), a capacitor contact region 32a and a bit contact region 33 serving as a third source and drain, a word line 30, and a third gate insulating film (not shown). It is composed of

  The word line 30 and the dummy word line 30 'have the same structure but have different functions. The word line 30 is used as the gate electrode of the third transistor Tr3, while the dummy word line 30 'is provided to isolate the adjacent third transistors Tr3 by applying a predetermined potential. That is, the third transistors Tr3 adjacent on the same active region 1a are separated by maintaining the dummy word line 30 'at a predetermined potential so that the parasitic transistors are turned off.

  A plurality of memory cells are formed in the entire memory cell region, and each memory cell is provided with a capacitor element (not shown in FIG. 1A). Each capacitive element is electrically connected to the capacitive contact region 32a of each third transistor Tr3 via a capacitive contact plug (conductive layer) 32b. As shown in FIG. 1A, the capacitor contact plugs 32b are arranged at predetermined intervals in the memory cell region so as not to overlap each other. Each memory cell is connected to the bit line 31 via the bit contact region 33.

  As shown in the region on the left side of the dotted line in FIG. 2A, in the memory cell region, each memory cell is formed of a third transistor Tr3 and a capacitor element (information storage element) 48. The third transistor Tr3 includes an active region 1a, a word line 30 including a buried gate electrode embedded in the semiconductor substrate 1, and a third gate insulating film 37 provided between the semiconductor substrate 1 and the word line 30. The low-concentration impurity diffusion layer 10 and a capacitor contact region 32 a and a bit contact region 33 provided on the main surface of the semiconductor substrate 1 and serving as a third source and drain. A low-concentration impurity diffusion layer 10 is further provided below the capacitor contact region 32 a and the bit contact region 33. The word line 30 includes, for example, a barrier metal film 30a made of a titanium nitride film and a metal gate film 30b made of a tungsten film. The upper surface of the word line 30 is formed to be lower than the upper surface of the semiconductor substrate 1. On the word line 30, a liner film 38a made of a silicon nitride film and an SOD (Spin on Dielectric) film 38b are provided.

  A bit-con interlayer insulating film 39 made of a silicon nitride film is provided on the semiconductor substrate 1 in the memory cell region. The bit contact interlayer insulating film 39 on the bit contact region 33 is opened, and the bit line 31 is provided so as to be in contact with the bit contact region 33. The bit line 31 includes a polysilicon film 11c containing impurities and a laminated film 12c of tungsten film in order from the side closer to the semiconductor substrate 1. A hard mask 15 made of a silicon nitride film is provided on the bit line 31. A liner film 43 made of a silicon nitride film is provided on both side surfaces of the bit line 31 and on the upper surface of the bit-con interlayer insulating film 39. An SOD film (interlayer insulating film) 22 is provided on the liner film 43. A stopper film (hydrogen diffusion preventing film) 45 made of a silicon nitride film is provided on the SOD film 22. This stopper film 45 prevents hydrogen from diffusing into elements and the like located under the stopper film 45 in the hydrogen annealing step.

  A capacitor contact plug 32b is provided so as to penetrate through the stopper film 45, the SOD film 22, the liner film 43, and the bit contact interlayer insulating film 39 and to be connected to the capacitor contact region 32a. A capacitive element 48 is provided so as to be electrically connected to the capacitive contact plug 32b. The capacitive element 48 is electrically connected to the capacitive contact region 32a via the capacitive contact plug 32b. The capacitive element 48 is a crown-type capacitive element in which a capacitive insulating film 48b and an upper electrode (plate electrode) are laminated in this order on the inner wall surface and the outer wall surface of the lower electrode 48a. The upper electrode (plate electrode) is composed of a polysilicon film 48c containing impurities and a tungsten film 48d formed thereon. In the memory cell region, a silicon nitride film (hydrogen supply film) 27 is provided so as to cover the capacitor element 48 in contact with the tungsten film 48d. The silicon nitride film (hydrogen supply film) 27 is provided on the tungsten film 48d in the memory cell region, but covers the stopper film 45 in contact with the stopper film 45 in the peripheral circuit region as will be described later. It is provided as follows. The silicon nitride film (hydrogen supply film) 27 serves as a supply source for supplying hydrogen by hydrogen annealing (heat treatment). An interlayer insulating film 28 made of a silicon oxide film is further provided on the silicon nitride film (hydrogen supply film) 27. In the memory cell region, a contact plug 23 is provided so as to penetrate the interlayer insulating film 28 and the silicon nitride film 27 and be connected to the tungsten film 48d. The contact plug 23 is further connected to an aluminum wiring 24g provided on the interlayer insulating film 28.

(2) Peripheral circuit area (second area)
As shown in FIG. 1B, in the peripheral circuit region, a region Cn where NMOS is formed and a region Cp where PMOS is formed are provided. The regions Cn and Cp are arranged so as to sandwich the element isolation region (STI) 2 therebetween. In each of the regions Cn and Cp, an active region 1a where the surface of the semiconductor substrate 1 is exposed is disposed, and a first gate electrode 17a and a second gate electrode 17b are provided so as to divide the active region 1a into two. Yes. A P well 3 and an N well 4 are provided in the active regions 1a of the regions Cn and Cp, respectively. In the P well 3 on both sides of the first gate electrode 17a in the region Cn, an LDD region into which a low concentration impurity is introduced and a first source and drain 21a into which a high concentration impurity is introduced are provided. It has been. In the region Cp, in the N well 4 on both sides of the second gate electrode 17b, an LDD region into which a low concentration impurity (not shown) is introduced and a second source and drain 21b into which a high concentration impurity is introduced are provided. It has been. The active region 1a, the first gate electrode 17a, the LDD region (not shown), the first source and drain 21a, and the first gate insulating film (not shown) formed on the region Cn are the first in the peripheral circuit region. A transistor (second element) Tr1 is formed. Similarly, the active region 1a, the second gate electrode 17b, the LDD region (not shown), the second source and drain 21b, and the second gate insulating film (not shown) formed on the region Cp are formed in the peripheral circuit region. A second transistor (second element) Tr2 is formed. The first source and drain 21a and the second source and drain 21b are connected to contact plugs 24a and 24b, respectively. The contact plugs 24a and 24b are connected to the wiring layers 24c and 24d, respectively. One of the wiring layers 24c and 24d is connected to a through-hole plug (not shown) via each.

  As shown in the region on the right side of FIG. 2, the peripheral circuit region of the semiconductor device of this embodiment has a P well 3 and an N well 4. An element isolation region 2 is provided between the P well 3 and the N well 4, and the P well 3 and the N well 4 are insulated and separated. The element isolation region 2 is composed of a laminated film of a silicon oxide film 2b and a silicon nitride film 2a. On the P-well 3, a silicon oxide film 5a and a hafnium oxide film 6a as a first gate insulating film 9a are provided in this order. A first gate electrode 17a made of a titanium nitride film 7a, a polysilicon film 11a containing impurities, and a tungsten film 12a is provided on the first gate insulating film 9a. On the N well 4, a silicon oxide film 5b and an aluminum oxide film 6b as a second gate insulating film 9b are provided in this order. A second gate electrode 17b made of a titanium nitride film 7b, a polysilicon film 11b containing impurities, and a tungsten film 12b is provided on the second gate insulating film 9b. A hard mask 15 made of a silicon nitride film is provided on each of the first and second gate electrodes 17a and 17b. Offset spacers 26a and sidewall spacers 26b are provided on both side surfaces of the first and second gate electrodes 17a and 17b. A liner film 43 is further provided so as to cover the offset spacers 26 a and the sidewall spacers 26 b and the semiconductor substrate 1.

  An N-type conductivity type LDD region 19 a and an N-type conductivity type first source and drain 21 a are formed on both sides of the first gate electrode 17 a in the P well 3. A P-type conductivity type LDD region 19b, and a P-type conductivity type second source and drain 21b are formed on both sides of the N well 4 with the second gate electrode 17b interposed therebetween. The P well 3, the first gate insulating film 9a, the first gate electrode 17a, the N-type conductivity type LDD region 19a, and the first source and drain 21a are NMOS (N-channel type) which is the first transistor Tr1. Transistor). The N well 4, the second gate insulating film 9b, the second gate electrode 17b, the P-type conductivity type LDD region 19b, and the second source and drain 21b are the PMOS (P channel) which is the second transistor Tr2. Type transistor).

  An SOD film (interlayer insulating film) 22 is provided on the semiconductor substrate 1 in the peripheral circuit region. A contact plug 24a and a wiring layer 24c are provided so as to penetrate the SOD film 22 and be connected to the first source and drain 21a. Similarly, a contact plug 24b and a wiring layer 24d are provided so as to penetrate the SOD film 22 and be connected to the second source and drain 21b. On the SOD film 22, a stopper film (hydrogen diffusion prevention film) 45, a silicon nitride film (hydrogen supply film) 27, and a silicon nitride film (hydrogen supply film) 27 so as to be in contact with and cover the stopper film 45 An interlayer insulating film 28 is provided on the substrate. Through-hole plugs 24e and 24f are provided through the interlayer insulating film 28, the silicon nitride film 27, and the stopper film 45 so as to be connected to one of the wiring layers 24c and 24d, respectively. The through hole plugs 24e and 24f are formed by burying a conductive material such as tungsten in a through hole (second opening) that penetrates the stopper film 45 and the interlayer insulating film 28. Through-hole plugs 24e and 24f are connected to aluminum wiring layers 24h and 24i provided on interlayer insulating film 28, respectively.

In the semiconductor device of this embodiment, the silicon nitride film is formed by heat (heat treatment for diffusing hydrogen from the hydrogen supply film) during the formation of the silicon nitride film (hydrogen supply film) 27 and during the formation of an interlayer insulating film 28 described later. The (hydrogen supply film) 27 releases a large amount of hydrogen. A large amount of the released hydrogen passes through the capacitor contact hole (first opening) opened in the stopper film (hydrogen diffusion preventing film) 45 in the memory cell region to the third transistor Tr3 on the semiconductor substrate 1. To spread. Accordingly, in the memory cell region, a sufficient amount of hydrogen atoms can be diffused into the semiconductor substrate 1 in the memory cell region through the capacitor contact hole. As a result, the refresh characteristics of the memory cell region can be effectively improved.
On the other hand, as will be described later, in the peripheral circuit region, a stopper film (hydrogen diffusion prevention film) having a very small hydrogen diffusion coefficient as a whole during the formation of the silicon nitride film (hydrogen supply film) 27 and the interlayer insulating film 28. 45. For this reason, hydrogen atoms do not diffuse to the first and second transistors Tr1 and Tr2 on the semiconductor substrate 1. As a result, V _t (threshold voltage) of the first and second transistors Tr1 and Tr2 can be prevented from fluctuating to cause a malfunction of the circuit operation.

2. Semiconductor Device Manufacturing Method A semiconductor device manufacturing method of this embodiment will be described below with reference to FIGS. 2 to 11 are diagrams in which a cross section corresponding to the BB ′ direction of the memory cell region of FIG. 1A and a cross section corresponding to the AA ′ direction of the peripheral circuit region of FIG. 1B are connected. . 2 to 11, the area on the left side of the dotted line represents the memory cell area, and the area on the right side of the dotted line represents the peripheral circuit area.
First, as shown in FIG. 3, an element isolation region (STI) 2 composed of a laminated film of a silicon oxide film 2b and a silicon nitride film 2a is formed in a memory cell region and a peripheral circuit region in the semiconductor substrate 1. As a result, the active region 1a defined by the element isolation region 2 is defined in the memory cell region and the peripheral circuit region. Further, the P well 3 and the N well 4 are formed in the active region 1a of the peripheral circuit region by a known method. A low concentration impurity is implanted into the semiconductor substrate 1 in the memory cell region to form a low concentration impurity diffusion layer 10. Subsequently, a silicon oxide film 51 is formed by thermally oxidizing the main surface of the semiconductor substrate 1, and a silicon nitride film 52 is formed on the silicon oxide film 51. A hard mask pattern is provided by patterning the silicon oxide film 51 and the silicon nitride film 52 on the memory cell region. A groove-like trench 55 extending in a direction intersecting the element isolation region 2 is formed in the semiconductor substrate 1 in the memory cell region by etching using the hard mask pattern. By the formation of the trench 55, the previously formed low concentration impurity diffusion layer 10 is divided.

  As shown in FIG. 4, the inner wall of the trench 55 is oxidized by an ISSG (in-situ steam generation) method to form a third gate insulating film 37 made of a silicon oxide film.

As shown in FIG. 5, a barrier film 30 a such as a titanium nitride film is formed on the inner wall of the trench 55. The trench 55 is filled with a metal gate film 30b such as a tungsten film. By etching back, the upper surfaces of the barrier film 30 a and the metal gate film 30 b are made to recede from the main surface of the semiconductor substrate 1 to form the word line (buried gate electrode) 30. At this time, the barrier film 30a and the metal gate film 30b in the peripheral circuit region are removed.
As shown in FIG. 6, after a liner film 38 a made of a silicon nitride film is formed on the entire surface of the semiconductor substrate 1, an SOD film 38 b is further formed on the entire surface of the semiconductor substrate 1. Thereafter, CMP processing is performed on the SOD film 38b until the upper surface of the liner film 38a is exposed.
As shown in FIG. 7, the upper portions of the liner film 38a and the SOD film 38b are removed by dry etching. Next, the silicon nitride film 52 is removed by wet etching. Next, a bit capacitor interlayer insulating film 39 made of a silicon nitride film is formed on the entire surface of the semiconductor substrate 1.

  As shown in FIG. 8, a part of the bit-con interlayer insulating film 39 is removed by using a photolithography method and an etching method. The exposed silicon oxide film 51 is removed to expose the semiconductor substrate 1 in the memory cell region. At this time, the silicon oxide film 51 on the peripheral circuit region is also removed. By implanting a high concentration impurity into the exposed low concentration impurity diffusion layer 10 of the semiconductor substrate, a bit contact region 33 serving as one of the third source and drain is formed.

  Next, the surfaces of P well 3 and N well 4 in the peripheral circuit region are thermally oxidized to form silicon oxides 5a and 5b on the surfaces of P well 3 and N well 4, respectively. A hafnium oxide film 6a is formed on the entire surface of the semiconductor substrate 1 by CVD. Thereafter, a titanium nitride film 7a and a first silicon oxide film (not shown) are formed on the entire surface of the semiconductor substrate 1. The first silicon oxide film is patterned to form a hard mask made of the first silicon oxide film so as to cover the P well 3. Using this hard mask, the titanium nitride film 7a is dry etched.

  Next, an aluminum oxide film 6b is formed on the entire surface of the semiconductor substrate 1 by a CVD method. Thereafter, a titanium nitride film 7b and a second silicon oxide film (not shown) are formed on the entire surface of the semiconductor substrate 1. Using a lithography technique and a dry etching technique, the second silicon oxide film is patterned to form a hard mask made of the second silicon oxide film so as to cover the N well 4. Using this hard mask, the titanium nitride film 7b and the aluminum oxide film 6b are dry-etched. Subsequently, the exposed hafnium oxide film 6a is removed by wet etching.

  Next, the first and second silicon oxide films are removed. After a polysilicon film containing impurities is formed on the entire surface of the semiconductor substrate 1 by CVD, a tungsten film is formed on the polysilicon film by sputtering. Thereafter, a silicon nitride film 15 is formed on the tungsten film by a CVD method. The silicon nitride film 15 is patterned using a lithography technique and a dry etching technique. Thus, hard masks made of the silicon nitride film 15 are formed on the P well 3 and N well 4 in the peripheral circuit region and the bit contact region 33 in the memory cell region, respectively.

  Next, the laminated film of the peripheral circuit region and the memory cell region is etched using the hard mask 15. Specifically, in the peripheral circuit region, dry etching of the tungsten film, the polysilicon film, the titanium nitride films 7a and 7b, the hafnium oxide film 6a, the aluminum oxide film 6b, and the silicon oxide films 5a and 5b is performed. Thereby, a silicon oxide film 5a and a hafnium oxide film 6a are formed on the P well 3 as the first gate insulating film 9a, and the first gate having the titanium nitride film 7a, the polysilicon film 11a, and the tungsten film 12a. Electrode 17a is formed. On the N well 4, a silicon oxide film 5b and an aluminum oxide film 6b are formed as a second gate insulating film 9b, and a second gate electrode 17b having a titanium nitride film 7b, a polysilicon film 11b and a tungsten film 12b. Is formed. In the memory cell region, dry etching of the tungsten film and the polysilicon film is performed using the hard mask 15. As a result, the bit line 31 having the polysilicon film 11 c and the tungsten film 12 c is formed on the bit contact region 33.

  As shown in FIG. 9, after a silicon nitride film is formed on the entire surface of the semiconductor substrate 1, the silicon nitride film is etched back to thereby offset the first and second gate electrodes 17a and 17b on both side surfaces. A spacer 26a is formed. An LDD region 19a is formed by implanting an N-type conductivity type impurity into the P well 3 using the hard mask 15 and the offset spacer 26a as a mask. An LDD region 19b is formed by implanting P-type conductivity type impurities into the N well 4 using the hard mask 15 and the offset spacer 26a as a mask.

  Next, after a silicon oxide film is formed on the entire surface of the semiconductor substrate 1, the silicon oxide film is etched back to form sidewall spacers 26b on both side surfaces of the first and second gate electrodes 17a and 17b. Form. By using the hard mask 15, the offset spacer 26a and the side wall spacer 26b as masks, N-type conductivity type impurities are implanted into the P well 3, thereby forming the first source and drain 21a. By using the hard mask 15, the offset spacer 26a and the side wall spacer 26b as a mask, a P-type conductivity type impurity is implanted into the N well 4, thereby forming the second source and drain 21b.

Next, a liner film 43 made of a silicon nitride film is formed on the entire surface of the semiconductor substrate 1 so as to cover the first and second gate electrodes 17a and 17b in the peripheral circuit region and the bit line 31 in the memory cell region. . After forming a coating insulating film on the entire surface of the semiconductor substrate 1, an SOD film 22 is formed by performing an annealing process.
Next, CMP processing of the SOD film 22 is performed to flatten these films. Using the lithography technique and the dry etching technique, contact holes and wiring grooves are formed in the SOD film 22 so as to expose the first source / drain 21a and the second source / drain 21b. Contact plugs 24a and 24b and wiring layers 24c and 24d are formed by embedding a conductive material such as tungsten in the contact hole and the wiring groove.

Next, a stopper film (hydrogen diffusion prevention film) 45 is formed on the SOD film 22 by thermal CVD. Examples of the thermal CVD method may include an LPCVD (Low-Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, or a combination of these methods. This stopper film 45 functions as a hydrogen diffusion preventing film for preventing hydrogen atoms from diffusing to the lower layer of the stopper film during hydrogen annealing described later.
Next, using a lithography technique and a dry etching technique, the capacitor contact hole is formed so as to penetrate the stopper film 45, the SOD film 22, the liner film 43, and the bit-con interlayer insulating film 39 and expose the low-concentration impurity diffusion layer 10. (First opening) is formed. By implanting high-concentration impurities into the exposed low-concentration impurity diffusion layer 10, a capacitor contact region 32a serving as the other of the third source and drain is formed. As a result, the capacitor contact region 32a and the bit contact region 33 serving as the third source and drain, the low-concentration impurity diffusion layer 10, the third gate insulating film 37, and the word line (buried gate electrode) 30 are provided. A transistor Tr3 is formed. A capacitor contact plug (conductive layer) 32b is formed by burying the capacitor contact hole using a conductive material such as tungsten.

As shown in FIG. 10, an interlayer insulating film (not shown) and a support film 35 made of a silicon nitride film are formed on the stopper film 45. After the cylinder hole is formed so that the capacitive contact plug 32b is exposed in the support film 35 and the interlayer insulating film, the lower electrode 48a is formed on the inner wall surface of the cylinder hole. Thereafter, after an opening is formed in the support film 35, the interlayer insulating film in the memory cell region and the peripheral circuit region is removed to expose the outer surface of the lower electrode 48a. A capacitive insulating film 48b is formed on the exposed surface of the lower electrode 48a. Thereafter, a polysilicon film 48c containing impurities is formed on the entire surface of the stopper film 45 so as to cover the lower electrode 48a and the capacitor insulating film 48b, and then the polysilicon film 48c in the peripheral circuit region is removed. A tungsten film 48d is formed so as to cover the polysilicon film 48c in the memory cell region. As a result, a crown-type capacitive element 48 composed of the lower electrode 48a, the capacitive insulating film 48b, and the upper electrodes (plate electrodes) 48c and 48d is completed.
As shown in FIG. 11, a hydrogen supply film 27 made of a silicon nitride film is formed on the entire surface of the semiconductor substrate 1 by plasma CVD. The hydrogen supply film 27 and the stopper film (hydrogen diffusion prevention film) 45 are made of silicon nitride, but the film forming method and composition of these films are different. That is, the hydrogen supply film 27 is formed by a plasma CVD method, and the composition thereof is preferably represented by SiNx having a value x of 0.8 to 1.2. On the other hand, the stopper film (hydrogen diffusion preventing film) 45 is formed by a thermal CVD method (for example, LPCVD method, ALD (Atomic Layer Deposition) method, or a combination of these methods), and its composition is Si _3. Represented by N ₄ . Therefore, the hydrogen supply film 27 supplies hydrogen atoms by annealing, while the stopper film (hydrogen diffusion prevention film) 45 prevents diffusion of hydrogen atoms.
For example, the conditions for forming the hydrogen supply film 27 are preferably those in which SiH ₄ and NH ₃ gas are used at a temperature of 250 to 300 ° C. and the flow rate ratio of NH ₃ is larger. The film formation conditions for the interlayer insulating film 28 include a plasma CVD method using Si (OC ₂ H ₅ ) ₄ and O ₂ at 300 to 400 ° C. The film formation temperature of the interlayer insulating film 28 is more preferably higher than the film formation temperature of the hydrogen supply film 27.

As described above, the hydrogen supply film 27 releases a large amount of hydrogen by heat (heat treatment for diffusing hydrogen from the hydrogen supply film) during the formation of the hydrogen supply film 27 and during the formation of an interlayer insulating film 28 described later. The released hydrogen atoms diffuse in a large amount to the third transistor Tr3 on the semiconductor substrate 1 through the capacitance contact hole (first opening) opened in the hydrogen diffusion preventing film 45 in the memory cell region. . On the other hand, the entire peripheral circuit region is covered with a stopper film (hydrogen diffusion prevention film) 45 having a very small hydrogen diffusion coefficient. Therefore, hydrogen atoms do not diffuse to the first and second transistors Tr1 and Tr2 on the semiconductor substrate 1 and remain in the interlayer insulating film 28. The remaining hydrogen comes out of the interlayer insulating film 28 due to outward diffusion or the like, and finally the residual hydrogen concentration in the interlayer insulating film 28 in the peripheral circuit region decreases. Thus, in this embodiment, a sufficient amount of hydrogen atoms can be diffused into the semiconductor substrate 1 in the memory cell region through the capacitor contact hole. As a result, the refresh characteristics of the memory cell region can be effectively improved. Further, since the entire peripheral circuit region is covered with the stopper film 45 (since there is no opening in the stopper film 45), it is possible to effectively prevent hydrogen atoms from diffusing to the semiconductor substrate 1 through the opening. it can. As a result, V _t (threshold voltage) of the first and second transistors Tr1 and Tr2 can be prevented from fluctuating to cause a malfunction of the circuit operation.

As shown in FIG. 2, a contact hole is formed through the interlayer insulating film 28 to expose the tungsten film 48d in the memory cell region, and through the interlayer insulating film 28, the hydrogen supply film 27, and the support film 45 in the peripheral circuit region. Then, a through hole (second opening) for exposing the wiring layers 24c and 24d is formed. A contact plug 23 and through-hole plugs 24e and 24f are formed by burying the inside of the contact hole and the through-hole using a conductive material such as tungsten. Thereafter, after forming an aluminum film on the interlayer insulating film 28, the aluminum film is patterned to form aluminum wiring layers 24g, 24h, and 24i connected to the contact plug 23 and the through-hole plugs 24e and 24f, respectively. To do.

Next, heat treatment is performed in an atmosphere containing hydrogen. At this time, a through hole (second opening) is opened in the support film 45 in the peripheral circuit region. For this reason, hydrogen can be supplied to the first and second transistors Tr1 and Tr2 on the semiconductor substrate 1 through this opening. At this time, the temperature and time of the hydrogen annealing is such that an appropriate amount of hydrogen is supplied to improve the characteristics of the first and second transistors Tr1 and Tr2 in the peripheral circuit region, and hydrogen has already been supplied in the process of FIG. The setting is such that desorption of hydrogen is not activated in the memory cell region in which a bond with hydrogen is formed. Specifically, the temperature of hydrogen annealing can be 400 to 450 ° C., and the time can be 30 to 60 minutes.

(Second embodiment)
In the first embodiment, the silicon nitride film (hydrogen supply film) 27 is formed in contact with the tungsten film 48d in the memory cell region and in contact with the support film 45 in the peripheral circuit region. On the other hand, the present embodiment is different in that the hydrogen supply film 27 is formed on the interlayer insulating film 28 in the memory cell region and the peripheral circuit region. In this embodiment, a silicon oxide film (plate mask film) 36 is formed instead of the silicon nitride film (hydrogen supply film) 27 in the step of FIG. A DRAM can be manufactured in the same manner as in the first embodiment except that the film (hydrogen supply film) 27 is formed. For this reason, below, it demonstrates centering on the process different from the process of FIG. 11 of 1st Example.

  FIG. 12 is a diagram illustrating a process in the middle of manufacturing the semiconductor device according to the present embodiment. The cross section corresponding to the BB ′ direction of the memory cell region in FIG. 1A and the AA in the peripheral circuit region in FIG. 'Represents a diagram in which cross sections corresponding to directions are connected. In FIG. 12, the area on the left side of the dotted line represents the memory cell area, and the area on the right side of the dotted line represents the peripheral circuit area.

In the process of FIG. 12, the support film 45 and the underlying structure are formed in the memory cell region and the peripheral circuit region. Thereafter, in the memory cell region, a capacitor contact plug 32b and a capacitor element 48 penetrating the support film 45 and the like are formed. Thereafter, a silicon oxide film (plate mask film) 36 is formed so as to cover the tungsten film 48 d of the capacitor element 48. Next, after an interlayer insulating film 28 is formed on the entire surface of the memory cell region and the peripheral circuit region, a silicon nitride film 27 that is a hydrogen supply film is formed on the interlayer insulating film 28. Due to the heat generated when the silicon nitride film 27 is formed, the hydrogen supply film 27 releases a large amount of hydrogen. In the memory cell region, the released hydrogen atoms diffuse in a large amount through the capacitive contact hole (first opening) opened in the hydrogen diffusion preventing film 45 to the third transistor Tr3 on the semiconductor substrate 1. To do. As a result, the refresh characteristics of the memory cell region can be effectively improved. On the other hand, in the peripheral circuit region, as in the first embodiment, the whole is covered with a stopper film (hydrogen diffusion preventing film) 45 having a very small diffusion coefficient of hydrogen. For this reason, it is possible to prevent hydrogen atoms from diffusing up to the first and second transistors Tr1 and Tr2 on the semiconductor substrate 1. As a result, V _t (threshold voltage) of the first and second transistors Tr1 and Tr2 in the peripheral circuit region can be prevented from fluctuating, thereby preventing malfunction of the circuit operation.

  Next, in the same manner as in the process of FIG. 2 of the first embodiment, contact plugs 23, through-hole plugs 24e and 24f, and aluminum wirings 24g, 24h and 24i are formed. Thereafter, a hydrogen annealing process similar to that of the first embodiment is performed to diffuse an appropriate amount of hydrogen atoms into the semiconductor substrate 1 in the peripheral circuit region. Thereby, the DRAM of this embodiment is completed.

In the first and second embodiments, the hafnium oxide film 6a and the aluminum oxide film 6b are used as part of the material of the first and second gate insulating films 9a and 9b as high dielectric constant insulating films. The material of the high dielectric constant insulating film is not particularly limited as long as it has a dielectric constant higher than that of silicon oxide. For example, HfSiON, ZrO ₂ , Ta ₂ O ₅ , Nb ₂ O ₅ , ScO ₃ , Y ₂ O ₃ , La ₂ O ₃ , CeO ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , at least one insulating material selected from the group consisting of Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , and Lu ₂ O ₃ can be used.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Active region 2 Element isolation region 2a, 52 Silicon nitride film 2b, 51 Silicon oxide film 3 P well 4 N well 5a, 5b Silicon oxide film 6a Hafnium oxide film 6b Aluminum oxide film 7a, 7b Titanium nitride film 9a First 1 gate insulating film 9b second gate insulating film 10 low-concentration impurity diffusion layers 11a, 11b, 11c polysilicon films 12a, 12b, 12c containing impurities tungsten film 15 hard mask (silicon nitride film)
17a first gate electrode 17b second gate electrode 19a, 19b LDD region 21a first source and drain 21b second source and drain 22 SOD films 23, 24a, 24b, 24g contact plugs 24c, 24d wiring layer 24e, 24f Through-hole plugs 24h, 24i Aluminum wiring layer 26a Offset spacer 26b Side wall spacer 27 Hydrogen supply film (silicon nitride film)
28 Interlayer insulation film 30 Word line (buried gate electrode)
30 'dummy word line 30a barrier metal film 30b metal gate film 31 bit line 32a capacitive contact region 32b capacitive contact plug 33 bit contact region 36 silicon oxide film (plate mask film)
37 Third gate insulating film 38a Liner film 38b SOD film 39 Bit-con interlayer insulating film 43 Liner film 45 Stopper film 48 Capacitor element 48a Lower electrode 48b Capacitor insulating film 48c Polysilicon film 48d containing impurities Tungsten film 55 Trench Cn NMOS Formed region Cp Region formed with PMOS Tr1 First transistor Tr2 Second transistor Tr3 Third transistor

Claims (9)

A semiconductor substrate including a first region and a second region;
A hydrogen diffusion prevention film provided in the first and second regions and provided with a first opening in the first region;
A conductive layer embedded in the first opening;
An information storage element electrically connected to the conductive layer;
A hydrogen supply film covering the information storage element in the first region and covering the hydrogen diffusion prevention film in contact with the hydrogen diffusion prevention film in the second region;
A second opening opened through both the hydrogen supply film and the hydrogen diffusion prevention film in the second region;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the hydrogen supply film is a silicon nitride film having a composition represented by SiNx, and a value of x is 0.8 to 1.2. 3. The semiconductor device according to claim 1, wherein the hydrogen diffusion preventing film is a silicon nitride film having a composition of Si ₃ N ₄ .   The semiconductor device according to claim 1, wherein the information storage element is a capacitive element including a lower electrode, a capacitive insulating film, and an upper electrode.   The semiconductor device according to claim 4, wherein the hydrogen supply film covers the upper electrode in contact with the upper electrode in the first region. Forming a first element in a first region on a semiconductor substrate;
Forming a second element in a second region on the semiconductor substrate;
Forming a hydrogen diffusion prevention film covering both the first region and the second region;
Forming a first opening in the hydrogen diffusion prevention film above the first element;
Forming a hydrogen supply film that covers both the first opening and the hydrogen diffusion prevention film;
Performing a heat treatment for diffusing hydrogen from the hydrogen supply film;
Forming a second opening penetrating both the hydrogen supply film and the hydrogen diffusion prevention film above the second element;
Performing a heat treatment in an atmosphere containing hydrogen;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 6, wherein the hydrogen supply film is a silicon nitride film formed by a plasma CVD method.   8. The method of manufacturing a semiconductor device according to claim 6, wherein the hydrogen diffusion preventing film is a silicon nitride film formed by a thermal CVD method.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the thermal CVD method is one of an LPCVD method and an ALD method.