KR100762232B1 - Method of fabricating the recessed cell array transistor - Google Patents

Abstract

A method of manufacturing a recessed cell array transistor (RCAT) according to the present invention includes forming a trench isolation layer defining an active region on a semiconductor substrate, and forming a recess channel trench in an active region of the semiconductor substrate. Forming a spacer film; forming a spacer film formed of a nitride-rich oxide film on the sidewalls of the recess channel trench; forming a gate insulating film on the bottom of the spacer film and the recess channel trench; and forming a recess channel. And forming a gate stack to fill the trench.

Recessed Cell Array Transistors, Recess Channels, Field Concentration, Nitride-Rich Oxides, Spacers

Description

Method of fabricating the recessed cell array transistor

1 is a layout diagram illustrating a general recessed cell array transistor.

FIG. 2 is a cross-sectional view taken along the line A-A 'of FIG. 1.

3 to 6 are cross-sectional views illustrating a method of manufacturing a recessed cell array transistor according to the present invention.

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a recessed cell array transistor (RCAT).

As the design rule of the integrated circuit semiconductor device is rapidly reduced to a level of 70 nm or less, the gate resistance of the cell transistor is greatly increased, and the channel length is also rapidly decreased. As a result, the planar transistor structure has a limitation in implementing the gate resistance and the threshold voltage. Therefore, various methods of securing the channel length without increasing the design rule have been studied in various ways. In particular, it is a structure that extends the channel length more while maintaining a limited gate line width. A recess channel that recesses a semiconductor substrate and adopts the recess region as a gate structure further extends an effective channel length. Research on semiconductor devices having been actively conducted.

1 is a layout diagram illustrating a general recessed cell array transistor. 2 is a cross-sectional view taken along the line A-A 'of FIG. 1.

1 and 2, a device isolation trench is disposed in the device isolation region of the semiconductor substrate 100 having the device isolation region and the active region, and is disposed on the semiconductor substrate 100 exposed by the device isolation trench. The liner insulating film 112 is disposed. A trench device isolation film 110 is disposed on the liner insulating layer 112 to fill the device isolation trench. A recess channel trench 130 is disposed in the active region 120 defined by the trench isolation layer 110, and a gate insulating layer 132 and a gate stack 134 are disposed on the recess channel trench 130. Is placed. Storage node contact regions 121 and bit line contact regions 122 are disposed on the semiconductor substrate 100 on both sides of the recess channel trench 130, respectively.

Such a recessed cell array transistor structure, as mentioned above, because the channel is formed along the recess channel trench 130, increases the effective channel length to suppress the short channel effect and increase the punchthrough margin. It offers the advantage that it can. However, due to the bias applied to the gate stack 134, a phenomenon occurs in which an electric field is concentrated in the region indicated by “B” in FIG. 2, that is, near the upper sidewall of the trench 130 for the recess channel. Due to the electric field concentration, there is a problem that the reliability of the transistor element is lowered and the junction leakage current in the semiconductor substrate 100 is increased.

SUMMARY OF THE INVENTION The present invention provides a recessed recess which suppresses electric field concentration on sidewalls of a recess channel trench, thereby improving reliability of the transistor device and reducing junction leakage current to suppress device deterioration. It is to provide a method of manufacturing a cell array transistor.

In order to achieve the above technical problem, a method of manufacturing a recessed cell array transistor according to an embodiment of the present invention, forming a trench isolation layer defining an active region on a semiconductor substrate; Forming a trench for a recess channel in an active region of the semiconductor substrate; Forming a spacer film formed of a nitride-rich oxide film on a sidewall of the recess channel trench; Forming a gate insulating layer on a bottom of the spacer layer and a recess channel trench; And forming a gate stack to fill the recess channel trench.

The forming of the spacer layer may include forming a nitride-rich oxide film on an entire surface of the semiconductor substrate having the recess channel trench; And performing anisotropic etching on the nitride-rich oxide film to remove the nitride-rich oxide film at the bottom of the recess channel trench and to form a spacer film remaining on the sidewall of the recess channel trench. It is characterized by.

The forming of the nitride-rich oxide film is preferably performed using a chemical vapor deposition method using 10-30% SiH ₄ or SiH ₂ Cl ₂ and 70-90% NH ₃ gas as a reaction gas.

After forming the gate insulating layer, the method may further include performing a low temperature plasma nitridation treatment in a gas atmosphere including an element having a valence higher than that of silicon and in an NH ₃ atmosphere.

In this case, the low temperature plasma nitridation treatment supplies 50-1000 sccm of the NH ₃ gas, maintains the temperature of the semiconductor substrate at 200-500 ° C., and applies 100-1000 W of power to the reaction chamber for plasma nitridation treatment. It is preferable to carry out.

And performing a heat treatment for 1-120 minutes at a temperature of 800-850 ° C. and a pressure of 0.1-150 torr after the low temperature plasma nitriding treatment.

In order to achieve the above technical problem, a method of manufacturing a recessed cell array transistor according to another embodiment of the present invention, forming a pad insulating film pattern covering a device isolation region on a semiconductor substrate; Forming a device isolation trench in the device isolation region of the semiconductor substrate by etching the pad insulating layer pattern as an etching mask; Sequentially forming a sidewall oxide film and a liner nitride film on the semiconductor substrate exposed by the device isolation trench; Filling the device isolation trench by forming a buried insulating film on the liner nitride film; Forming a trench isolation layer by planarizing the buried insulating layer until the surface of the pad insulating layer is exposed; Forming a hard mask pattern on the trench isolation layer and the pad insulating layer; Forming a recess channel trench by sequentially removing exposed portions of the pad insulating layer and the semiconductor substrate by etching using the hard mask layer pattern as an etching mask; Forming a nitride-rich oxide film on an entire surface of the semiconductor substrate having the recess channel trench; Anisotropically etching the nitride-rich oxide layer to form a spacer layer on the trench sidewalls of the recess channel; Forming a gate insulating layer on a bottom of the spacer layer and a recess channel trench; And forming a gate stack to fill the recess channel trench.

The pad insulating layer pattern may be formed of an oxide layer having a thickness of 710-790 Å.

The forming of the nitride-rich oxide film is preferably performed using a chemical vapor deposition method using 10-30% SiH ₄ or SiH ₂ Cl ₂ and 70-90% NH ₃ gas as a reaction gas.

After forming the gate insulating layer, the method may further include performing a low temperature plasma nitridation treatment in a gas atmosphere including an element having a valence higher than that of silicon and in an NH ₃ atmosphere.

In this case, the low temperature plasma nitridation treatment supplies 50-1000 sccm of the NH ₃ gas, maintains the temperature of the semiconductor substrate at 200-500 ° C., and applies 100-1000 W of power to the reaction chamber for plasma nitridation treatment. It is preferable to carry out.

And performing a heat treatment for 1-120 minutes at a temperature of 800-850 ° C. and a pressure of 0.1-150 torr after the low temperature plasma nitriding treatment.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

3 to 6 are cross-sectional views illustrating a method of manufacturing a recessed cell array transistor according to the present invention.

First, referring to FIG. 3, a pad insulating layer pattern 302 is formed on a semiconductor substrate 300 such as a silicon substrate. To this end, a pad insulating film (not shown) and a mask film pattern (not shown) having a thickness of about 710 to 790 위에 are sequentially formed on the semiconductor substrate 300. The pad insulating layer pattern 302 is formed by removing a portion of the pad insulating layer by etching using the mask layer pattern as an etching mask. The pad insulating layer pattern 302 may be formed of an oxide layer to expose the device isolation region defining the active region 301 of the semiconductor substrate 300.

Next, the device isolation region of the semiconductor substrate 300 is etched to a predetermined depth, for example, 2800-3100 μs by etching using the pad insulating film pattern 302 or the pad insulating film pattern 302 and the mask film pattern as an etching mask. A separation trench 304 is formed. Next, a sidewall oxide film 306 is formed on the semiconductor substrate 300 exposed by the device isolation trench 304 to a thickness of approximately 190-210Å. The sidewall oxide film 306 can be formed using a thermal oxidation method using SiH ₄ gas and O ₂ gas. Next, the liner nitride film 308 is formed to a thickness of approximately 90-110 mm 3 over the entire surface of the resultant sidewall oxide film 306 is formed. The liner nitride film 308 can be formed using low pressure chemical vapor deposition (LPCVD) using SiH ₂ Cl ₂ gas and NH ₃ gas as the source gas.

Next, a buried insulating film is formed on the liner nitride film 308 so that the device isolation trench 304 is buried. The buried insulating film may be formed of a silicon oxide nitride (Si _x O _y N _z ) film having a thickness of approximately 4400-4600 Å. In this case, the buried insulating film may be performed, followed by heat treatment. Next, the trench isolation layer 310 is formed by planarization until the pad insulation layer pattern 302 is exposed. The planarization may be performed using a chemical mechanical polishing (CMP) method, and the thickness of the remaining pad insulating layer pattern 302 may be about 670-730 Å.

Next, referring to FIG. 4, a nitride film is formed to have a thickness of about 1-100 GPa as a hard mask film on the entire surface of the resultant trench device isolation film 310. After forming a mask film pattern such as a photoresist film pattern on the nitride film, the surface of the pad insulating film pattern 302 corresponding to the region where the recess channel trench is to be formed by etching using the photoresist film pattern as an etch mask. The nitride film pattern 312 exposing the film is formed. Specifically, although not shown in detail in the drawing, the nitride film pattern 312 has a lower portion of the gate region and an opening that exposes both active regions and sidewall oxide films adjacent to the active regions.

Next, the exposed portion of the pad insulating film pattern 302 and the semiconductor substrate 300 is etched using the nitride film pattern 312 as an etch mask to form a recess channel trench 314. Next, a nitride-rich oxide layer 316 is formed on the entire surface of the resultant trench 314 formed therein. The nitride-rich oxide film 316 can be formed using 10-30% SiH ₄ or SiH ₂ Cl ₂ and 70-90% NH ₃ gas as the reaction gas. In this case, a chemical vapor deposition method may be used, or in some cases, a thermal oxidation method may be used. In the step of using SiH ₄ gas or SiH ₂ Cl ₂ gas, the process is performed under a pressure condition of about 1.0 torr, a temperature condition of about 640 ° C., and a deposition rate condition of about 19 nm / min. In the step of using NH ₃ gas, the process is carried out under a pressure condition of about 0.1-150.0 torr, a temperature condition of about 850 ° C., and a deposition rate condition of about 1-150 nm / min.

Referring next to FIG. 5, anisotropic etching, such as etchback, is performed on the nitride-rich oxide film 316 of FIG. A spacer film 318 is formed. The bottom surface of the recess channel trench 314 is exposed by the spacer film 318. Next, a gate insulating film 320 is formed on the bottom surface of the spacer film 318 and the recess channel trench 314. The gate insulating film 320 may be formed of an oxide film. After the gate insulating film 320 is formed, low temperature plasma nitridation is performed in a gas atmosphere containing an element having a valence higher than that of silicon and in an NH ₃ atmosphere to improve the insulating property of the gate insulating film 320. The low temperature plasma nitridation treatment is performed by supplying 50-1000 sccm of NH ₃ gas, maintaining the temperature of the semiconductor substrate 300 at 200-500 ° C., and applying 100-1000 W of power to the reaction chamber for plasma nitridation treatment. can do. After the heat treatment is performed for 1-120 minutes at a temperature of 800-850 ℃ and pressure of 0.1-150torr. In some cases, the gate insulating film 320 may be formed at a temperature of about 850 ° C. and a pressure of about 0.1-150.0 torr using NH ₃ gas or a mixture of NH ₃ / Ar or NH ₃ / N ₂ . Depending on the plasma may be applied.

Next, referring to FIG. 6, the gate conductive layer, the metal silicide layer, and the gate hard mask layer are sequentially stacked on the entire surface of the resultant in which the gate insulating layer 320 is formed. The gate conductive film is formed of a doped polysilicon film, the metal silicide film is formed of a tungsten silicide film, and the gate hard mask film is formed of a nitride film. Next, a gate in which the gate conductive film pattern 322, the metal silicide film pattern 324, and the gate hard mask film pattern 326, which fill the recess channel trench 314, are sequentially stacked by performing normal patterning. Form stack 328. In this process, the nitride film pattern 312, the liner nitride film 308, and the pad insulating film pattern 302 on the surface of the semiconductor substrate 300 may also be removed. Next, an impurity region such as a source / drain region is formed using a conventional ion implantation method.

In such a recessed cell array transistor, a spacer film 318 made of a nitride-rich oxide film is disposed on a sidewall of the recess channel trench 314 and is recessed due to a bias applied to the gate stack 328. The phenomenon in which the strength of the electric field increases to the sidewalls of the channel trench 314 can be reduced, thereby reducing the electric field affecting the source region and the drain region, thereby blocking the passage of the junction leakage current. In the case of a semiconductor memory device, a refresh characteristic for improving storage capacity is improved. Furthermore, in the method of forming the gate insulating film 320, the low temperature plasma nitridation treatment is performed in a nitrogen atmosphere instead of the conventional oxygen atmosphere that generates excessive leakage current, or during the subsequent heat treatment after the gate insulating film 320 is formed. By doing so, problems caused by the high temperature heat treatment, for example, reduction of breakdown voltage from around the semiconductor substrate 300 can be suppressed, and ultimately, insulation characteristics of the gate insulating film 320 are improved. .

As described so far, according to the method for manufacturing a recessed cell array transistor according to the present invention, after forming a spacer film made of a nitride-rich oxide film on a trench sidewall for a recess channel, and further forming a gate insulating film, By performing low-temperature plasma nitridation and heat treatment, the field concentration on the trench channel sidewalls can be suppressed to improve the reliability of the device, and the junction leakage current can be reduced to improve the operation characteristics of the device, and the gate insulating film. It is provided with the advantage that the insulating properties of the can be improved.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (12)

Forming a trench isolation layer that defines an active region on the semiconductor substrate; Forming a trench for a recess channel in an active region of the semiconductor substrate; Forming a spacer film formed of a nitride-rich oxide film on a sidewall of the recess channel trench; Forming a gate insulating layer on a bottom of the spacer layer and a recess channel trench; And And forming a gate stack to fill the recess channel trench. The method of claim 1, wherein the forming of the spacer film, Forming a nitride-rich oxide film on an entire surface of the semiconductor substrate having the recess channel trench; And Performing anisotropic etching on the nitride-rich oxide film to remove the nitride-rich oxide film at the bottom of the recess channel trench and to form a spacer film remaining on the sidewall of the recess channel trench. A method of manufacturing a recessed cell array transistor, characterized in that. The method of claim 2, The forming of the nitride-rich oxide layer may be performed using a chemical vapor deposition method using 10-30% SiH ₄ or SiH ₂ Cl ₂ and 70-90% NH ₃ as a reaction gas. Method of manufacturing recessed cell array transistor. The method of claim 1, And forming a gas atmosphere including an element having a valence higher than that of silicon, and performing a low temperature plasma nitridation treatment in an NH ₃ atmosphere after forming the gate insulating layer. The method of claim 4, wherein The low temperature plasma nitridation treatment is performed by supplying 50-1000 sccm of the NH ₃ gas, maintaining the temperature of the semiconductor substrate at 200-500 ° C., and applying power of 100-1000 W to the reaction chamber for plasma nitridation treatment. Method of manufacturing a recessed cell array transistor, characterized in that. The method of claim 4, wherein And performing a heat treatment for 1-120 minutes at a temperature of 800-850 ° C. and a pressure of 0.1-150 torr after the low temperature plasma nitridation treatment. Forming a pad insulating layer pattern covering the device isolation region on the semiconductor substrate; Forming a device isolation trench in the device isolation region of the semiconductor substrate by etching the pad insulating layer pattern as an etching mask; Sequentially forming a sidewall oxide film and a liner nitride film on the semiconductor substrate exposed by the device isolation trench; Filling the device isolation trench by forming a buried insulating film on the liner nitride film; Forming a trench isolation layer by planarizing the buried insulating layer until the surface of the pad insulating layer is exposed; Forming a hard mask pattern on the trench isolation layer and the pad insulating layer; Forming a recess channel trench by sequentially removing exposed portions of the pad insulating layer and the semiconductor substrate by etching using the hard mask layer pattern as an etching mask; Forming a nitride-rich oxide film on an entire surface of the semiconductor substrate having the recess channel trench; Anisotropically etching the nitride-rich oxide layer to form a spacer layer on the trench sidewalls of the recess channel; Forming a gate insulating layer on a bottom of the spacer layer and a recess channel trench; And And forming a gate stack to fill the recess channel trench. The method of claim 7, wherein And the pad insulating film pattern is formed of an oxide film having a thickness of 710-790 Å. The method of claim 7, wherein The forming of the nitride-rich oxide layer may be performed using a chemical vapor deposition method using 10-30% SiH ₄ or SiH ₂ Cl ₂ and 70-90% NH ₃ as a reaction gas. Method of manufacturing recessed cell array transistor. The method of claim 7, wherein And forming a gas atmosphere including an element having a valence higher than that of silicon, and performing a low temperature plasma nitridation treatment in an NH ₃ atmosphere after forming the gate insulating layer. The method of claim 10, The low temperature plasma nitridation treatment is performed by supplying 50-1000 sccm of the NH ₃ gas, maintaining the temperature of the semiconductor substrate at 200-500 ° C., and applying power of 100-1000 W to the reaction chamber for plasma nitridation treatment. Method of manufacturing a recessed cell array transistor, characterized in that. The method of claim 10, And performing a heat treatment for 1-120 minutes at a temperature of 800-850 ° C. and a pressure of 0.1-150 torr after the low temperature plasma nitridation treatment.

Images