JP4462029B2 - Manufacturing method of MOS semiconductor devices - Google Patents

Description

  The present invention relates to a method for manufacturing a MOS type semiconductor device such as a MOS type IC (integrated circuit) having a MOS type transistor, and more particularly to a method for inactivating interface states with fluorine atoms at the interface between a gate insulating film and a silicon substrate. Is.

  In general, in a MOS transistor, unbonded silicon bonds in which neither Si—Si nor Si—O bonds are formed exist as so-called dangling bonds on the surface of a silicon substrate immediately below a gate oxide film. A dangling bond behaves as an interface state for trapping and re-emission of charge, and therefore causes fluctuations in threshold voltage and generation of current noise in a MOS transistor, and it is preferable that it does not exist.

  Conventionally, as a method for inactivating interface states generated during a manufacturing process, a method of performing a low-temperature heat treatment in a hydrogen atmosphere at the final stage of the manufacturing process is known. The interface state is generated when etching damage or charge-up damage in a subsequent process such as dry etching is applied to the silicon substrate in addition to the one generated in the gate oxide film formation stage. Since hydrogen reaches the interface between the gate oxide film and the silicon substrate by diffusion at a relatively low temperature of 400 to 450 ° C., heat treatment is performed in a hydrogen atmosphere at the stage where dry etching of the wiring material layer is completed. The interface states are terminated by hydrogen in the form of Si—H and deactivated.

  However, when using hydrogen to inactivate the interface state, the bond energy between hydrogen and silicon is relatively low, so that the hydrogen is released while using the MOS transistor, and transistor characteristics There has been a problem that fluctuates over time.

  Therefore, as another conventional method, a method of inactivating the interface state using fluorine (F), which has a more stable bond with silicon than hydrogen (for example, Patent Document 1, Non-Patent Document 1). (See Patent Documents 1 and 2).

FIG. 12 shows an interface state deactivation method similar to the method described in Non-Patent Document 1. In this method, a field oxide film 2 is formed on the surface of a silicon substrate 1 and then a gate oxide film 3 is formed in an element hole of the oxide film 2. After depositing the polysilicon layer 4 for the gate electrode so as to cover the oxide films 2 and 3, fluorine ions F ⁺ are implanted into the polysilicon layer 4. Then, fluorine in the polysilicon layer 4 is diffused to the interface between the oxide film 3 and the substrate 1 by heat treatment to terminate the interface state with fluorine atoms. Thereafter, the polysilicon layer 4 is patterned to form a gate electrode layer.

  FIG. 13 shows an interface state deactivation method similar to the method disclosed in Patent Document 1 or Non-Patent Document 2. In this method, a field oxide film 2 and a gate oxide film 3 are formed on the surface of a silicon substrate 1 and then a polysilicon layer for a gate electrode is deposited so as to cover the oxide films 2 and 3. After this polysilicon layer is patterned to form a gate electrode layer 4G, low impurity concentration source / drain regions 5S and 5D are formed by impurity ion implantation using the field oxide film 2 and the gate electrode layer 4G as a mask. .

  Next, a silicon oxide film is deposited on the upper surface of the substrate 1 by a CVD (Chemical Vapor Deposition) method. Then, the silicon oxide film is etched back by anisotropic etching to form side spacers 6S and 6D made of the remaining portions of the silicon oxide film on one side and the other side of the gate electrode layer 4G, respectively. Thereafter, high impurity concentration source / drain regions 7S, 7D are formed by impurity ion implantation using the field oxide film 2, the gate electrode layer 4G and the side spacers 6S, 6D as a mask.

In the method disclosed in Non-Patent Document 2, after forming the gate electrode layer 4G, fluorine ions F ⁺ are implanted into the electrode layer 4G. Thereafter, fluorine is diffused to the interface between the oxide film 3 and the substrate 1 below the electrode layer 4G by heat treatment to terminate the interface state with fluorine atoms. On the other hand, in the method disclosed in Patent Document 1, after forming the source and drain regions 7S and 7D, fluorine ions F + are implanted into the entire surface of the substrate. Thereafter, at least fluorine in the gate electrode layer 4G is diffused to the interface between the oxide film 3 and the substrate 1 by heat treatment, and the interface state is terminated with fluorine atoms.
JP 2000-269492 A "Lower noise of MOS type operational amplifier in in-vehicle ECU" Automobile Technical Society Pre-print 961 (1996-5) pp.125-128 “Improvement of SiO2 / Si Interface Properties Utilizing Fluorine Ion Implantation and Drive-in Diffusion”, Japanese Journal of Applied Physics, Vol.28, No.6, pp.1041-1045

  According to the conventional technique described above with reference to FIGS. 12 and 13, since the fluorine ion implantation process is performed before or after the formation of the gate electrode layer 4G, the interface state inactivation generated before the process is performed. Although there is an effect on the conversion, the interface state generated by the damage in the dry etching process after the processing process cannot be inactivated. For this reason, suppression of characteristic variation and noise reduction in the MOS transistor are not always sufficient.

  An object of the present invention is to provide a method for manufacturing a novel MOS type semiconductor device with low noise and little characteristic variation.

The manufacturing method of the MOS type semiconductor device according to the present invention is as follows:
A gate electrode layer is formed on one main surface of the silicon substrate via a gate insulating film, and a source region and a drain region are formed on one main surface of the silicon substrate on one side and the other side of the gate electrode layer, respectively. Forming a MOS transistor having the gate insulating film, the gate electrode layer, the source region and the drain region,
Forming an interlayer insulating film covering the MOS transistor on one main surface of the silicon substrate;
Forming first and second connection holes respectively corresponding to the source region and the drain region in the interlayer insulating film by photolithography and dry etching;
Implanting fluorine ions shallower than the junction depth of the source region and the drain region into the source region and the drain region through the first and second connection holes, respectively;
Diffusing fluorine contained in the source region and the drain region to the interface between the gate insulating film and the silicon substrate below the gate electrode layer by heat treatment to terminate the interface state with fluorine atoms;
Forming a first wiring layer and a second wiring layer on the interlayer insulating film so as to be connected to the source region and the drain region through the first and second connection holes, respectively.

  According to the manufacturing method of the MOS type semiconductor device of the present invention, after forming the first and second connection holes corresponding to the source region and the drain region in the interlayer insulating film, respectively, the first and second connection holes are respectively interposed. Then, fluorine ions are implanted into the source region and the drain region. Then, fluorine contained in the source region and the drain region is diffused to the interface between the gate insulating film and the silicon substrate below the gate electrode layer by heat treatment, and the interface state is terminated with fluorine atoms to be inactivated.

  As described above, when fluorine ion implantation and heat treatment are performed after the connection hole is formed, not only the interface state generated by the dry etching damage at the time of forming the gate electrode layer but also the interface state generated by the dry etching damage at the time of forming the connection hole. Can also be inactivated. Further, since the heat treatment for fluorine diffusion is performed before the formation of the wiring layer, the heat treatment temperature can be set to a relatively high temperature up to about 1000 ° C., and the gate electrode can be formed from the ion implantation portion in the source region and the drain region. Fluorine can easily reach the region immediately below the layer by diffusion.

  In the manufacturing method of the MOS type semiconductor device according to the present invention, in the step of forming the first and second connection holes, the opening size is increased as the first and second connection holes are both moved outward. You may make it form. In this way, when fluorine ions are implanted, the fluorine ions are uniformly implanted in the source region and the drain region, which are located around the bottoms of the first and second connection holes, respectively, and near the gate electrode layer. Can do. For this reason, it becomes easier to diffuse fluorine in the region directly under the gate electrode layer. Further, the step coverage is also improved for the first and second wiring layers formed so as to cover the first and second connection holes, respectively.

  According to the present invention, after the connection holes for the source and drain wirings are formed in the interlayer insulating film, the interface state is deactivated by fluorine ion implantation and heat treatment, so that the fluctuation of characteristics in the MOS transistor is suppressed. And an effect that noise reduction can be sufficiently achieved in practice.

  1 to 5 show a method of manufacturing a MOS IC according to an embodiment of the present invention, and steps (1) to (5) corresponding to the respective drawings will be described in order.

  (1) A field insulating film 12 made of a silicon oxide film is formed on one main surface of the silicon substrate 10 by a known selective oxidation method. The insulating film 12 can also be formed by depositing a silicon oxide film by a CVD method or the like in a recess provided on one main surface of the substrate 10. A gate insulating film 14 made of a silicon oxide film is formed on the surface of the silicon region in the element hole 12a of the insulating film 12 by a known thermal oxidation method.

  Next, an electrode material layer is formed on the upper surface of the substrate so as to cover the field insulating film 12 and the gate insulating film 14. Then, this electrode material layer is patterned by photolithography and dry etching treatment to form a gate electrode layer 16 composed of the remaining portion of the electrode material layer on the gate insulating film 14. As the electrode material layer, a doped polysilicon layer or a polycide layer (a laminate in which a silicide layer of a refractory metal such as Ti, W, or Mo is stacked on the polysilicon layer) or the like can be used.

  Next, low impurity concentration source / drain regions 20 and 22 are formed in the silicon region in the element hole 12a by impurity ion implantation using the field insulating film 12 and the gate electrode layer 16 as a mask. Then, after a silicon oxide film is deposited on the upper surface of the substrate 10 by the CVD method, the silicon oxide film is etched back by an anisotropic etching process so that the silicon oxide film remains on one side and the other side of the gate electrode layer 16. Side spacers 18a and 18b consisting of portions are formed. Thereafter, high impurity concentration source and drain regions 24 and 26 are formed in the silicon region in the element hole 12a by impurity ion implantation using the field insulating film 12, the gate electrode layer 16 and the side spacers 18a and 18b as a mask. .

  As described above, the MOS transistor having the gate insulating film 14, the gate electrode layer 16, the low impurity concentration source / drain regions 20, 22 and the high impurity concentration source / drain regions 24, 26 is formed into an element hole. 12a. As the MOS transistor, an N-channel or P-channel type transistor may be formed. On the substrate 10, a complementary MOS IC including P-channel and N-channel MOS transistors can be formed.

  (2) An interlayer insulating film 28 is formed on the upper surface of the substrate 10 so as to cover the field insulating film 12 and the MOS transistor in the element hole 12a. As the insulating film 28, a silicon oxide film, a PSG (phosphosilicate glass) film, a BPSG (boron / phosphosilicate glass) film, or the like is formed by a CVD method or the like, or an organic or inorganic silicon oxide film is formed by a coating method or the like. Or a laminated film of a CVD film and a coating film can be formed as necessary.

  (3) A resist layer 30 having connection hole patterns for source and drain wirings is formed on the interlayer insulating film 28 by photolithography. Then, connection holes 32 and 34 corresponding to the source and drain regions 24 and 26 are formed in the interlayer insulating film 28 by anisotropic dry etching using the resist layer 30 as a mask. Thereafter, the resist layer 30 is removed.

  FIG. 6 shows an example of the arrangement of connection holes, and the cross section taken along the line A-A ′ of FIG. 6 corresponds to the cross section shown in FIG. 3. In the example of FIG. 6, the connection holes 32 and 34 for the source and drain wiring are both formed as a plurality of (for example, four) holes arranged along the gate electrode layer 16. FIG. 7 shows another example of the arrangement of connection holes, and the cross section taken along line B-B ′ of FIG. 7 corresponds to the cross section shown in FIG. 3. In the example of FIG. 7, the connection holes 32 and 34 for source and drain wiring are both formed as one elongated hole extending along the gate electrode layer 16. 6 and 7, the connection hole 36 for the gate wiring is formed by a selective etching process simultaneously with the connection holes 32 and 34.

(4) Fluorine ions F ⁺ are implanted into the source and drain regions 24 and 26 through the connection holes 32 and 34, respectively. The ion implantation conditions at this time may be an acceleration energy of 15 to 50 keV (preferably 30 keV) and a dose of 1 × 10 ^{12 to} 5 × 10 ¹⁵ cm ⁻² (preferably 1 × 10 ¹⁵ cm ⁻² ). Assuming that the junction depth Xj of the source / drain regions 24 and 26 is 0.2 μm as an example, the implantation depth of fluorine ions F ⁺ is preferably set to be shallower than Xj = 0.2 μm. This is because if fluorine ions F ⁺ are implanted into or near the PN junction, the junction leakage current increases.

  After the fluorine ion implantation, a heat treatment is performed in order to diffuse fluorine in the source / drain regions 24 and 26 to the interface between the gate insulating film 14 and the substrate 10 immediately below the gate electrode layer 16. In the case where the heat treatment at this time is performed by RTA (Rapid Thermal Anneal) treatment, the heat treatment conditions can be, for example, a temperature of 1000 ° C. and a time of 5 to 15 seconds (preferably 10 seconds). As another example of the heat treatment conditions, the temperature may be 900 to 950 ° C. and the time may be 15 to 30 seconds. When the heat treatment is performed by furnace annealing, the heat treatment conditions can be a temperature of 800 to 900 ° C. and a time of 10 to 30 minutes. As a result of the heat treatment, the interface state is terminated with fluorine atoms at the interface between the gate insulating film 14 and the substrate 10 immediately below the gate electrode layer 16 and inactivated. The interface states to be deactivated at this time are those generated by the oxidation treatment for forming the gate insulating film 14 in the step of FIG. 1, and the electrodes for forming the gate electrode layer 16 in the step of FIG. There are those caused by the material layer etching process and those caused by the etching process for forming the connection holes 32 to 36 in the interlayer insulating film 28 in the step of FIG.

Since fluorine ions F ⁺ are also implanted into the gate electrode layer 16 through the connection holes 36 shown in FIG. 6 or 7, the fluorine in the electrode layer 16 is subjected to a heat treatment so that the gate insulating film is directly under the electrode layer 16. 14 and the substrate 10 are supplied to the interface. However, the amount of fluorine supplied to the channel portion in this way is small. Most of the fluorine supplied to the channel portion is supplied by diffusion from the source and drain regions 24 and 26 as described above.

  (5) A wiring material layer such as an Al alloy is deposited on the upper surface of the substrate 10 by, for example, a sputtering method, reflow treatment is performed as necessary, and then the wiring material layer is patterned by photolithography and dry etching treatment. Wiring layers 38 and 40 made of the remaining material layer are formed on the interlayer insulating film 28. The wiring layers 38 and 40 are connected to the source and drain regions 24 and 26 through the connection holes 32 and 34, respectively.

  FIGS. 8 and 10 show first and second modifications of the connection hole forming method, respectively. FIGS. 9 and 11 show a state in which a wiring layer is formed in the connection hole of FIGS. 8 to 11, parts similar to those in FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the step of FIG. 8, the recesses 34a are formed in the interlayer insulating film 28 by isotropic wet (or dry) etching using the resist layer 30 as a mask. The recess 34 a is an upper opening of the connection hole 34 and is formed in a size larger than the opening size of the resist layer 30. Subsequently, a connection hole 34 continuing to the recess 34 a is formed in the interlayer insulating film 28 by anisotropic dry etching using the resist layer 30 as a mask. The connection hole 34 is formed so that the opening size of the upper portion is substantially equal to the opening size of the resist layer 30 and the opening size of the lower portion is slightly smaller than the opening size of the resist layer 30, and includes the entire recess 34 a. A typical shape is such that the opening size increases as it goes outward. The connection hole 32 shown in FIG. 3 is also formed in the same manner as the connection hole 34 described above. Thereafter, the resist layer 30 is removed.

In the step of FIG. 4, fluorine ions F ⁺ are implanted into the source and drain regions 24 and 26 through the connection holes 32 and 34 having the shapes as shown in FIG. At this time, in the drain region 26, the fluorine ions F ⁺ can be uniformly implanted in the portion R located near the bottom of the connection hole 34 and close to the gate electrode layer 16. The same applies to the portion of the source region 24 that is located near the bottom of the connection hole 32 and is close to the gate electrode layer 16. For this reason, if heat treatment for fluorine diffusion is performed in the same manner as described above, fluorine can be easily diffused into the region immediately below the gate electrode layer 16, and the interface states can be efficiently deactivated. The In the connection hole 34 shown in FIG. 3, since the side wall is nearly vertical, the unevenness of the implantation of fluorine ions F ⁺ occurs in the part corresponding to the part R in FIG. 8 compared to the connection hole 34 shown in FIG. It's easy to do. The same applies to the connection hole 32 shown in FIG.

  After the heat treatment, in the step of FIG. 9, the wiring layer 40 is formed in the connection hole 34 in the same manner as described above with reference to FIG. In addition, the wiring layer 38 is similarly formed in the connection hole 32 having the same shape as the connection hole 34. In this case, since both the connection holes 32 and 34 are stepped at the upper opening 34a as shown in FIG. 9, the step coverage of the wiring layer is improved.

  In the process of FIG. 10, the connection hole 34 is formed in the interlayer insulating film 28 by anisotropic dry etching using the resist layer 30 as a mask. In this case, if the etching is performed under the condition that the opening end of the resist layer 30 is etched back, the connection hole 34 is formed so that the opening size increases as it goes outward. The connection hole 32 shown in FIG. 3 is also formed in the same manner as the connection hole 34 described above. Thereafter, the resist layer 30 is removed.

In the step of FIG. 4, fluorine ions F ⁺ are implanted into the source and drain regions 24 and 26 through the connection holes 32 and 34 having the shape shown in FIG. 10 as described above. At this time, in the drain region 26, the fluorine ions F ⁺ can be uniformly implanted in the portion R located near the bottom of the connection hole 34 and close to the gate electrode layer 16. The same applies to the portion of the source region 24 that is located near the bottom of the connection hole 32 and is close to the gate electrode layer 16. For this reason, if heat treatment for fluorine diffusion is performed in the same manner as described above, fluorine can be easily diffused into the region immediately below the gate electrode layer 16, and the interface states can be efficiently deactivated. The

  After the heat treatment, in the step of FIG. 11, the wiring layer 40 is formed in the connection hole 34 in the same manner as described above with reference to FIG. In addition, the wiring layer 38 is similarly formed in the connection hole 32 having the same shape as the connection hole 34. In this case, since both the connection holes 32 and 34 are stepped at the upper opening, the step coverage of the wiring layer is improved.

It is sectional drawing which shows the MOS type transistor formation process in the manufacturing method of MOS type IC which concerns on one Embodiment of this invention. FIG. 2 is a cross-sectional view showing an interlayer insulating film forming step that follows the step of FIG. 1. FIG. 3 is a cross-sectional view showing a connection hole forming step following the step of FIG. 2. It is sectional drawing which shows the fluorine ion implantation process following the process of FIG. FIG. 5 is a cross-sectional view showing a wiring formation process following the process of FIG. 4. FIG. 4 is a top view showing the arrangement of connection holes in the MOS transistor of FIG. 3. It is a top view which shows the modification of connection hole arrangement | positioning. It is sectional drawing which shows the 1st modification of a connection hole formation method. It is sectional drawing which shows the state which formed the wiring layer in the connection hole of FIG. It is sectional drawing which shows the 2nd modification of a connection hole formation method. It is sectional drawing which shows the state which formed the wiring layer in the connection hole of FIG. It is sectional drawing which shows the 1st example of the conventional interface state deactivation method. It is sectional drawing which shows the 2nd example of the conventional interface state deactivation method.

Explanation of symbols

  10: silicon substrate, 12: field insulating film, 14: gate insulating film, 16: gate electrode layer, 18a, 18b: side spacer, 20, 22: low concentration source / drain region, 24, 26: high concentration source / drain Region, 28: interlayer insulating film, 30: resist layer, 32-36: connection hole, 38, 40: wiring layer.

Claims (3)

A gate electrode layer is formed on one main surface of the silicon substrate via a gate insulating film, and a source region and a drain region are formed on one main surface of the silicon substrate on one side and the other side of the gate electrode layer, respectively. Forming a MOS transistor having the gate insulating film, the gate electrode layer, the source region and the drain region,
Forming an interlayer insulating film covering the MOS transistor on one main surface of the silicon substrate;
Forming first and second connection holes respectively corresponding to the source region and the drain region in the interlayer insulating film by photolithography and dry etching;
Implanting fluorine ions shallower than the junction depth of the source region and the drain region into the source region and the drain region through the first and second connection holes, respectively;
Diffusing fluorine contained in the source region and the drain region to the interface between the gate insulating film and the silicon substrate below the gate electrode layer by heat treatment to terminate the interface state with fluorine atoms;
Forming a first wiring layer and a second wiring layer on the interlayer insulating film so as to be connected to the source region and the drain region through the first and second connection holes, respectively. Manufacturing method of semiconductor devices. When forming the first and second connection holes, simultaneously forming a third connection hole corresponding to the gate electrode layer;
In the step of implanting the fluorine ions, fluorine ions are implanted into the gate electrode layer through the third connection hole formed on the gate electrode layer, and the first and second connection holes are respectively formed. 2. The method of manufacturing a MOS type semiconductor device according to claim 1, wherein fluorine ions are implanted through the first electrode.   3. The MOS type according to claim 1, wherein in the step of forming the first and second connection holes, the first and second connection holes are formed so that the opening size increases as they proceed outward. Manufacturing method of semiconductor devices.

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