JPH11307764A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce variations in contact resistance and to prevent the increase in parasitic junction capacitance. SOLUTION: In a metal oxide semiconductor(MOS) transistor, a sidewall 19 is formed on the side surface of an electrode 18. The sidewall 19 comprises an oxide layer 19a, a nitride layer 19b, a silicon layer 19c, and a silicide layer 19d in this order, starting from the electrode 18 side. A silicide layer 19d is connected electrically to a source region 12 and a drain region 13. Even if the formation position of contact with respect to the source region 12 and drain region 13 is displaced, the connection is assured due to the silicide layer 19d. Since the width of the sidewall 19 is thick, impurity is introduced with large energy at the formation of the source region 12 and the drain region 13. Thus, the source region 12 and drain region 13 can be formed down to a deep position of a substrate 11, for making parasitic junction capacitance small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an electrode having a side wall formed on a side surface and a method of manufacturing the same, and more particularly to a MOS (Metal-Oxide-Se) device.
The present invention relates to a semiconductor device provided with a semiconductor transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the miniaturization of semiconductor devices has been advanced, and the resistance during driving has been decreasing year by year due to the shortening of the gate length of transistors and the like. However, on the other hand, the parasitic resistance is increasing due to the increase in the contact resistance due to the reduction of the contact diameter and the shallow junction of the source region and the drain region. Further, the distance between the contact portion and the gate electrode cannot be increased, and the contact portion may approach the gate electrode or come into contact with the gate electrode. Further, short channel effects such as reduction in threshold voltage due to shortening of the gate length and connection between the drain depletion layer and the source depletion layer (so-called punch-through) have become remarkable.

Therefore, for example, as a means for reducing the parasitic resistance, a self-aligned silicide (which forms a silicide layer on the surface of a metal layer after depositing a metal layer on the surface of the source region, the drain region and the gate electrode, and then heating the metal layer) is used. Salicide) technology is being developed. As a means for preventing the approach between the gate electrode and the contact portion, a self-aligned contact technique of forming a side wall on the side surface of the gate electrode using a material different from that of the interlayer insulating film has been developed. Further, as a means for suppressing the short channel effect, an impurity having a conductivity type different from that of the source region and the drain region is introduced into a region between the source region and the drain region to form a concentration adjustment region, and an impurity in the semiconductor substrate is formed. Technology to adjust the concentration has been developed (Semiconductor World 1995.11 P78 -8
2).

[0004]

However, when the side wall is formed on the gate electrode to prevent the gate electrode from coming into contact with the contact portion as described above, there is a problem as shown in FIG. This figure shows a conventional MOS (Metal Oxide Se
a cross-sectional configuration of a transistor, and a region surrounded by an element isolation region 121 of a silicon substrate 111 has a source region 112 and a drain region 11
3 and a gate electrode 118 having a side wall 119, respectively. Here, contact portions 123 and 1 for source region 112 and drain region 113 are provided.
24 shows a state where the original formation position is shifted particularly due to misalignment of the contact portion 124 or the like. As described above, if the contact portion 124 is displaced, the side wall 11
The contact area between the contact portion 124 and the drain region 113 is reduced by an amount corresponding to the overlap with 9, resulting in a large variation in the contact area. For example, when the contact diameter is 0.30 μm, the contact resistance is 5.
When the contact diameter is 0.26 μm, the contact resistance is 7.0 to 1 Ω.
It varied to about 2.0Ω.

[0005] As shown in FIG. 8, when the concentration adjustment region 116 is formed for suppressing the short channel effect, the introduction of impurities for forming the concentration adjustment region 116 forms the gate electrode 118. In general, the process is generally performed on the entire surface including a region where the source region 112 and the drain region 113 are to be formed. However, in recent years, the junction depth between the source region 112 and the drain region 113 has become shallower, so that the deepest portions of the source region 112 and the drain region 113 may have the concentration of impurities introduced when forming the concentration adjustment region 116. (The area shown by Rishiji in FIG. 8). Therefore, there is also a problem that the parasitic junction capacitance of the transistor increases and the load increases.

As a means for solving such an increase in the parasitic capacitance, a method has been proposed in which impurities for forming the concentration adjusting region 116 are introduced in a self-aligned manner after the gate electrode 118 is formed. I have. However, in this case, since ion implantation is performed through the gate electrode 118,
There is a problem that a large implantation energy is required, and the profile of the implanted impurity is widened. Further, since impurities pass through the gate insulating film 117, there is a problem that the reliability of the gate insulating film 117 is also reduced, and more preferable means have been desired.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device and a method of manufacturing the same, which can reduce the variation in contact resistance and prevent an increase in parasitic junction capacitance. It is in.

[0008]

A semiconductor device according to the present invention comprises: an electrode formed on a surface of a semiconductor substrate and having a side surface along a thickness direction of the semiconductor substrate; And a side wall having a conductive layer in at least a part of the portion.

A method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming an electrode having a side surface along the thickness direction of the semiconductor substrate on the surface of the semiconductor substrate; Forming a side wall having a conductive layer.

[0010] In the semiconductor device according to the present invention, the electrode on the semiconductor substrate includes a conductive layer on the outside of the side wall. Therefore, for example, even when the formation position of the contact portion is shifted in the case where the contact portion is formed near the electrode, the electrical connection is ensured through the conductive layer.

In the method for manufacturing a semiconductor device according to the present invention,
First, an electrode is formed, and then a side wall having a conductive layer on at least a part of an outer portion is formed on a side surface thereof.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a configuration of a semiconductor device according to an embodiment of the present invention. This semiconductor device is MOS
A transistor, which is a p-type or n-type semiconductor substrate 11 made of, for example, silicon (hereinafter, referred to as a substrate 11), is spaced apart from a region surrounded by the element isolation region 21 (specifically, a surface layer). It has a source region 12 and a drain region 13 as a pair of formed impurity regions, respectively. The source region 12 and the drain region 13 are formed from the surface of the substrate 11 in the depth direction, and have a depth of about 0.1 μm, for example. Note that the element isolation region 2
1 is made of, for example, silicon dioxide (SiO ₂ ).

Source region 12 and drain region 13
Are formed by introducing a first conductivity type impurity having a different conductivity type from that of the substrate 11 at a high concentration. For example, when the substrate 11 is p-type, arsenic (A
n-type impurities such as s) and phosphorus (P), and p-type impurities such as boron (B) when the substrate 11 is n-type. The type of the impurity of the first conductivity type may be the same or different between the source region 12 and the drain region 13. Further, as shown in FIG.
In the case where the well region 11a is formed in the surface layer portion of the P.1, the first conductivity type impurity introduced into the source region 12 and the drain region 13 when the well region 11a is p-type is n.
When the well region 11a is n-type, the first conductivity type impurity introduced therein becomes a p-type impurity.

On the surfaces of the source region 12 and the drain region 13, a silicide layer 12a having a thickness of, for example, 30 nm and made of a compound (silicide) of a refractory metal and silicon is formed in order to reduce the sheet resistance and the parasitic resistance. , 1
3a are respectively formed. A silicide layer 12a,
For example, cobalt silicide (CoSi ₂ ) or titanium silicide (Ti)
Si ₂ ).

In the inside (specifically, the surface layer) of the substrate 11 between the source region 12 and the drain region 13, the electric field near the drain is reduced adjacent to the source region 12 and the drain region 13, respectively. LDD region 14 for
15 are formed. These LDD regions 14, 1
5 are formed from the surface of the substrate 11 in the depth direction, for example, each having a depth of 0.0
It is about 7 μm. The LDD regions 14 and 15 are formed by introducing impurities of the first conductivity type at a lower concentration than the source region 12 and the drain region 13. The type of the first conductivity type impurity may be the same as or different from the source region 12 and the drain region 13.
The same applies between the DD regions 14 and 15.

The inside of the substrate 11 (specifically, near the surface) between the source region 12 and the drain region 13
A concentration adjusting region 16 is formed for adjusting the impurity concentration in the depth direction of 1 to suppress the short channel effect. The concentration adjustment region 16 is formed by introducing a second conductivity type impurity having the same conductivity type as the substrate 11. For example, when the substrate 11 is p-type, a p-type impurity such as boron is used, and when the substrate 11 is n-type, an n-type impurity such as arsenic or phosphorus is used.

The impurity concentration (the impurity concentration of the second conductivity type) of the concentration adjusting region 16 changes in the depth direction of the substrate 11 as shown in FIG. 3, for example. The impurity concentration in the concentration adjustment region 16 is, for example,
Above a certain value (for example, 1 × 10 ¹⁸ cm ⁻³ or more) in a region having a depth from the surface of 0.05 to 0.1 μm.
It has become. A region having a high impurity concentration in the concentration adjustment region 16 (for example, the maximum concentration of 1 in the concentration adjustment region 16).
Is preferably located closer to the front surface of the substrate 11 than the deepest portion of the source region 12 and the drain region 13 in the depth direction of the substrate 11. Even if the impurity of the second conductivity type is introduced over the source region 12 and the drain region 13 when forming the concentration adjustment region 16, the concentration of the impurity of the second conductivity type in the deepest part of the source region 12 and the drain region 13 Can be reduced, and the parasitic junction capacitance can be reduced.

On the substrate 11, for example, a thickness of 4 corresponds to a region between the source region 12 and the drain region 13.
through a gate insulating film 17 made of silicon dioxide (SiO ₂ ) having a thickness of, for example, 400 nm.
8 are formed. That is, the gate electrode 18 is formed to face the concentration adjustment region 16 so as to be sandwiched between the source region 12 and the drain region 13.

The gate electrode 18 has a two-layer structure laminated in the thickness direction (perpendicular to the surface) of the substrate 11, and has a thickness of, for example, 385 nm formed on the gate insulating film 17.
And a silicide layer 18b having a thickness of, for example, 30 nm formed on the silicon layer 18a. Silicon layer 18a
Is doped with impurities of the first conductivity type. The impurities of the first conductivity type may be different from or different from the source region 12, the drain region 13, and the LDD regions 14 and 15, respectively.

A side wall (side wall) 19 is formed on a side surface of the gate electrode 18. The side wall 19 in the present embodiment has a layered structure in which a plurality of layers are stacked in a direction substantially perpendicular to the side surface of the gate electrode 18. The portion has a conductive layer. Specifically, in order from the side of the gate electrode 18, for example, an oxide layer 19a as an insulating layer made of silicon dioxide having a width (thickness in a direction perpendicular to the side surface of the gate electrode 18) of 10 nm and a nitride layer having a width of 90 nm, for example. Silicon (S
a nitride layer 19b as an insulating layer made of i ₃ N ₄ ) and a silicon layer 19c as a conductive layer made of, for example, polycrystalline silicon or amorphous silicon having a width of 15 nm.
And a silicide layer 19d as a conductive layer made of silicide having a width of 30 nm, for example.

The first conductivity type impurity is introduced into the silicon layer 19c. The impurity of the first conductivity type may be different from or the same as the impurity of the other first conductivity type. The silicide layers 19 d are formed on the source region 12 and the drain region 13.
a and is electrically connected to the source region 12 or the drain region 13 through the silicide layers 12a and 13a, respectively. Note that the width of the side wall 19 is reduced from the surface side of the substrate 11 to the opposite side, and the width exemplified here is a width near the surface of the substrate 11.

The semiconductor device having such a configuration can be manufactured as follows.

4 (A) to 4 (C) to FIG. 6 (A) to
(C) shows the manufacturing method in the order of each step.
First, as shown in FIG. 4A, the surface of the substrate 11 made of silicon is, for example, reactive ion etching (Reacti etching).
The element isolation region 21 made of silicon dioxide is buried therein by, for example, a CVD (Chemical Vapor Deposition) method. Next, when the well region 11a is formed as shown in FIG. 2, an appropriate impurity is selectively implanted into the substrate 11, and the well region 1a is formed in a region surrounded by the element isolation region 21.
1a is formed.

Subsequently, as shown in FIG. 4B, a second conductivity type impurity is implanted into the entire surface of the substrate 11 surrounded by the element isolation region 21 to form a concentration adjusting region 16. 11 is oxidized by, for example, a thermal oxidation method to form a gate insulating film 17 having a thickness of, for example, 4 nm. When forming the concentration adjustment region 16, for example, when using boron as the impurity of the second conductivity type, implantation is performed with boron as the ion source, implantation energy of 30 KeV, and implantation amount of 6 × 10 ¹² cm ⁻² . For example, when arsenic is used as the second conductivity type impurity, the ion source is arsenic, the implantation energy is 100 KeV, and the implantation amount is 6 × 10 ¹² cm ^−2.
And perform the injection. After that, RTA (Rapid Thermal
Annealing) treatment to activate impurities and recover crystallinity.

After performing the RTA process, as shown in FIG. 4C, a silicon layer 18a made of polycrystalline silicon having a thickness of 150 nm is formed on the gate insulating film 17 by, for example, a CVD method. After that, an auxiliary layer 31 made of silicon dioxide having a thickness of 200 nm is formed on the silicon layer 18a by, for example, a CVD method. This auxiliary layer 31
This is for increasing the width of the side wall 19 when forming the side wall 19 on the side surface of the gate electrode 18 in a step described later.

After the formation of the auxiliary layer 31, as shown in FIG. 5A, the auxiliary layer 31 and the silicon layer 18a are selectively removed by using a lithography technique, and the gate electrode 1 is formed.
8 shape. Thereby, a part of the gate electrode 18 (the part of the silicon layer 18a) is formed. after that,
Using the auxiliary layer 31 and the gate electrode 18 as a mask, a first conductivity type impurity is implanted into the substrate 11 to form the LDD region 1.
4 and 15 are respectively formed. At this time, the impurity of the first conductivity type is implanted at a lower concentration than the source region 12 and the drain region 13 formed in the subsequent steps. For example, when arsenic is used as the first conductivity type impurity, the ion source is arsenic and the implantation energy is 10K.
The implantation is performed at an eV of 6 × 10 ¹⁴ cm ⁻² . When boron is used as the first conductivity type impurity, for example, the ion source is boron fluoride, the implantation energy is 10 KeV, and the implantation amount is 4 × 10 ¹⁴ cm ⁻² .

After the LDD regions 14 and 15 are formed, an oxide layer 19a having a thickness of 10 nm is formed on the entire surface by, eg, CVD.
Is formed thereon, and a thickness of 90 nm is formed thereon by, for example, a CVD method.
Is formed. After that, these nitride layers 1
9b and the oxide layer 19a are anisotropically etched to form the silicon layer 18a of the gate electrode 18 and the auxiliary film 31.
Remove leaving only the sides. Thereby, FIG. 5 (B)
As shown in the figure, the oxide layer 19a having a width of 10 nm and the
An insulating layer composed of a 0 nm nitride layer 19b is formed.
In addition, in etching when forming this insulating layer,
The gate insulating film 17 other than the portion covered with the insulating layer and the silicon layer 18a is also removed, exposing the surface of the substrate 11 in that portion.

After forming an insulating layer on the side surfaces of the silicon layer 18a and the auxiliary layer 31, a silicon layer 19c of polycrystalline silicon or amorphous silicon having a thickness of 30 nm is formed on the entire surface by, for example, a CVD method. Thereafter, this is removed by etch-back, leaving only the side surfaces of the insulating layer. As a result, as shown in FIG.
A silicon layer 19c having a width of 30 nm is formed.

After the formation of the silicon layer 19c, FIG.
As shown in FIG. 2A, a resist film 32 having a thickness of, for example, 500 nm is applied and formed on the entire surface. Expose. After that, for example, the auxiliary layer 31 is treated with a dilute hydrogen fluoride solution (for example, a solution in which water and hydrogen fluoride are mixed at a volume ratio of 20: 1) for 100 seconds.
Is removed.

After removing the auxiliary layer 31, as shown in FIG. 6B, the resist film 32 is removed by ashing, and the silicon layer 18a, the oxide layer 19a, the nitride layer 19b and the silicon layer 19c are used as masks. A first conductivity type impurity is introduced into the surface of the substrate 11 and the silicon layer 1
8a is also doped with a first conductivity type impurity. This allows
In the surface layer of the substrate 11, the source region 12 and the drain region 13 are formed in a self-aligned manner with the silicon layer 18a interposed therebetween. This also allows the silicon layer 19c to have the first
A conductivity type impurity is introduced. When introducing the impurity of the first conductivity type, for example, when arsenic is used as the impurity of the first conductivity type, the ion source is arsenic, the implantation energy is 60 KeV, and the implantation amount is 6 × 10 ¹⁵ cm ^−2. Do. For example, when using boron as the first conductivity type impurity, implantation is performed with boron ion as the ion source, implantation energy of 15 KeV, and implantation amount of 6 × 10 ¹⁵ cm ⁻² .

Here, since the silicon layer 19c is formed on the side surface of the nitride layer 19b, the silicon layer 19c is formed.
The width of the mask is increased by the width of c, and even if the implantation energy for implanting the impurity of the first conductivity type is increased, the width in the direction perpendicular to the depth direction of the source region 12 and the drain region 13 is increased. The width can be the same as before. Incidentally, the ion implantation conditions in the conventional method in which the silicon layer 19c is not formed are, for example, when the ion source is arsenic, the implantation energy is 30 KeV and the implantation amount is 5 × 1.
0 ¹⁵ cm ^-2 . For example, when the ion source is boron fluoride, the implantation energy is 2.5 KeV and the implantation amount is 5 × 10 ¹⁵ cm ⁻² . Therefore, here, the source region 12 and the drain region 13 are formed to a position deeper by the amount of the increased implantation energy.

After the impurity of the first conductivity type is thus introduced, RTA treatment (for example, heating at 1000 ° C. for 10 seconds) is performed to activate the impurity and recover the crystallinity. Thereafter, as shown in FIG. 6C, a metal layer 33 made of, for example, cobalt (Co) having a thickness of, for example, 10 nm is formed on the entire surface, and a heat treatment is performed, for example, at 550 ° C. for 10 seconds. A part of each of the drain region 13, the silicon layer 18a, and the silicon layer 19c reacts with the metal layer 33, respectively. Thereby, as shown in FIG.
Source region 12, drain region 13 and silicon layer 1
Silicide layers 12a, 13a, 18b, and 19d are formed on 8a and on side surfaces of silicon layer 19c, respectively. At this time, the silicide layers 12a and 13a and the silicide layer 19d are integrally formed. Thus, gate electrode 18 and side wall 19 in the present embodiment are formed.

After that, the unreacted portion of the metal layer 33 is removed using a mixed solution of sulfuric acid and hydrogen peroxide solution.
By performing the heat treatment at 700 ° C. for 30 seconds, FIG.
Is formed.

Such a semiconductor device is used, for example, as shown in FIG. 7, and operates as follows.

That is, an interlayer insulating film 22 made of silicon dioxide having a thickness of, for example, 0.9 μm is formed on the semiconductor device.
Is formed. This interlayer insulating film 22 has a source region 1
2, a contact hole 22b corresponding to the drain region 13, and a contact hole (not shown) corresponding to the gate electrode 18 are formed. In each of the contact holes 22a and 22b, for example, titanium nitride (TiN) having a thickness of 15 nm is buried, and then tungsten (W) is buried, so that the contact portions 23 and 24 are formed. The source region 12, the drain region 13 and the gate electrode 18 are connected to respective wirings (not shown) formed on the interlayer insulating film 22 via the respective contact portions 23 and 24.

In this semiconductor device, when a voltage is applied to gate electrode 18 via a contact portion (not shown), the current flowing between source region 12 and drain region 13 is modulated. Here, since the side wall 19 is provided with a conductive layer (silicon layer 19c and silicide layer 19d) on the outside, the contact portions 23 and 24 are provided as shown in FIG.
Is formed, the connection with the source region 12 or the drain region 13 is ensured via the conductive layer even if a part thereof overlaps with the side wall 19. Therefore, variation in contact resistance is reduced.

Here, since side wall 19 includes a conductive layer (silicon layer 19c and silicide layer 19d) in addition to the insulating layer (oxide layer 19a and nitride layer 19b), source region 12 and drain region 13 A contact area with the contact portions 23 and 24 is ensured, and the side wall 19
Is thicker. Therefore, the source region 12 and the drain region 13 can be formed using large implantation energy, and the source region 12 and the drain region 13 are formed to a deep position. That is, the concentration of the impurity of the second conductivity type (concentration adjustment region 16) in the deepest portion is low, the parasitic junction capacitance is small, and a high current value is obtained.

As described above, in the semiconductor device according to the present embodiment, the side wall 19 having the conductive layer (silicon layer 19c and silicide layer 19d) is provided outside the gate electrode 18, so that the contact portion 23, 24
Even if the contact portions 23 and 24 partially overlap with the side wall 19 due to a shift in the formation position, the connection with the source region 12 or the drain region 13 can be secured via the conductive layer, and the contact resistance varies. Can be reduced.

Further, in particular, the silicide layer 1 is used as the conductive layer.
9d, the resistance can be reduced, and the variation in contact resistance can be further reduced.

Further, in the present embodiment, the gate electrode 18
Of the insulating layer (the oxide layer 19a and the nitride layer 19)
Since a conductive layer (silicon layer 19c and silicide layer 19d) is provided in addition to b), the source region 12
In addition, the thickness of the side wall 19 can be increased while ensuring a contact area between the drain region 13 and the contact portions 23 and 24. Therefore, even if a large implantation energy is used when forming the source region 12 and the drain region 13,
The source region 12 and the drain region 13 can be formed to a deep position without changing the width in the depth direction and the vertical direction. That is, the deepest part of the source region 12 and the drain region 13 is set to a position deeper than a region in the concentration adjusting region 16 where the concentration of the impurity of the second conductivity type is high (for example, a region of half or more of the maximum concentration). it can. That is, when forming the density adjustment region 16, the second
Even if the conductivity type impurity is introduced into the entire surface, the concentration of the second conductivity type impurity at the deepest part of the source region 12 and the drain region 13 can be reduced. Therefore, the parasitic junction capacitance can be reduced while suppressing the short channel effect.

In addition, according to the method of manufacturing a semiconductor device according to the present embodiment, side wall 19 having a conductive layer (silicon layer 19c and silicide layer 19d) is formed on the side surface of silicon layer 18a. The semiconductor device according to the present embodiment can be easily formed.

Further, after an oxide layer 19a, a nitride layer 19b and a silicon layer 19c are formed on the side surfaces of the silicon layer 18a, impurities of the first conductivity type are introduced into the substrate 11 by using these as a mask to form the source region 12 and the drain. Since the region 13 is formed, the width of the mask can be increased by the thickness of the silicon layer 19c, and the implantation energy for implanting the impurity of the first conductivity type can be increased. Therefore, the source region 12 and the drain region 1
The deepest part of No. 3 can be located deeper than a region where the concentration of the impurity of the second conductivity type is high.

In addition, an oxide layer 19a, a nitride layer 19b, and a silicon layer 19c are formed on the side surfaces of the silicon layer 18a, and the source region 12 and the drain region 13 are formed using these as masks. Formed and heated, the silicide layers 12a, 13a, 18b, 1
9d, the respective silicide layers 12a, 13a, 18b and 19d can be easily formed in one step, and the silicide layers 12a and 13d can be formed easily.
a and the silicide layer 19d can be integrally formed, and the contact resistance can be reduced.

In order to examine the effect of the semiconductor device according to the present embodiment, the semiconductor device (N-channel MOS
Transistor) was formed, and the junction capacitance and the contact resistance of the source region 12 and the drain region 13 at an area of 1.0 μm ² were measured. Table 1 shows the results.

[0046] A similar experiment was performed on the conventional semiconductor device shown in FIG. 8 (a device without the silicon layer 19c and the silicide layer 19d on the side wall 19).
5fF and the contact resistance is 0.3
When it was 0 μm, it was 5.0 to 10.1 Ω, and when it was 0.26 μm, it was 7.0 to 12.0 Ω. That is, according to the semiconductor device of the present embodiment, it has been found that the junction capacitance can be reduced and the variation in contact resistance can be reduced.

As described above, the present invention has been described with reference to the embodiments. However, the present invention is not limited to these embodiments, and can be variously modified. For example, in the above embodiment, the conductive layer (silicon layer 19c and silicide layer 19d) on the side wall 19 is formed on the entire side surface of the insulating layer (oxide layer 19a and nitride layer 19b). May be formed.

In the above embodiment, the side wall 1
9 is a silicon layer 19c and a silicide layer 19 as conductive layers.
d, but only one of them may be used. However, since the resistance of the silicide layer 19d is lower,
The silicide layer 19d is more preferable.

Further, in the above-described embodiment, the concentration adjusting region 16 is formed in the entire region between the source region 12 and the drain region 13, but the substrate between the source region 12 and the drain region 13 is formed. In the vicinity of the surface of the semiconductor substrate 11, it may be formed partially at the boundary between the source region 12 and the drain region 13 and at the boundary between the LDD regions 14 and 15. Further, the density adjustment region is set to the source region 1.
It may be formed in the entire region between the second region 2 and the drain region 13 and may be partially formed as described above. Thus, the source region 12 and the drain region 1
In the case where the concentration adjustment region is formed at the boundary between the gate electrode 18 and the LDD regions 14 and 15,
After forming the silicon layer 18a constituting the electrode into an electrode shape, the second conductivity type impurity may be introduced into the substrate 11 before the sidewalls 19 (the oxide layer 19a and the nitride layer 19b) are formed.

[0050]

As described above, according to the semiconductor device of the present invention, since the side wall having the conductive layer is provided on the outer portion, the contact portion is formed, for example, when the contact portion is formed near the electrode. Even if the formation position shifts and the side wall partially overlaps, the connection can be secured through the conductive layer. Therefore, there is an effect that variation in contact resistance can be reduced.

Further, since a stable connection of the contact portion can be ensured by the conductive layer, the side wall can be made thicker by the amount of the conductive layer. For example, when an impurity region is formed by using the side wall as a mask, the impurity has a large energy. Even if the impurity region is introduced, the impurity region can be formed to a deep position without changing the width in the direction perpendicular to the depth direction. Therefore, for example, even when the concentration adjustment region is formed, the concentration of the impurity of the second conductivity type at the deepest portion of the impurity region can be reduced,
There is also an effect that the parasitic junction capacitance can be reduced.

Further, according to the method of manufacturing a semiconductor device of the present invention, since the side wall having the conductive layer is formed on the side surface of the electrode, the semiconductor device of the present invention can be easily formed. In particular, if a sidewall having a conductive layer is formed on the side surface of the electrode, and then the impurity region is formed using the sidewall as a mask, the width of the mask can be increased by the amount of the conductive layer and impurities are introduced. Energy at the time can be increased. Therefore, even when the concentration adjusting region for suppressing the short channel effect is formed, the deepest portion of the impurity layer can be located at a position deeper than the region where the concentration of the impurity of the second conductivity type is high. The semiconductor device of the present invention can be easily realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a modification of the semiconductor device illustrated in FIG.

FIG. 3 is a characteristic diagram illustrating a second conductivity type impurity concentration distribution in a depth direction in a concentration adjustment region of the semiconductor device illustrated in FIG. 1;

FIG. 4 is a cross-sectional view illustrating each manufacturing process of the semiconductor device illustrated in FIG.

FIG. 5 is a sectional view illustrating each manufacturing step following FIG. 4;

FIG. 6 is a sectional view illustrating each manufacturing step following FIG. 5;

FIG. 7 is a sectional view for explaining the operation of the semiconductor device shown in FIG. 1;

FIG. 8 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

[Explanation of symbols]

11 ... substrate, 11a ... well region, 12 ... source region (impurity region), 12a, 13a, 18b, 19d ... silicide layer, 13 ... drain region (impurity region), 1
4, 15: LLD region, 16: concentration adjusting region, 17: gate insulating film (insulating layer), 18: gate electrode (electrode), 1
8a, 19c silicon layer, 19 side wall, 19a oxide layer, 19b nitride layer, 21 element isolation region, 22 interlayer insulating film, 23, 24 contact part, 31 auxiliary layer, 3
2. Resist film

Claims (14)

[Claims] 1. An electrode formed on a surface of a semiconductor substrate and having a side surface along a thickness direction of the semiconductor substrate, and a conductive layer formed on a side surface of the electrode and at least part of an outer portion. A semiconductor device comprising a side wall. 2. The semiconductor device according to claim 1, wherein said side wall has an insulating layer inside. 3. The semiconductor device according to claim 1, wherein said conductive layer has a silicide layer. 4. A semiconductor substrate further comprising a pair of impurity regions formed by introducing an impurity of a first conductivity type so as to sandwich the electrode inside the semiconductor substrate, and the electrode has an insulating film on a surface of the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein said conductive layer is electrically connected to said pair of impurity regions. 5. The semiconductor device according to claim 1, further comprising a silicide layer provided on a surface of each of said pair of impurity regions, and wherein said conductive layer is electrically connected to said pair of impurity regions via said silicide layers. The semiconductor device according to claim 4, wherein 6. The semiconductor device according to claim 4, further comprising a concentration adjusting region formed by introducing an impurity of a second conductivity type corresponding to said electrode inside said semiconductor substrate. . 7. A semiconductor device according to claim 1, wherein a region of the concentration adjusting region having an impurity concentration equal to or more than の of a maximum concentration thereof is located closer to a surface than a deepest portion of the impurity region in a depth direction of the semiconductor substrate. 7. The semiconductor device according to claim 6, wherein: 8. A step of forming an electrode having a side surface along a thickness direction of the semiconductor substrate on a surface of the semiconductor substrate; and forming a side wall having a conductive layer on at least a part of an outer portion on the side surface of the electrode. Forming a semiconductor device. 9. The step of forming a side wall on the side surface of the electrode, the step of forming an insulating layer on the side surface of the electrode, the step of forming the insulating layer on the side surface of the electrode, and at least a part of the side surface of the insulating layer 9. The method for manufacturing a semiconductor device according to claim 8, further comprising the step of forming a conductive layer. 10. The step of forming a side wall including the conductive layer includes: forming a silicon layer on at least a part of a side surface of the insulating layer; and forming a metal layer on the side surface of the silicon layer after forming the silicon layer. 10. The method of manufacturing a semiconductor device according to claim 9, further comprising the step of forming a layer and heating to react at least a part of the silicon layer with the metal layer to form a silicide layer. 11. The method according to claim 11, further comprising the step of selectively introducing an impurity of the first conductivity type into the semiconductor substrate to form a pair of impurity regions, respectively. Formed over the insulating layer,
9. The method of manufacturing a semiconductor device according to claim 8, wherein in the step of forming the side wall, the conductive layer is formed by being electrically connected to the pair of impurity regions. 12. The step of forming the side wall includes forming an insulating layer on a side surface of the electrode, forming a silicon layer on at least a part of the side surface of the insulating layer, and forming a silicon layer on the side surface of the silicon layer. Forming a metal layer, heating and reacting at least a portion of the silicon layer with the metal layer to form a silicide layer, and forming the pair of impurity regions. After that, before forming the silicide layer, a pair of impurity regions are respectively formed using the electrode, the insulating layer, and the silicon layer as a mask, and further, simultaneously with forming the silicide layer on the side wall, a pair of impurity regions are formed. 12. The semiconductor according to claim 11, further comprising a step of forming a metal layer, heating and causing a part of the metal layer to react with the metal layer, and forming a silicide layer. Device manufacturing method. 13. The method according to claim 8, further comprising the step of introducing a second conductivity type impurity into the semiconductor substrate to form a concentration adjusting region. 14. The method for manufacturing a semiconductor device according to claim 13, wherein an electrode is formed after forming the concentration adjusting region.