JP2005072418A - 電子部品封止用基板およびそれを用いた電子装置の製造方法 - Google Patents
電子部品封止用基板およびそれを用いた電子装置の製造方法 Download PDFInfo
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- JP2005072418A JP2005072418A JP2003302416A JP2003302416A JP2005072418A JP 2005072418 A JP2005072418 A JP 2005072418A JP 2003302416 A JP2003302416 A JP 2003302416A JP 2003302416 A JP2003302416 A JP 2003302416A JP 2005072418 A JP2005072418 A JP 2005072418A
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- Prior art keywords
- electronic component
- main surface
- substrate
- frame member
- sealing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
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- Micromachines (AREA)
Abstract
【解決手段】 一方主面から他方主面または側面に導出された配線導体2が形成された絶縁基板1と、絶縁基板1の一方主面に形成された、配線導体2と接続された接続パッド3と、絶縁基板1の一方主面に、接続パッド3を取り囲むようにして接合された枠部材4と、接続パッド3上に形成された、枠部材4と同じ高さの接続端子5とから成り、半導体基板7の主面に微小電子機械機構8およびこれに接続された電極9が形成された電子部品10が、電極9を接続端子5に接合し、半導体基板7の主面を枠部材4の主面に接合されることによって、枠部材4の内側に電子部品10の微小電子機械機構8を気密封止するとともに、配線導体2の少なくとも一部がフェライトを含んで成る。
【選択図】 図1
Description
2:配線導体
3:接続パッド
4:枠部材
5:接続端子
6:電子部品封止用基板
6a:電子部品封止領域
6b:電子部品封止用基板
7:半導体基板
8:微小電子機械機構
9:電極
10:電子部品
10a:電子部品領域
10b:電子部品
Claims (3)
- 一方主面から他方主面または側面に導出された配線導体が形成された絶縁基板と、該絶縁基板の前記一方主面に形成された、前記配線導体と電気的に接続された接続パッドと、前記絶縁基板の前記一方主面に前記接続パッドを取り囲むようにして接合された枠部材と、前記接続パッド上に形成された、前記枠部材と同じ高さの接続端子とから成り、半導体基板の主面に微小電子機械機構およびこれに電気的に接続された電極が形成されて成る電子部品が、前記電極が前記接続端子に接合され、前記半導体基板の前記主面を前記枠部材の主面に接合されることによって、前記枠部材の内側に前記電子部品の前記微小電子機械機構を気密封止するとともに、前記配線導体の少なくとも一部がフェライトを含んで成ることを特徴とする電子部品封止用基板。
- 前記接続パッドおよび前記接続端子が内側に形成された前記枠部材が多数個縦横に配列形成されていることを特徴とする請求項1記載の電子部品封止用基板。
- 半導体基板の主面に、微小電子機械機構およびこれに電気的に接続された電極が形成されて成る電子部品領域を多数個縦横に配列形成した電子部品を準備する工程と、一方主面から他方主面または側面に導出された配線導体が形成された絶縁基板と、該絶縁基板の前記一方主面に形成された、前記配線導体と電気的に接続された接続パッドと、前記絶縁基板の前記一方主面に前記接続パッドを取り囲むようにして接合された枠部材と、前記接続パッド上に形成された、前記枠部材と同じ高さの接続端子とから成る電子部品封止領域を多数個前記電子部品の前記電子部品領域に対応させて配列形成した電子部品封止用基板を準備する工程と、前記電子部品における前記電極を前記接続端子に接合するとともに前記微小電子機械機構の周囲の前記半導体基板の前記主面を前記枠部材の主面に接合して前記微小電子機械機構を前記枠部材の内側に気密封止する工程と、互いに接合された前記電子部品および前記電子部品封止用基板を前記電子部品封止領域毎に分割して、前記電子部品封止領域に前記電子部品領域が接合されて成る個々の電子装置を得る工程とを具備することを特徴とする電子装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2003302416A JP4116954B2 (ja) | 2003-08-27 | 2003-08-27 | 電子部品封止用基板およびそれを用いた電子装置 |
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JP2003302416A JP4116954B2 (ja) | 2003-08-27 | 2003-08-27 | 電子部品封止用基板およびそれを用いた電子装置 |
Publications (3)
Publication Number | Publication Date |
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JP2005072418A true JP2005072418A (ja) | 2005-03-17 |
JP2005072418A5 JP2005072418A5 (ja) | 2006-11-30 |
JP4116954B2 JP4116954B2 (ja) | 2008-07-09 |
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JP2003302416A Expired - Fee Related JP4116954B2 (ja) | 2003-08-27 | 2003-08-27 | 電子部品封止用基板およびそれを用いた電子装置 |
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JP (1) | JP4116954B2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006300976A (ja) * | 2005-04-15 | 2006-11-02 | Fujitsu Ltd | マイクロ可動素子および光スイッチング装置 |
JP2007147409A (ja) * | 2005-11-25 | 2007-06-14 | Matsushita Electric Works Ltd | センサエレメント |
JP2010071911A (ja) * | 2008-09-22 | 2010-04-02 | Alps Electric Co Ltd | Memsセンサ |
-
2003
- 2003-08-27 JP JP2003302416A patent/JP4116954B2/ja not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006300976A (ja) * | 2005-04-15 | 2006-11-02 | Fujitsu Ltd | マイクロ可動素子および光スイッチング装置 |
JP4550653B2 (ja) * | 2005-04-15 | 2010-09-22 | 富士通株式会社 | マイクロ可動素子および光スイッチング装置 |
JP2007147409A (ja) * | 2005-11-25 | 2007-06-14 | Matsushita Electric Works Ltd | センサエレメント |
JP4665733B2 (ja) * | 2005-11-25 | 2011-04-06 | パナソニック電工株式会社 | センサエレメント |
JP2010071911A (ja) * | 2008-09-22 | 2010-04-02 | Alps Electric Co Ltd | Memsセンサ |
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JP4116954B2 (ja) | 2008-07-09 |
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