JP2005064995A - Frequency divider - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress jitter occurring internally without increasing power consumption. <P>SOLUTION: A synchronization compensation circuit 1-2 is provided on the poststage of a frequency divider 1-1. A master clock is inputted to a branch of the synchronization compensation circuit 1-2. The synchronization compensation circuit 1-2 takes an operating state only during a time band of one period of the master clock centering about a point where level change of a frequency divided signal from the frequency divider 1-1 is predicted and takes a holding state during other time bands. Consequently, power consumption is minimized and jitter occurring internally can be suppressed without increasing power consumption. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a frequency dividing device that divides a high-speed clock signal (master clock) and outputs a signal having a desired frequency (frequency-divided output).

  Conventionally, there is a synthesizer circuit as shown in FIG. 15 as an example using this type of frequency divider (see Non-Patent Document 1). The synthesizer circuit includes a reference oscillator 101, a frequency divider 102, a phase comparator 103, a charge pump 104, a loop filter 105, an oscillator (VCO) 106, and a pulse / swallow type frequency divider 107. ing.

  The pulse swallow type frequency divider 107 divides the input master clock by the frequency division number programmed from the outside, and supplies it to the phase comparator 103 as a frequency division output. The pulse swallow type frequency divider 107 corresponds to a frequency divider.

  Since this synthesizer circuit can control the oscillation frequency of the oscillator 106 to be an integer multiple of the reference oscillator 101 accurately, it is used as an oscillation circuit of a wireless communication device such as a cellular phone.

"CMOS analog circuit design technology", published by Trikes, Inc., issued November 13, 1988, page 226.

  In the synthesizer circuit described above, when jitter is generated inside the pulse / swallow type frequency divider (frequency divider) 107, it directly affects the phase noise of the frequency-divided output to the phase comparator 103. As a method for suppressing the jitter generated in the frequency divider 107, for example, it is conceivable to operate all the circuits (prescaler, counter, etc.) in the frequency divider 107 in synchronization with the master clock. However, if all the circuits in the frequency divider 107 are operated in synchronism with the master clock, the circuit scale becomes enormous due to the operation with the high-speed master clock, and the power consumption increases remarkably. It was.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a frequency divider that can suppress jitter generated inside without increasing power consumption. is there.

In order to achieve such an object, the present invention divides a master clock and outputs a divided signal as a divided signal, and outputs a divided signal from the divider by a predetermined amount with respect to the master clock. A synchronization compensation circuit that takes in synchronization with the shifted master clock for synchronization compensation and outputs it as a frequency-divided output, and the synchronization compensation circuit starts from the point where the level of the signal after frequency division is expected to be displaced. An operation state in which the level of the frequency-divided signal is captured in synchronization with the synchronization compensation master clock only during a predetermined time period, and a retention state in which the captured level is retained is set in other time periods.
According to the present invention, the master clock is frequency-divided by the frequency divider and supplied to the synchronous compensation circuit as a frequency-divided signal. The synchronization compensation circuit takes in the frequency-divided signal from the frequency divider in synchronization with the synchronization compensation master clock (a clock whose phase is shifted by a predetermined amount with respect to the master clock), and outputs it as a frequency-divided output. At this time, the synchronization compensation circuit is in an operating state only in a predetermined time zone starting from a point at which the level of the divided signal is expected to be displaced, and the level of the divided signal is synchronized with the master clock for synchronization compensation. take in. In other time zones, the state is held, and the captured level is held.

  For example, a clock whose quarter cycle phase is delayed with respect to the master clock is used as a synchronization compensation master clock, and the level of the frequency-divided signal is taken in when the synchronization compensation master clock rises to the “H” level. To do. In this case, even if the rising edge of the divided signal to the “H” level fluctuates back and forth by a quarter period (a total of 1/2 period) due to jitter, for example, if the level of the divided signal rises to the “H” level Since the level of the divided signal is taken in when the master clock for synchronization compensation rises to “H” level after a ¼ period delay from the expected point, the influence of jitter does not appear on the divided output. Become. Similarly, even if the falling edge of the divided signal to the “L” level fluctuates forward and backward by a quarter period (a total of 1/2 period) due to jitter, the divided signal level rises to the “L” level. Since the level of the frequency-divided signal is captured when the synchronization compensation master clock rises to the “H” level with a delay of ¼ period from the point where it is expected to decrease, the influence of jitter does not appear on the frequency-divided output. It will be a thing. Further, the synchronization compensation circuit has a predetermined time zone starting from a point at which the level of the divided signal is expected to be displaced, for example, one period of the master clock centering on a point at which the level of the divided signal is expected to be displaced. Since only the minute time zone is activated, power consumption is negligible.

  The predetermined time period starting from the point at which the level of the signal after frequency division is expected to be displaced, that is, the time period in which the synchronous compensation circuit is in the operating state, is not limited to the time period for one cycle. In practice, it is quite difficult to set the operating state in the time period for one cycle. On the other hand, if the displacement of the signal after frequency division can be accurately predicted to that extent, the final output can be made only by the prediction and the master clock. In other words, it can be said that the high-precision prediction up to that point is generally equivalent to the function of the frequency divider, and if the prediction is accurate, the meaning of the present application is almost lost. Therefore, the point where the level of the signal after the frequency division is expected to be displaced should be considered to be inaccurate, and the time zone in which the synchronous compensation circuit is in the operating state is set to two cycles or more rather than one cycle. Is more realistic. Even when the time period of two cycles or more is set to the operating state, the power consumption is extremely small because it operates only for a sufficiently short time compared to the case of continuous operation.

In the present invention, the master clock for synchronization compensation may be generated internally by supplying the master clock to the synchronization compensation circuit, or may be generated externally and provided to the synchronization compensation circuit.
In addition, the synchronization compensation master clock is continuously generated, and the divided signal is synchronized with the synchronization compensation master clock only in a predetermined time period starting from a point where the level of the divided signal is expected to be displaced. The level may be taken in, or a synchronization compensation master clock is generated only in a predetermined time period starting from a point where the level of the divided signal is expected to be displaced, and the synchronization compensation is generated only in the predetermined time period. The level of the frequency-divided signal may be captured in synchronization with the master clock.
In addition, the predetermined time zone starting from the point at which the level of the divided signal is expected to shift may be known within the synchronization compensation circuit by counting the master clock, or by counting the master clock. You may make it notify a synchronous compensation circuit from the outside.

Further, the predetermined time period starting from the point at which the level of the divided signal is expected to be displaced may be determined only in the delay direction starting from the point at which the level of the divided signal is expected to be displaced.
In addition, the frequency-divided signal from the frequency divider is not captured in synchronization with the synchronization compensation master clock whose phase is shifted by a predetermined amount with respect to the master clock. The synchronous compensation frequency-divided signal whose quantitative phase is shifted may be captured in synchronization with the master clock. In this case, the synchronization compensation circuit is activated only during a predetermined time period starting from the point at which the level of the signal after frequency division for synchronization compensation is expected to be displaced, and the synchronization compensation circuit is maintained in the other time period. .

  According to the present invention, the synchronization compensation circuit is activated only during a predetermined time period starting from the point at which the level of the frequency-divided signal is expected to be displaced, and the synchronization compensation circuit is maintained in the remaining state during other time periods. As a result, power consumption in the synchronous compensation circuit becomes extremely small, and jitter generated inside can be suppressed without increasing power consumption.

Hereinafter, the present invention will be described in detail with reference to the drawings.
[Embodiment 1]
FIG. 1 is a schematic configuration diagram showing the main part of an embodiment of a frequency divider according to the present invention. The frequency dividing device 1 divides the master clock and outputs the divided signal as a post-divided signal, and the master clock to the frequency divider 1-1 is used as a branch input. A synchronization compensation master clock with a delay of / 4 cycle phase is generated, and the frequency-divided signal from the frequency divider 1-1 is fetched in synchronization with the generated synchronization compensation master clock and output as a frequency-divided output. And a compensation circuit 1-2.

  Further, in the present embodiment, the synchronization compensation circuit 1-2 is a time zone for one cycle of the master clock centered on the point where the level of the frequency-divided signal from the frequency divider 1-1 is expected to be displaced. Only in the operating state (the state where the divided signal level is captured in synchronization with the master clock for synchronization compensation), and the remaining time zone is in the retaining state (the state where the captured level is retained). Yes.

  FIG. 3 shows a time chart showing the operation of the frequency dividing device 1. 3A is a master clock for the frequency divider 1-1 and the synchronization compensation circuit 1-2, FIG. 3B is a master clock for synchronization compensation generated in the synchronization compensation circuit 1-2, and FIG. (C) is a frequency-divided signal output from the frequency divider 1-1, and FIG. 3 (d) is a frequency-divided output output from the synchronous compensation circuit 1-2.

  In FIG. 3, for the sake of simplicity, the frequency divider 1-1 is described as having no delay time. When considering the delay time of the frequency divider 1-1, the time axis for the frequency-divided signal may be read as being delayed by the delay time of the frequency divider 1-1. The same concept applies to the timing charts in the following description.

  The master clock to the frequency divider 1 has a period Tck and is supplied to the frequency divider 1-1 and the synchronous compensation circuit 1-2. The frequency divider 1-1 divides the input master clock by a predetermined frequency and outputs it as a signal after frequency division. This frequency-divided signal is input to the synchronous compensation circuit 1-2 as a signal having a jitter Tj generated in the frequency divider 1-1.

  The synchronization compensation circuit 1-2 uses the master clock to the frequency divider 1-1 as a branch input, and generates a synchronization compensation master clock with a quarter cycle phase delayed from the master clock. Further, the synchronization compensation circuit 1-2 counts the master clock, determines a point P1 where the level of the frequency-divided signal from the frequency divider 1-1 is expected to be shifted to the “H” level, and determines this point P1. Only the time period TM (TM = Tck) corresponding to one cycle of the master clock as the center is in an operating state. In this operation state, the synchronization compensation circuit 1-2 captures the level of the frequency-divided signal from the frequency divider 1-1 at the rising edge of the synchronization compensation master clock to the “H” level.

[Time zone TM1]
The synchronization compensation circuit 1-2 counts the master clock, determines a point P1 at which the level of the frequency-divided signal from the frequency divider 1-1 is expected to shift to the “H” level, and centered on this point P1. In the time zone TM1 (TM1 = Tck) for one cycle of the master clock to be operated, the operation state is set.

  Here, it is assumed that the rising point of the frequency-divided signal to the “H” level fluctuates by a quarter period (Tj = Tck / 2) due to jitter. In this case, the synchronization compensation master clock rises to the “H” level at a point P2 delayed by Tck / 4 from the point P1 at which the level of the frequency-divided signal is expected to shift to the “H” level. After being divided, the level of the signal is taken in and used as a divided output. At point P2, the frequency-divided signal contains no jitter, and the frequency-divided output changes from the “L” level to the “H” level. As a result, the rising point of the frequency-divided output to the “H” level is synchronized with the master clock for synchronization compensation, and jitter does not occur.

  The synchronous compensation circuit 1-2 enters an operation state in a time zone TM1 corresponding to one cycle of the master clock centered on the point P1, and then switches to a holding state that holds the fetched level. Thereby, the frequency-divided output that has changed from the “L” level to the “H” level at the point P2 maintains the “H” level state.

[Time zone TM2]
Next, the synchronization compensation circuit 1-2 counts the master clock, determines the point P3 where the level of the frequency-divided signal from the frequency divider 1-1 is expected to be shifted to the “L” level, and this point P3 In the time zone TM2 (TM2 = Tck) for one cycle of the master clock centering on, the operation state is entered.

  Here, it is assumed that the time when the divided signal falls to the “L” level fluctuates back and forth by a quarter period (Tj = Tck / 2) due to jitter. In this case, the synchronization compensation master clock rises to the “H” level at the point P4 delayed by Tck / 4 from the point P3 where the level of the frequency-divided signal is expected to be shifted to the “L” level. After being divided, the level of the signal is taken in and used as a divided output. At point P4, the frequency-divided signal contains no jitter, and the frequency-divided output changes from the “H” level to the “L” level. As a result, the falling point of the frequency-divided output to the “L” level is synchronized with the master clock for synchronization compensation, and jitter does not occur.

  The synchronization compensation circuit 1-2 enters an operation state in a time zone TM2 corresponding to one cycle of the master clock centered on the point P3, and then switches to a holding state that holds the fetched level. As a result, the frequency-divided output that has changed from the “H” level to the “L” level at the point P4 maintains the “L” level state.

  As can be understood from the above description, in the frequency dividing device 1, the synchronization compensation circuit 1-2 is operated in the time zone TM corresponding to one period of the master clock centered on the point where the level of the frequency-divided signal is expected to be displaced. However, since it is in an operating state and is in a holding state during other time periods, power consumption is negligible. As a result, it is possible to suppress jitter generated inside without increasing the power consumption.

  In the first embodiment, the synchronization compensation circuit 1-2 is in an operating state only in a time period corresponding to one cycle of the master clock centering on a point where the level of the divided signal is expected to be displaced. It is quite difficult to set the operating state in a time period for one cycle. On the other hand, if the displacement of the signal after frequency division can be accurately predicted to that extent, the final output can be made only by the prediction and the master clock. In other words, it can be said that the high-precision prediction up to that point is almost equivalent to the operation of the frequency divider 1-1, and if the prediction is accurate, the meaning of the present application is almost lost. Therefore, the point where the level of the signal after the frequency division is expected to be displaced should be considered to be inaccurate, and the time zone in which the synchronous compensation circuit 1-2 is in the operating state is equal to two periods rather than one period. The above is more realistic. Even when the time period of two cycles or more is set to the operating state, the power consumption is extremely small because it operates only for a sufficiently short time compared to the case of continuous operation.

[Embodiment 2]
FIG. 2 is a schematic configuration diagram showing a main part of another embodiment of the frequency divider according to the present invention. The frequency dividing device 2 divides the master clock and outputs the divided signal as a divided signal, and the master clock to the frequency divider 2-1 is used as a branch input. A synchronization compensation master clock with a delay of / 4 cycle phase is generated, and the frequency-divided signal from the frequency divider 2-1 is taken in synchronization with the generated synchronization compensation master clock and output as a frequency-divided output. And a compensation circuit 2-2.

  In the second embodiment, the frequency divider 2-1 includes a first frequency divider 2-11 and a second frequency divider (counter) 2-12, and the first frequency divider 2-11. 1, the master clock is frequency-divided and applied to the second frequency divider 2-12 as a frequency-divided signal A. The frequency-divided signal A is further frequency-divided by the second frequency divider 2-12 and the frequency-divided signal B Is provided to the synchronous compensation circuit 2-2. As the first frequency divider 2-11, a 2-modulus prescaler that operates at high speed can be used, and as the second frequency divider 2-12, a programmable counter or the like can be used.

  Further, the second frequency divider 2-12 counts the rising of the frequency-divided signal A to the “H” level, and outputs an “H” level forecast signal to the synchronous compensation circuit 2-2. The synchronization compensation circuit 2-2 is informed of a time zone centered around a point where the level of the signal B after the frequency division is expected to be displaced (in this example, a time zone of 3 counts).

  Further, the synchronization compensation circuit 2-2 operates only in a time zone in which the prediction signal from the frequency divider 2-1 is at the “H” level (the level of the divided signal B is synchronized with the master clock for synchronization compensation). In other words, it is configured to be in a holding state (a state in which the acquired level is held).

  FIG. 4 shows a time chart showing the operation of the frequency divider 2. 4A is a master clock for the frequency divider 2-1 and the synchronization compensation circuit 2-2, FIG. 4B is a master clock for synchronization compensation generated in the synchronization compensation circuit 2-2, and FIG. (C) is a frequency-divided signal A output from the first frequency divider 2-11, FIG. 4 (d) is a forecast signal output from the second frequency divider 2-12, and FIG. 4 (e). Is a frequency-divided signal B output from the second frequency divider 2-12, and FIG. 4F is a frequency-divided output output from the synchronous compensation circuit 2-2.

  The master clock to the frequency divider 2 is supplied to the frequency divider 2-1 and the synchronization compensation circuit 2-2. In the frequency divider 2-1, the first frequency divider 2-11 divides the input master clock by a predetermined frequency division number and outputs it as a frequency-divided signal A. This frequency-divided signal A is supplied to the second frequency divider 2-12.

  The second frequency divider 2-12 further divides the input divided signal A and outputs it as a divided signal B. This frequency-divided signal B is input to the synchronous compensation circuit 2-2 as a signal having a jitter Tj generated in the frequency divider 2-1.

  The second frequency divider 2-12 counts the rising of the frequency-divided signal A to the “H” level, and provides the above-described forecast signal to the synchronization compensation circuit 2-2. In this example, the frequency divider 2-12 raises the prediction signal to the synchronous compensation circuit 2-2 to the “H” level when the rising of the divided signal A to the “H” level is counted N−1 times. , N + 1 counts, the forecast signal to the synchronous compensation circuit 2-2 falls to the “L” level. The frequency divider 2-12 raises the divided signal B to the “H” level every time the rising of the divided signal A to the “H” level is counted N times.

  The synchronization compensation circuit 2-2 receives the master clock to the frequency divider 2-1 as a branch input, and generates a synchronization compensation master clock having a quarter cycle phase delayed from the master clock. Further, the synchronous compensation circuit 2-2 is in an operating state only during the time zone TM (TM = 4 Tck) in which the prediction signal from the frequency divider 2-1 is at the “H” level. In this operating state, the synchronization compensation circuit 2-2 captures the level of the frequency-divided signal B from the frequency divider 2-1 at the rising edge of the synchronization compensation master clock to the “H” level.

[Time zone TM2]
The frequency divider 2-12 raises the prediction signal to the synchronous compensation circuit 2-2 to the “H” level at the time point P1 when the rising of the divided signal A to the “H” level is counted N−1 times. At the time point P3 counted N + 1 times, the prediction signal to the synchronous compensation circuit 2-2 is lowered to the “L” level. The synchronous compensation circuit 2-2 receives the prediction signal from the frequency divider 2-12, and is in an operating state while the prediction signal is at the “H” level, that is, during the time zone TM2.

  Here, it is assumed that the rising point of the frequency-divided signal B to the “H” level fluctuates back and forth by a quarter period (Tj = Tck / 2) due to jitter. In this case, the synchronization compensation master clock rises to the “H” level at a point P4 delayed by Tck / 4 from the point P2 at which the level of the frequency-divided signal is expected to shift to the “H” level. After being divided, the level of the signal B is fetched and used as a divided output. At point P4, the frequency-divided signal B does not contain jitter, and the frequency-divided output changes from the “L” level to the “H” level. As a result, the rising point of the frequency-divided output to the “H” level is synchronized with the master clock for synchronization compensation, and jitter is not included.

  When the forecast signal from the frequency divider 2-12 becomes “L” level, the synchronization compensation circuit 2-2 switches from the operating state to the holding state. Thus, the frequency-divided output that has changed from the “L” level to the “H” level at the point P4 maintains the “H” level state.

  As can be seen from the above description, in the frequency dividing device 2, the synchronization compensation circuit 2-2 is configured to have a time period TM corresponding to four periods of the master clock centered on the point where the level of the divided signal B is expected to be displaced. Since it is in an operating state only and is in a holding state during other time periods, power consumption is negligible. As a result, it is possible to suppress jitter generated inside without increasing the power consumption.

  In the first embodiment (2) described above, a master clock is supplied to the synchronization compensation circuit 1-2 (2-2), and the synchronization compensation master clock is supplied to the synchronization compensation circuit 1-2 (2-2). Although generated, a delay circuit may be provided outside, and the master clock delayed by this delay circuit may be given to the synchronization compensation circuit 1-2 (2-2) as a synchronization compensation master clock.

  Further, in the first embodiment (2) described above, the master is centered on the point where the synchronization compensation master clock is continuously generated and the level of the divided signal (post-divided signal B) is expected to be displaced. The level of the post-division signal (post-division signal B) is captured in synchronization with the master clock for synchronization compensation only in the time period of one cycle (four cycles) of the clock. The synchronization compensation master clock is generated only in the time period of one period (four periods) of the master clock centering on the point where the level of the rear signal B) is expected to be displaced, and the synchronization compensation is generated only in this time period. The level of the post-division signal (post-division signal B) may be captured in synchronization with the master clock.

  In the first embodiment (2) described above, a time corresponding to one cycle (four cycles) of the master clock centered on a point at which the level of the divided signal (post-divided signal B) is expected to be displaced. The frequency of the divided signal (divided signal B) is captured in synchronization with the master clock for synchronization compensation only in the band, but this time period is not limited to one period or four periods of the master clock. Absent. In addition, the time zone TM to be in the operating state may be determined only in the delay direction starting from a point where the level of the divided signal (post-divided signal B) is expected to be displaced.

  In the first embodiment (2) described above, the frequency-divided signal from the frequency divider 1-1 (2-1) is synchronized with the master clock for synchronization compensation whose phase is shifted from the master clock by a predetermined amount. However, the synchronous compensation frequency-divided signal whose phase is shifted by a predetermined amount with respect to the frequency-divided signal from the frequency divider 1-1 (2-1) is captured in synchronization with the master clock. Also good. In this case, the synchronization compensation circuit is set in an operating state only in a predetermined time zone starting from a point at which the level of the signal after frequency division for synchronization compensation is expected to be displaced, and in other time zones, the synchronization compensation circuit 1-2 (2 -2) is set to the holding state. Further, the frequency-divided signal for synchronization compensation is generated in the synchronization compensation circuit 1-2 (2-2).

[Variable frequency divider described in Japanese Patent Application No. 2003-174543]
FIG. 5 shows a variable frequency divider described in Japanese Patent Application No. 2003-174543 previously proposed by the present applicant. In this variable frequency divider 300, an exclusive OR circuit (EX-OR) is used as the inverting / non-inverting circuit 304, the TFF (two frequency divider) is used as the fixed frequency divider 305, and the feedback frequency divider 308. ), And a speed reduction frequency divider (TFF: 2 frequency divider) 309 is provided at the preceding stage of the inverting / non-inverting circuit 304 (between the clock input terminal 301 and the input terminal 304a of the inverting / non-inverting circuit 304). Provided.

  In the inverting / non-inverting circuit 304, a terminal 304a connected to one input of EX-OR is an input terminal, and a terminal 304b connected to the other input is a control terminal. The input terminal 304 a is connected to the clock input terminal 301 via the speed reduction frequency divider 309, and a feedback path 307 is formed between the control terminal 304 b and the output of the fixed frequency divider 305. The feedback path 307 is provided with a connector 306 and a feedback frequency divider 308. FIG. 6 shows a truth table of the inverting / non-inverting device (exclusive OR circuit) 304.

[When the feedback path is blocked]
When the control signal M is “0” level, the connector 306 turns off the feedback path 307 and disconnects the connection between the output of the fixed divider 305 and the control terminal 304 b of the inverting / non-inverting device 304. In this case, the level of the control terminal 304b of the inverting / non-inverting circuit 304 is set to “0” level, and the inverting / non-inverting circuit 304 performs the exclusive clock operation according to the truth table shown in FIG. Is passed through without being inverted, and is supplied to the fixed frequency divider 305 as a clock signal before frequency division.

  FIG. 7 shows a time chart when the feedback path 307 is blocked. 7A shows a clock signal (master clock) supplied to the clock input terminal 301, FIG. 7B shows an input clock signal supplied to the input terminal 304a of the inverting / non-inverting circuit 304, and FIG. FIG. 7D shows an output clock signal output from the fixed frequency divider 305. FIG. 7D shows an output clock signal output from the fixed frequency divider 305. FIG. 7 (e) is a signal level of the control terminal 304 b of the inverting / non-inverting device 304.

  In this example, the clock signal from the clock input terminal 301 is divided by two by the speed reduction frequency divider 309, and the clock signal thus reduced in speed is input to the input terminal 304 a of the inverting / non-inverting circuit 304 as an input clock signal. Given to. As can be seen from this time chart, when the control signal M is “0” level, the variable frequency divider 300 outputs one pulse of the output clock signal every four clock pulses of the clock signal from the clock input terminal 301. And operates as a frequency divider.

[When feedback path is connected]
When the control signal M is “1” level, the connector 306 turns on the feedback path 307 to connect between the output of the fixed frequency divider 305 and the control terminal 304 b of the inverting / non-inverting device 304.

  FIG. 8 shows a time chart when the feedback path 307 is connected. 8A is a clock signal (master clock) supplied to the clock input terminal 301, FIG. 8B is an input clock signal supplied to the input terminal 304a of the inverting / non-inverting circuit 304, and FIG. 8C is inverted. / A pre-division clock signal output from the non-inverter 304 (pre-division clock signal supplied to the fixed frequency divider 305), FIG. 8 (e) is a feedback signal supplied to the control terminal 304 b of the inverting / non-inverting device 304 via the feedback path 307.

  In this time chart, the signal applied to the input terminal 304 a of the inverting / non-inverting circuit 304 passes through the inverting / non-inverting circuit 304, the fixed frequency divider 305, and the feedback path 307, so that the inverting / non-inverting circuit 304 The delay time Td until returning to the control terminal 304b is set to be slightly larger than the pulse width Tck of the input clock signal.

  As can be seen from this time chart, when the control signal M is “1” level, the variable frequency divider 300 outputs two pulses of the output clock signal every time six clock pulses of the clock signal from the clock input terminal 301 are given. And operates as a three-frequency divider.

  In this variable frequency divider 300, an inverting / non-inverting circuit 304 is provided in order to switch between the required odd frequency division and even frequency division, and as a result, the rise and fall of the speed reduction frequency divider 309 are provided. Frequency division is performed using both falling edges. Therefore, when the duty ratio of the output of the speed reduction frequency divider 309 is not 1: 1, jitter Tj is generated in the output clock signal (see FIG. 9).

  On the other hand, as shown in FIG. 10, a synchronous compensation circuit 310 is provided after the fixed frequency divider 305, and a clock signal (master clock) to the speed reduction frequency divider 309 is branched and input to the synchronous compensation circuit 310. By doing so, it is possible to obtain a frequency-divided output that does not include the jitter Tj synchronized with the synchronization compensation master clock (see FIG. 11).

  As an example of the synchronization compensation circuit, a DFF type latch circuit as shown in FIG. 12 can be considered. Since the synchronous compensation circuit 400 is required to operate at a master clock, it is a current mode circuit from the viewpoint that a circuit as fast as possible is desirable. Of course, a CMOS logic latch circuit or the like may be used. Needless to say, it is good. The bias potential VB is applied only during the time period before and after the input (DN, DP: signal after frequency division) to the synchronization compensation circuit 400 shown in FIG. FIG. 13 is a time chart showing the operation of the synchronization compensation circuit 400.

  When the bias potential VB is zero or a very small value, the power consumption of the entire circuit is very small, but high-speed operation is impossible. Therefore, even if the synchronization compensation master clocks CN and CP are input, the output is possible. Will not change. On the other hand, if a voltage is applied to VB to put the circuit in an operating state, the power consumption increases, but the input signals DP and DN can be output in synchronization with the timings of the synchronization compensation master clocks CP and CN. Thus, jitter is suppressed.

  In the power consumption of the entire frequency divider, the increase in power when the synchronization compensation circuit 400 is added can be almost negligible when the activation rate of the synchronization compensation circuit 400 is low. For example, when a synthesizer as described in the description of the prior art is configured by a pulse swallow type frequency divider, the frequency division number of the pulse swallow type frequency divider is from several thousand to several hundred thousand, The interval at which the output value is displaced is sufficiently longer than the master clock cycle Tck. Therefore, if the synchronous compensation circuit 400 is activated only at the time of displacement, the power consumption can be negligible.

  In the time chart shown in FIG. 13, the function (operating state / holding state) of the synchronous compensation circuit 400 is realized by controlling the bias potential VB, but as shown in the time chart shown in FIG. Alternatively, it may be realized by controlling whether or not the synchronization compensation master clocks CN and CP are input. In the example of FIG. 14, the presence / absence of input of the synchronization compensation master clock to the synchronization compensation circuit 400 and VB are controlled simultaneously. However, VB is always supplied with the potential of the operation state and the synchronization compensation master clock is input. It goes without saying that only the presence or absence may be controlled.

It is a schematic block diagram which shows the principal part of one Embodiment (Embodiment 1) of the frequency divider which concerns on this invention. It is a schematic block diagram which shows the principal part of other embodiment (Embodiment 2) of the frequency divider which concerns on this invention. 2 is a time chart showing the operation of the frequency dividing device shown in FIG. 1. FIG. 3 is a time chart showing the operation of the frequency dividing device shown in FIG. 2. FIG. It is a figure which shows the variable frequency divider described in Japanese Patent Application No. 2003-174543 previously proposed by the present applicant. It is a figure which shows the truth table of the inversion / non-inversion device (exclusive OR circuit) used with this variable frequency divider. It is a time chart when the feedback path is interrupted in this variable frequency divider. 6 is a time chart when a feedback path is connected in the variable frequency divider. In this variable frequency divider, when the duty ratio of the output of the speed reducing frequency divider is not 1: 1, it is a diagram showing a situation where jitter occurs in the output clock signal. It is a figure which shows the variable frequency divider which provided the synchronous compensation circuit. 3 is a time chart showing the operation of a variable frequency divider provided with this synchronization compensation circuit. It is a circuit diagram showing a DFF type latch circuit as an example of a synchronous compensation circuit. 3 is a time chart showing the operation of this synchronization compensation circuit. 6 is a time chart when the function (operation state / holding state) of the synchronization compensation circuit is realized by controlling whether or not a master clock is input. It is a circuit diagram of a synthesizer circuit using a conventional frequency divider.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Frequency divider, 1-1 ... Frequency divider, 1-2 ... Synchronization compensation circuit, 2 ... Frequency divider, 2-1 ... Frequency divider, 2-11 ... 1st frequency divider, 2-12 2nd frequency divider (counter) 2-2 Synchronous compensation circuit 300 Variable variable frequency divider 301 Clock input terminal 302 Clock output terminal 303 Control signal input terminal 304 Inverted / non-inverted Inverter (exclusive OR circuit), 304a ... input terminal, 304b ... control terminal, 305 ... fixed frequency divider, 306 ... connector, 307 ... feedback path, 308 ... frequency divider for feedback, 309 ... for speed reduction Frequency divider, 310... Synchronization compensation circuit, 400... Synchronization compensation circuit.

Claims (4)

A frequency divider that divides the master clock and outputs the divided signal as a signal,
A synchronization compensation circuit that captures the frequency-divided signal from the frequency divider in synchronization with the master clock for synchronization compensation whose phase is shifted by a predetermined amount with respect to the master clock, and outputs the signal as a frequency-divided output;
The synchronization compensation circuit is an operation state in which the level of the frequency-divided signal is captured in synchronization with the synchronization compensation master clock only in a predetermined time period starting from a point where the level of the frequency-divided signal is expected to be displaced. The frequency divider is characterized in that it is in a holding state that holds the captured level during other time periods. The frequency divider according to claim 1,
The frequency-dividing device, wherein the synchronization compensation master clock is generated only in a predetermined time period starting from a point where the level of the frequency-divided signal is expected to shift. In the frequency dividing device according to claim 1 or 2,
A frequency divider comprising: means for notifying the synchronization compensation circuit of a predetermined time period starting from a point at which the level of the frequency-divided signal is expected to be displaced. A frequency divider that divides the master clock and outputs the divided signal as a signal,
A synchronous compensation circuit that takes in a synchronous compensation frequency-divided signal whose phase is shifted from the frequency-divided signal from the frequency divider in synchronization with the master clock, and outputs it as a frequency-divided output;
The synchronization compensation circuit synchronizes the level of the post-synchronization signal for synchronization compensation with the master clock only during a predetermined time period starting from a point at which the level of the post-synchronization signal for synchronization compensation is expected to shift. A frequency dividing device characterized in that it is in an operating state for capturing, and is in a holding state for retaining the level that has been captured during other time periods.

Images