JP2011040934A - Frequency divider circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency divider circuit capable of correctly generating a frequency division signal of high frequency-division accuracy even for a high-speed clock signal. <P>SOLUTION: Variable integer frequency dividers (1A, 1B) capable of performing frequency dividing operations by two continuous integers P and P+1 are arranged in parallel with each other, and the frequency dividers are made to perform frequency dividing operations at a half-clock phase difference. Either of output signals (DO1, DO2) of the variable integer frequency dividers is selected according to a route selection signal (MXCNT) to generate a final frequency division signal (DO). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a frequency dividing circuit, and more particularly to a configuration of a variable fractional frequency dividing circuit capable of switching between integer frequency division and fractional frequency division used in a PLL frequency synthesizer.

  In wireless communication such as mobile communication, communication is performed by generating radio waves by placing data on a carrier wave and transmitting and receiving the radio waves. In order to generate this carrier wave, a PLL (phase locked loop) frequency synthesizer is generally used. In general, in a PLL of a PLL frequency synthesizer, a frequency divider having a frequency division number N is disposed between a voltage controlled oscillator and a phase comparator. An output signal of the PLL is generated by the voltage controlled oscillator. The phase comparator detects a phase difference between the PLL input reference signal and the output signal. In the case of this configuration, the frequency of the output signal is N times the frequency of the input reference signal.

  The configuration of the frequency divider of such a PLL frequency synthesizer is shown as an example in Non-Patent Document 1 (written by Toshiyuki Ozawa, “PLL Frequency Synthesizer / Circuit Design Method”, pp111-119, Sogo Electronics Publishing Co., Ltd., 1994). ing. In this non-patent document 1, a configuration of a pulse swallow system is shown as a configuration of a frequency divider. In such a frequency divider, an integer frequency dividing number is used.

  On the other hand, the configuration of a fractional frequency divider (fractional-N frequency divider) that uses a fractional frequency division to reduce the channel spacing is described in Non-Patent Document 2 (Yu-Che Yang et. Al., “A Quantization Noise”). Suppression Technique for ΔΣ Fractional-N Frequency Synthesizers ”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.41, No.11, Nov. 2006). In the configuration shown in Non-Patent Document 2, a prescaler logic that can be switched between a frequency division number of 1 and 1.5 and an end-of-cycle logic that adjusts the frequency division number of the prescaler logic according to a control signal are provided. Each of the prescaler logic and the end-of-cycle logic includes two complementary D-latches (flip-flops) and a multiplexer that selects output signals of the two flip-flops. The output signal of the prescaler logic is fed back to the end-of-cycle logic. In the end-of-cycle logic, the frequency division number of the prescaler logic is set to 1 or 1.5 according to the frequency division number control signal (MOD, FB_CTRL).

Ozawa Toshiyuki, “PLL Frequency Synthesizer / Circuit Design Method”, pp111-119, Sogo Electronics Publishing, 1994 Yu-Che Yang et. Al., “A Quantization Noise Suppression Technique for ΔΣ Fractional-N Frequency Synthesizers”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.41, No.11, Nov. 2006

  In the above-mentioned Non-Patent Document 1, a two-coefficient prescaler type PLL is disclosed as a frequency divider having a fractional number. This two-coefficient prescaler can perform frequency division operation with two consecutive integer frequency division numbers P and P + 1. The 2-coefficient prescaler performs a frequency dividing operation for each predetermined cycle with frequency dividing numbers P and (P + 1) in accordance with the output signal of the swallow counter. The frequency division ratio can be set to a fraction by the average signal of the output signals.

  However, in the case of the two-coefficient prescaler, a frequency division signal having an integer frequency division number is generated, and a signal having a fractional frequency division number is generated as an average. The output signal of the fractional frequency division is not directly generated, and no consideration is given to the configuration of the fractional frequency divider that directly generates the frequency-divided signal of fractional accuracy.

  In the configuration shown in Non-Patent Document 2 described above, the frequency division number is switched between 1 and 1.5 according to the control signal. In order to configure the frequency division number with step (channel interval) 0.5, it is necessary to execute the frequency division operation with frequency division number 1 and frequency division number 1.5 according to the frequency division number. However, when the frequency division number is switched between 1.5 and 1, the frequency division number control signal is divided into a state in which the frequency division number 1 is designated and divided in 1.5 cycles of the input signal (input clock signal). It is necessary to switch between states that specify a lap number of 1.5.

  Specifically, in the configuration of Non-Patent Document 2, a latch circuit that complementarily latches / holds in accordance with an input signal is used to latch the output signal in accordance with the input signal, and the output signal is switched by a multiplexer to divide the frequency. The number is switched between 1.0 and 1.5. The output signal to be latched is set to a fixed value or an output signal according to the frequency division number control signal.

  When the frequency division control signal is set to a state in which the frequency division number 1.5 is designated between 1.5 clock cycles and 2 clock cycles of the input clock signal, only 1.5 clocks are output. Yes, the frequency division number can be switched from 1 to 1.5. However, if the frequency division control signal is set to be longer than 2 clock cycles in a state designating 1.5 clocks and then set to a state designating 1.0 frequency divisions, 1.5 clock pulses Are output twice, and a pulse signal having a cycle longer by one clock cycle (= 0.5 × 2) is generated. Therefore, in this case, the frequency division number is switched between 1 and 2, and the frequency division cannot be performed with step 0.5 clock. Here, “clock” indicates one pulse of the clock signal.

  Therefore, when the frequency division number is switched to 1.0, 1.5, and 1.0, it is necessary to switch the logical value of the frequency division number control signal twice during 1.5 clocks. When the input clock signal is a high-speed signal, the timing margin for switching the frequency division number control signal becomes small, and it becomes difficult to generate a frequency division signal with a fractional accuracy for the high-speed input signal. The largest timing margin can be obtained when the frequency division number control signal is switched in synchronization with the input clock signal. Even in this case, the state of the frequency division number control signal needs to be switched twice within three clock cycles of the input clock signal, and the same problem occurs.

  The frequency division number control signal is output from a control signal generation circuit that is usually composed of a logic circuit. Therefore, the operating frequency is limited, and when the input clock signal is a high-speed clock signal, it becomes difficult to generate a frequency division control signal with high time accuracy, and a high-speed variable fractional frequency division operation can be realized. Disappear.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a frequency dividing circuit that can accurately perform a fractional frequency dividing operation even for a high-speed input clock signal.

  The frequency dividing circuit according to the present invention is provided in parallel with each other, and each divides the clock signal applied according to the frequency dividing number setting signal by at least one of the continuous integers P and P + 1. And N + 1 frequency dividers to be output, and a path switching circuit that selects and outputs any one of the output signals of these N + 1 frequency dividers according to the path selection signal.

  The N + 1 frequency dividers are sequentially numbered from 0 to N, and the Jth frequency divider in the N + 1 frequency dividers corresponds to the clock signal supplied to the 0th frequency divider. A clock signal having a delay of J / (N + 1) cycles is provided.

  Preferably, the frequency division setting signal is MOD () when the final frequency division signal is changed from P frequency division to P + (A / N + 1) frequency while the output signal of the Kth frequency divider is selected. The output signal of the (A + K, N + 1) th frequency divider is selected. Here, MOD (A + K, N + 1) is a remainder when (A + K) is divided by (N + 1), and indicates a modulo-M operation. The frequency division number setting signal sets the frequency division ratio of the MOD (A + K, N + 1) th frequency divider to P, and performs frequency division operation at a timing earlier than that of the MOD (A + J, N + 1) th frequency divider. For the frequency divider to be executed, the frequency division number is set to P + 1, and for the remaining frequency dividers, the frequency division number is set to P. Here, A is an integer of 0 or more and less than N.

  When changing to P + 1 frequency division with the output signal of the Jth frequency divider selected, the frequency division number setting signal is set so that the frequency division numbers of the N + 1 frequency dividers are all set to P + 1. The path selection signal continuously selects the output signal of the Jth frequency divider.

  The state of the frequency division number control signal is changed once in one frequency division cycle. Therefore, it is only required to change the state during the cycle period of the input clock signal that is about 1/2 times the frequency division number of the final frequency division signal, and the frequency division number should be set with a sufficient margin. The frequency division number change interval can be increased, and the frequency division number can be accurately changed even for a high-speed input clock signal.

It is a figure which shows roughly the structure of the variable fractional frequency dividing circuit according to Embodiment 1 of this invention. FIG. 2 is a timing diagram showing an operation of the variable fractional frequency dividing circuit shown in FIG. 1. FIG. 6 is a timing chart showing a specific operation of the variable fractional frequency divider circuit according to the first embodiment of the present invention. FIG. 3 is a timing chart showing a specific frequency dividing operation of the variable fractional frequency dividing circuit shown in FIG. 1. It is a figure which shows the timing margin of the setting of the frequency division number control signal of the variable fractional frequency dividing circuit shown in FIG. It is a figure which shows the timing margin of the setting of the frequency division number control signal of the variable fractional frequency dividing circuit shown in FIG. It is a figure which shows schematically the structure of the conventional fractional frequency dividing circuit. FIG. 8 is a timing chart showing a specific operation of the conventional fractional frequency dividing circuit shown in FIG. 7. FIG. 8 is a timing chart showing a specific operation of the conventional fractional frequency dividing circuit shown in FIG. 7. It is a figure which shows the setting timing margin of the frequency dividing number control signal of the fraction dividing circuit shown in FIG. 1 and FIG. It is a figure which shows roughly an example of a structure of the frequency division number control signal generation part with respect to the frequency divider circuit according to Embodiment 1 of this invention. It is a figure which shows the concrete operation | movement sequence and variable frequency control signal setting timing margin of the variable fractional frequency dividing circuit according to Embodiment 2 of this invention. It is a figure which shows the concrete operation | movement sequence of the fractional frequency divider circuit according to Embodiment 3 of this invention, and the timing margin of a frequency division number control signal. It is a figure which shows the other frequency division operation | movement sequence of the fractional frequency divider circuit according to Embodiment 3 of this invention. It is a timing diagram which shows the further another frequency division operation sequence according to Embodiment 3 of this invention. It is a figure which shows roughly the structure of the fractional frequency dividing circuit according to Embodiment 4 of this invention. It is a figure which shows roughly the structure of the fractional frequency dividing circuit according to Embodiment 5 of this invention. It is a figure which shows roughly the structure of the fractional frequency dividing circuit according to Embodiment 6 of this invention. It is a figure which shows roughly the structure of the fractional frequency dividing circuit according to Embodiment 7 of this invention. FIG. 20 schematically shows a configuration of a variable integer frequency divider shown in FIG. 19. It is a figure which shows roughly an example of a structure of the fraction control signal generation part of the variable fractional frequency dividing circuit according to Embodiment 7 of this invention. It is a figure which shows roughly the structure of the variable fractional frequency dividing circuit according to Embodiment 8 of this invention. FIG. 23 is a diagram schematically showing a configuration of a variable integer frequency divider shown in FIG. 22. FIG. 23 is a diagram schematically showing a configuration of a path selection signal generation circuit shown in FIG. 22. FIG. 23 is a diagram schematically showing an example of a configuration of a part that generates a frequency division number selection signal shown in FIG. 22; It is a figure which shows roughly the structure of the variable fractional frequency dividing circuit according to Embodiment 9 of this invention. FIG. 27 is a diagram schematically showing an example of a configuration of a frequency division number control signal generation unit for the fractional frequency dividing circuit shown in FIG. 26. It is a figure which shows roughly the structure of the variable fractional frequency dividing circuit according to Embodiment 10 of this invention. It is a figure which shows the timing relationship of the clock signal given to FIG. It is a figure which shows the phase relationship of the frequency-divided signal which the master and slave output at the time of operation | movement of the fractional frequency dividing circuit shown in FIG. FIG. 29 is a timing chart showing an operation sequence of the fractional frequency dividing circuit shown in FIG. 28. It is a figure which shows the operation | movement switching aspect of the fractional frequency dividing circuit shown in FIG. FIG. 29 is a diagram schematically showing an example of a configuration of a fractional control signal generation unit for the fractional frequency dividing circuit shown in FIG. 28. FIG. 34 is a flowchart showing an operation of a frequency division number control signal generation unit shown in FIG. 33. It is a figure which shows roughly the structure of the fractional frequency dividing circuit of the example of a change of Embodiment 10 of this invention.

[Embodiment 1]
FIG. 1 schematically shows a configuration of a frequency dividing circuit (variable fractional frequency dividing circuit) according to the first embodiment of the present invention. In FIG. 1, the frequency dividing circuit includes variable integer frequency dividers (DIV) 1A and 1B provided in parallel, and output signals (sub frequency dividing signals) DO1 of variable integer frequency dividers 1A and 1B according to path selection signal MXCNT. A path switching circuit (MUX) 2 that selectively passes DO2 and generates an output signal (final frequency-divided signal) DO.

  A variable integer frequency divider (DIV1) 1A receives differential clock signals CLK1 and CLK1B having a duty of 50% at a positive phase input (+) and a negative phase input (−), respectively, and a frequency division number according to a frequency division number setting signal DVCNT1. Is set to one of the consecutive integer frequency division numbers P and P + 1 to generate the sub-frequency division signal DO1. Here, P is a positive integer of 1 or more.

  Variable integer frequency divider (DIV2) 1B receives differential clock signals CLK1B and CLK1 at the positive phase input and the negative phase input, respectively, and in accordance with frequency division number setting signal DVCNT2, the frequency division number is integer frequency division numbers P and P + 1. The sub-frequency-divided signal DO2 is generated by performing a frequency-dividing operation. Therefore, variable integer frequency dividers 1A and 1B are provided in such a manner that differential clock signals CLK1 and CLK1B are complementary to each other, and sub-frequency-divided signals DO1 and DO2 are half cycles (0. 5 clocks).

  The path switching circuit (MUX) 2 receives the path selection signal MXCNT at the selection input S, and when the path selection signal MXCNT is at the H level (“1”), selects the output signal DO1 of the variable integer frequency divider 1A, When the selection signal MXCNT is at L level (“0”), the output signal DO2 of the variable integer frequency divider 1B is selected.

  The variable integer frequency dividers 1A and 1B have the same internal configuration, and are different only in the polarities (phases) of input differential clock signals CLK1 and CLK1B. Variable integer frequency dividers 1A and 1B whose frequency division number can be switched between integer frequency division numbers P and P + 1 are not particularly limited, but are configured using, for example, a two-coefficient prescaler. As an example of the configuration of such a two-coefficient prescaler, the following configuration can be used. That is, a plurality of divide-by-2 circuits are connected in cascade, and a variable frequency divider (2/3 frequency divider) that can be set so that the frequency division number can be switched between 2 and 3 is provided in the first stage. The gate circuit (NAND gate) alternately receives the positive output Q and the complementary output / Q of the two frequency dividers connected in cascade, and receives the frequency division number setting signal. The output signal of this gate circuit sets the frequency division number of the 2/3 frequency divider. The configurations of the divide-by-2 circuit and the divide-by-2 / 3 circuit are well known. The internal configuration of the variable integer frequency dividers 1A and 1B is not limited to the above-described configuration, and can be divided by a specified frequency division number among consecutive integers P and P + 1 according to the frequency division number setting signal. Any configuration may be used.

  FIG. 2 is a timing chart showing the operation of the variable fractional frequency dividing circuit shown in FIG. In FIG. 2, the variable integer frequency divider 1A counts the rising edge of the input clock signal CLK1, and when the frequency division number is set to P, the output sub frequency division signal DO1 is output while the count value is P / 2. Is set to H level, and during the next P / 2 clock cycle, output sub-divided signal DO1 is set to L level to generate a signal with a duty of 50%. On the other hand, when the frequency division number is set to P + 1, the variable integer frequency divider 1A sets the output sub frequency division signal DO1 to the H level while the number of rising edges of the input clock signal CLK1 is P / 2. During the next P / 2 + 1 cycle, the output frequency division signal DO1 is set to L level.

  The variable integer frequency divider 1B is provided with differential clock signals CLK1 and CLK1B in a manner complementary to the variable integer frequency divider 1A, and outputs its output signal DO2 in synchronization with the falling edge of the input clock signal CLK1. Start-up, the sub-divided signal DO2 is set to the H level while the count value is P / 2, and the output divided signal DO2 is set to the L level during the next P / 2 cycle (P-dividing operation). in the case of). On the other hand, in the case of the P + 1 frequency division operation, the variable integer frequency divider 1B sets the output sub-frequency-divided signal to the H level while counting the fall for P / 2 in synchronization with the fall of the input clock signal CLK1. Then, during the period when the next count value is (P / 2) +1, the output sub-divided signal DO2 is set to L level.

  A frequency dividing circuit according to the present invention (hereinafter referred to as a variable fractional frequency dividing circuit) performs P frequency division, P + 1 frequency division, or P + 0.5 frequency division operations. In the following description, the variable integer frequency divider selected by the path switching circuit 2 at the start of the frequency division operation is defined as “master”, and the non-selected variable integer frequency divider is defined as “slave”. In the initial state of the variable fractional frequency dividing circuit, the variable integer frequency divider that starts the frequency dividing operation by first catching the rising edge with respect to the input differential clock signals CLK1 and CLK1B is set as a master. Therefore, the master outputs a sub-frequency-divided signal that is 0.5 clock cycles faster (phase advanced) of the input clock signal CLK1 to the slave.

  The frequency division number setting signals DVCNT1 and DVCNT2 are changed to a period in which the output sub frequency division signals DO1 and DO2 of the variable integer frequency dividers 1A and 1B are both at the H level. Therefore, a period of (P / 2) −0.5 clock cycles can be used as the frequency division number changing period. Next, a specific operation of the variable fractional frequency dividing circuit shown in FIG. 1 will be described.

  FIG. 3 is a timing chart showing the frequency dividing operation of the variable fractional frequency dividing circuit shown in FIG. In FIG. 3, the frequency dividing number P in the variable fractional frequency dividing circuit is set to 8 as an example, and is switched between the frequency dividing numbers 8 and 9, and as a whole, continuously divided by 8 and 8.5 minutes. An example of the operation when performing the divide and divide-by-8 operations will be described.

  The variable integer frequency divider 1A is set to 9 when the frequency division number setting signal DVCNT1 is at the H level, and is set to the frequency division operation when the frequency division number setting signal DVCNT1 is at the L level. Similarly, the variable integer frequency divider 1B is set to divide-by-9 operation when the division number setting signal DVCNT2 is at H level, and is set to divide-by-8 operation when the division number setting signal DVCNT2 is at L level. Is done. The same applies to the following description.

  Further, in FIG. 3 and the timing charts below, a waveform indicated by a thick line indicates a signal waveform selected and output by the path switching circuit 2.

  In FIG. 3, the variable integer frequency divider 1A is selected as a master, and in synchronization with the rising edge of the input clock signal CLK1 from time T0, the output sub-frequency-divided signal DO1 becomes H level, delayed by half a clock cycle. The output frequency division signal DO2 of the variable integer frequency divider 1B rises to the H level. In the divide-by-8 operation, sub-frequency-divided signals DO1 and DO2 are at H level during 4 clock cycles of clock signal CLK1, and sub-frequency-divided signals DO1 and DO2 are at L-level during 4 clock cycles.

  Here, in the following description, for convenience, the frequency division number setting signals DVCNT1 and DVCNT2 and the path selection signal MXCNT are collectively referred to as a frequency division number control signal. In the present embodiment, these frequency division number control signals MXCNT, DVCNT1 and DVCNT2 are controlled in their states (logical values) in parallel at the same timing.

  At time T0, the path selection signal MXCNT is at the H level, and the path switching circuit 2 selects the sub frequency division signal DO1 output from the variable integer frequency divider 1A. The frequency division number setting signal DVCNT1 is set to the L level, and the variable integer frequency divider executes the frequency division operation. On the other hand, the frequency division number setting signal DVCNT2 is at the H level, and the variable fractional frequency divider executes a frequency division operation of 9.

  At time T1a, the frequency division number setting signal DVCNT2 is set to the L level, and the variable integer frequency divider 1B executes the frequency division operation. From time T0 to time T1, the path selection signal MXCNT is at L level, the variable integer frequency divider 1A is the master, and the final frequency division signal DO from the path selection circuit 2 is at H level for 4 clock cycles. During 4 clock cycles, it becomes an L level duty 50% divide-by-8 signal.

  After time T1, the route selection signal MXCNT is set to L level and the frequency division number setting signal DVCNT1 is set to H level at time T2a. In this state, the output signal DO2 of the variable integer frequency divider 1B is selected by the path selection circuit 2. The output signal DO2 of the variable integer frequency divider 1B is delayed in half clock cycle phase with respect to the output signal DO1 of the variable integer frequency divider 1A. Therefore, the frequency-divided signal DO from the path switching circuit 2 is at the H level for 4.5 clock cycle periods, and during the next 4 clock cycle periods, the variable integer frequency divider 1B performs the frequency dividing operation of 8 clocks. The cycle period is at L level. Therefore, in the period between time T1 and time T2, a signal divided by 8.5 is generated.

  At time T2a, in parallel with switching of the route selection signal MXCNT, the frequency division number setting signal DVCNT1 is set to the H level, and the variable integer frequency divider 1A executes the frequency division operation by 9. In this divide-by-9 operation, the L level period is extended by one clock compared to the divide-by-8 operation. Therefore, at time T2, the output signal DO2 of the master variable integer frequency divider 1B rises to the H level, and the output signal DO1 of the slave variable integer frequency divider 1A becomes the H level after a delay of 0.5 clock cycle. stand up. That is, the phase of the output signal DO1 of the slave variable integer frequency divider 1A is delayed by 0.5 clock with respect to the master output signal DO2. As a result, the sub-frequency-divided signal output from the master maintains the time relationship that the phase is delayed by 0.5 clock from the sub-frequency-divided signal output from the slave.

  At time T3a, the frequency division number setting signal DVCNT1 is set to L level again, and the frequency division number of the variable integer frequency divider 1A is set to 8. The states of the fraction setting signal DVCNT2 and the route selection signal MXCNT are not changed. Thus, from time T2 to T3, the output signal of the frequency divider selected by the path selection circuit 2, that is, the output signal DO2 of the master variable integer frequency divider 1B is the output signal of the slave variable fractional frequency divider 1A. The relationship that the half clock cycle phase is ahead of DO1 is maintained.

  Accordingly, when the frequency division is performed by 8 and the sub frequency division signals DO1 and DO2 are both at the H level, the frequency division number setting signal of the master at that time is set from 8 to 9, and the path selection circuit 2 By changing the selection path, the 8.5 divided signal can be continuously generated after the divided by 8 signal. Naturally, when the frequency division number setting signal and the selection path are maintained, the frequency divided signal can be continuously generated.

  FIG. 4 is a timing chart showing an operation when the 8.5 frequency dividing operation is continuously executed. In FIG. 4, the operation from time T0 to time T2 is the same as the timing chart shown in FIG. That is, during the period from time T0 to time T2a, the variable integer frequency divider 1A operates as the master and the variable integer frequency divider 1B operates as the slave, and the final frequency division signal DO is the output frequency division signal of the variable integer frequency divider 1A. It changes according to DO1.

  At time T2a, the path selection signal MXCNT is set to L level, and in parallel, the frequency division number setting signal DVCNT1 is set to H level, and a frequency division operation of 9 is designated for the variable integer frequency divider 1A. . At this time, the final frequency-divided signal DO changes according to the sub-frequency-divided signal DO2 output from the variable integer frequency divider 1B.

  At time T2, even if the output frequency division signal DO2 of the variable integer frequency divider 1B rises to the H level, the variable integer frequency divider 1A is still executing the frequency division operation of 9 and is output. Sub-frequency-divided signal DO1 is at L level, and sub-frequency-divided signal DO1 rises to H-level with a delay of a half clock cycle from time T2. Thus, similar to the operation shown in FIG. 3, in the phase relationship between the sub-divided signals output from the master variable integer frequency divider and the slave integer frequency divider, there is a relationship in which the master always performs the frequency dividing operation faster by half a clock cycle. Maintained.

  At time T3d, the path selection signal MXCNT is set to H level, the frequency division number selection signal DVCNT1 is set to L level, and the frequency division number setting signal DVCNT2 is set to H level. As a result, the variable integer frequency divider 1A performs the frequency division operation by 8, and the variable integer frequency divider 1B performs the frequency division operation by 9. Since the sub-frequency-divided signal DO1 is delayed by half a clock cycle from the sub-frequency-divided signal DO2 selected until time T3d, the final frequency-divided signal DO is at the H level for 4.5 clock cycle periods. Thereafter, during the 4-clock cycle period, the final frequency-divided signal DO becomes L level in accordance with the sub-frequency-divided signal DO1, and a signal having a period of 8.5 clock cycles is output.

  That is, when the 8.5 frequency division operation is repeatedly executed, the master and slave are alternately switched and the frequency division number is changed during the period in which each of the sub frequency division signals DO1 and DO2 is at the H level in each frequency division clock cycle. Switch.

  As shown in FIG. 3 and FIG. 4, it is only necessary to change the state of the frequency division control signals MXCNT, DVCNT1 and DVCNT2 once in the frequency division clock cycle, and the frequency of the frequency division control signal is changed twice in each frequency division clock cycle period. There is no need to change state. That is, the timing margin for the frequency division control signal can be made sufficiently large, and the frequency division number can be accurately changed even for the high-speed clock signal to generate the fractional frequency division signal.

  FIG. 5 is a diagram showing a setting timing margin (temporal margin) of the frequency division control signal under the operating conditions shown in FIG. Setting of the frequency division control signals MXCNT, DVCNT1, and DVCNT2 needs to be executed when both the sub frequency division signals DO1 and DO2 are at the H level. In the case of the divide-by-8 operation, both of the sub-divide signals DO1 and DO2 are at the H level in the period from time T1b to T1c and in the period from time T3b to time T3c. It is a clock cycle. On the other hand, in the case of 8.5 frequency division operation, the period during which both sub frequency division signals DO1 and DO2 are at the H level is a 3.5 clock cycle period from time T2b to time T2c.

  In addition, when the 8.5 frequency dividing operation is executed following the frequency dividing operation, after the frequency dividing number control signal is set once, the time from the time T1c until the next frequency dividing number control signal is set is set. There is a period of at least 4.5 clock cycles until time T2b. Further, when the frequency division operation is executed after the frequency division operation of 8.5, when the frequency division number control signal is once set and then set again, at least 5 clock cycles from time T2c to time T3b are required. There is a period.

  Therefore, when the 8.5 frequency dividing operation is performed after the frequency dividing operation, the frequency division number control signal for executing the frequency dividing operation is within the 3.5 clock cycle period from time T1b to time T1c. Can be set at any time. Regarding the setting of the frequency division number control signal for executing the next 8.5 frequency division operation, 4.5 clock cycles from time T1c to time T2b and 3.5 clock cycles from time T2b to time T2c are added up. There is a time margin of 8 clock cycles.

  Further, in the case where the frequency dividing operation is executed after the frequency dividing operation of 8.5, the frequency division number control signal for executing the frequency dividing operation of 8.5 is set to 3.5 from time T2b to time T2c. It can be executed at any time within the clock cycle period. In addition, by the setting of the frequency division number control signal for executing the next frequency division operation, a total of 8.5 clock cycles of 5 clock cycles from time T2c to time T3b and 4 clock cycles from time T3b to time T3c. There is time for clock cycles.

  Therefore, in any case, the setting interval of the frequency division number control signal is wide, the frequency division number control signal can be controlled at a low speed, and the frequency division number can be accurately set even for the high-speed input clock signal. be able to.

  FIG. 6 is a diagram showing a time margin of the frequency division control signal when the 8.5 frequency division shown in FIG. 4 is continuously performed. In FIG. 6, the sub-frequency-divided signals DO1 and DO2 output from the variable integer frequency dividers 1A and 1B are both at the H level from the time T1 to the time T2 in the first 8.5 frequency division operation. This is a period of 3.5 clock cycles from time T2d to time T2e, and from time T2 to time T4 performed in the second 8.5 frequency dividing operation, from time T3e to time T3f. This is a period of 5 clock cycles. When the frequency division number control signal is once set and then reset, there is a time of at least 5 clock cycles from time T2e to time T3e.

  As described above, when the 8.5 frequency dividing operation is continuously executed, the frequency division number control signal for executing the first 8.5 frequency dividing operation is set to 3 from time T2d to time T2e. It can be executed at any time up to 5 clock cycles. Further, until the setting of the frequency dividing number control signal for executing the next 8.5 frequency dividing operation, five clock cycles from time T2e to time T3e and 3.5 clock cycles from time T3e to time T3f are required. There is a total time of 8.5 clock cycles. Therefore, even when the 8.5 frequency dividing operation is continuously executed, the setting interval of the frequency dividing number control signal is long, and the frequency dividing number control signal can be controlled at a low speed.

  For comparison, consider a frequency dividing circuit using a 1 / 1.5 frequency dividing cell. As shown in FIG. 7, the frequency dividing circuit using the 1 / 1.5 frequency dividing cell is configured to divide the output signal of the 1 / 1.5 frequency divider 11 and the 1 / 1.5 frequency divider 11 by P. An integer divider 12 is included. The 1 / 1.5 frequency divider 11 receives the differential clock signals CLK1 and CLK1B having a duty of 50% at the positive phase input and the negative phase input, respectively, and performs the frequency dividing operation at any one of the frequency division numbers 1 and 1.5. Execute. The frequency division number of the 1 / 1.5 frequency divider 11 is set by a frequency division number setting signal DVCNT.

  The integer frequency divider 12 receives the complementary output signals DOa and DOb of the 1 / 1.5 frequency divider 11 at the normal phase and reverse phase inputs, respectively, performs a frequency division operation with the integer frequency division number P, and performs the final frequency division signal. Generate DO.

  When the 1 / 1.5 frequency divider 11 is set to the frequency division number 1, the input clock signals CLK1 and CLK1B are output as the output signals DOa and DOb. When the frequency division number is set to 1.5, 1 / 1.5 frequency divider 11 generates sub frequency division signals DOa and DOb by extending the L level period by a half clock cycle with respect to input signal CLK1.

  The integer frequency divider 12 counts the rising edge of the output signal DOa of the 1 / 1.5 frequency divider 11, and switches the logic level of the output signal DO every time the count value becomes P / 2.

  FIG. 8 is a timing chart showing the operation of the frequency dividing circuit shown in FIG. In FIG. 8, the operation when the frequency dividing number P of the integer frequency divider 12 is 8 is shown for comparison with the first embodiment of the present invention.

  Frequency division number setting signal DVCNT is set to the L level between 1.5 and 2 cycles of input clock signal CLK1. In FIG. 8, when 1.5 frequency division operation is designated, the frequency division number selection signal DVCNT is set to H level in synchronization with the rising edge of the input clock signal CLK1, and this H level is 1.75 clock cycles. As an example, the case of being maintained during In this case, the 1 / 1.5 frequency divider 11 extends the L level period of the output signal DOa by a half clock cycle (0.5 clock) of the input clock signal CLK1 while the frequency division number setting signal DVCNT is at the H level. To do. Therefore, in the case shown in FIG. 8, only one signal of 1.5 clock cycles is output from the output signal DOa of the 1 / 1.5 frequency divider 11.

  In the integer frequency divider 12, only one 1.5 clock pulse is inserted in the input signal DOa, and the final frequency division signal DO is set to H during the period in which the rising of the input signal DOa to H level is counted four times. Then, the final frequency-divided signal DO is set to L level while counting four rising edges of the input signal DOa to H level. Therefore, as shown in FIG. 8, when the frequency division number selection signal DVCNT is set to H level for 1.75 clock cycles, the output frequency division signal DO becomes H clock period longer by 0.5 clock cycles. A frequency-divided signal having a period of 8.5 clock cycles can be obtained, and 8.5 frequency-dividing can be realized.

  On the other hand, as shown in FIG. 9, when the frequency division number setting signal DVCNT is set to H level asynchronously with the input clock signal CLK1 for two clock cycles or more, the 1 / 1.5 frequency divider 11 is 1. Two pulses of 5 clock cycles are output. In FIG. 9, an operation in which the frequency division number setting signal DVCNT is set to the H level during the 2.25 clock cycle period is shown as an example. In this case, since two 1.5 clock cycle pulses are continuously supplied to the integer divider 12, the H level period of the final divided signal DO output from the integer divider 12 is 5 clock cycles. The L level period is 4 clock cycles, a signal having a period of 9 clock cycles is generated, and a 9-frequency division operation is performed.

  Consider a case where the generation timing of the frequency division number setting signal DVCNT is optimized and the frequency division number setting signal DVCNT is set to the H level in synchronization with the fall of the input clock signal CLK1. Even in this case, if the frequency division number setting signal DVCNT is set to a state of designating the 1.5 frequency division operation at H level for a period exceeding 3 clocks, two pulses of 1.5 clock cycles are generated. A frequency-divided signal having a period of 9 clock cycles is obtained.

  Therefore, in order to generate the 8.5 frequency division signal following the 8 frequency division operation, the frequency division number setting signal DVCNT is switched from the frequency division number 1 to the frequency division number 1.5 and the frequency division number. Switching from 1.5 to 1 is necessary within a very limited maximum of 3 clock cycles. Therefore, when the input clock signal CLK1 is a high-speed clock signal, the timing margin for setting the frequency division number becomes extremely small, and it becomes difficult to accurately generate the fractional frequency division signal.

  The integer frequency dividing number P is not limited to 8, and the fractional frequency dividing operation can be executed as long as it is an integer of 2 or more. Therefore, obviously, the frequency division number switching interval in the first embodiment can secure a minimum P / 2 + 0.5 clock period, and uses a conventional 1 / 1.5 frequency divider. The fractional frequency division number can be set and switched with a sufficient margin.

  FIG. 10 schematically shows a timing margin for setting the frequency dividing number of the frequency dividing circuit according to the first embodiment of the present invention and the conventional frequency dividing circuit shown in FIG.

  In FIG. 10, the horizontal axis represents the frequency division number P, and the vertical axis represents the set time margin from the first frequency division number setting to the second frequency division number setting in terms of the number of clock cycles. In the figure, the black squares indicate the set time margin of the conventional frequency dividing circuit shown in FIG. 7, and the straight line indicated by the triangular marks indicates the timing of the frequency dividing number setting signal of the frequency dividing circuit according to the first embodiment of the present invention. Indicates the margin.

  In the case of the conventional frequency dividing circuit shown in FIG. 7, it is necessary to switch between frequency dividing numbers 1 and 1.5. Therefore, when the frequency dividing number P is 1 and 2, the setting time margin of the frequency dividing number setting signal in the conventional frequency dividing circuit is 2.5 clock cycles between 1.5 clock cycles and 2 clock cycles, respectively. Between one cycle and three clock cycles. When the frequency division number P is 3, the setting time margin is 3 clock cycles (switching of the frequency division number setting signal at the optimization timing). Thereafter, even if the frequency division number P is increased, the time margin is not increased. It does not change and is constant at 3 clock cycles.

  On the other hand, in the frequency dividing circuit according to the first embodiment of the present invention, the time margin for setting the frequency division number control signal is set because the output signals of both frequency dividers 1A and 1B are in the H level period. The time margin for timing is (P / 2-0.5) clocks. As for the next setting timing, the minimum condition is to switch from the P frequency dividing operation to the P + 0.5 frequency dividing operation, which is P / 2 + 0.5 clock. In total, the interval is P, and the set time interval is , Linearly proportional to the frequency dividing number P. Therefore, when the frequency dividing number P exceeds 3, the time margin of the frequency dividing number setting signal in the frequency dividing circuit according to the first embodiment of the present invention becomes larger than that in the conventional circuit, and the frequency dividing number control is performed at a low speed operation. The signal can be controlled.

  FIG. 11 is a diagram schematically showing an example of the configuration of a portion for generating a frequency division control signal for the frequency divider circuit in the first embodiment of the present invention. In FIG. 11, the frequency division control signal generation unit includes a timing generator 15 that defines the timing at which the frequency division control signal is generated, a master / slave register 16 that stores data for identifying a master and a slave, and a frequency division number. Frequency division number setting circuit 17 to be set, and frequency division numbers for generating frequency division number control signals MXCNT, DVCNT1 and DVCNT2 in accordance with output signals / data of timing generator 15, master / slave register 16 and frequency division number setting circuit 17 A sequence control circuit 18 is included.

  Timing generator 15 asserts switching enable signal EN when both sub-divided signals DO1 and DO2 output from integer frequency dividers 1A and 1B shown in FIG. 1 are at the H level. The master / slave register 16 stores data identifying the master and slave variable integer frequency dividers in the current cycle. The frequency division number setting circuit 17 stores information specifying whether the frequency division number of the final frequency division signal DO is, for example, 8, 8.5, or 9.

  The frequency division sequence control circuit 18 identifies the frequency division sequence of the final frequency division output signal DO according to the frequency division number information set in the frequency division number setting circuit 17 and asserts the switching enable signal EN from the timing generator 15. Sometimes, the frequency division number control signals MXCNT, DVCNT1, and DVCNT2 are generated with reference to the master and slave information stored in the master / slave register 16. Next, the operation of the frequency division number control signal generator shown in FIG. 11 will be described.

(I) When the current cycle is the frequency division number P and the next cycle is the frequency division number P:
Now, in the master / slave register 16, the variable integer frequency divider 1A that starts the frequency division operation first (the sub frequency division signal rises to the H level first) is set as the master in the current cycle. The frequency division number setting signals DVCNT1 and DVCNT2 are both set to the frequency division number P, and the path selection signal MXCNT is set to select the master. Since the frequency division number is P in the current cycle and the next cycle, even if the switching enable signal EN from the timing generator 15 is asserted, the frequency division sequence control circuit 18 is in the state of the frequency division number control signals MXCNT, DVCNT1 and DVCNT2. To maintain.

(Ii) When the current cycle is the frequency division number P and the frequency division number of the final frequency division signal DO in the next cycle is P + 0.5:
Consider a state in which the variable integer frequency divider 1A is operating as a master in the current cycle. The frequency division sequence control circuit 18 sets the path selection signal MXCNT to a state in which the sub frequency division signal DO1 output from the master variable integer frequency divider 1A is selected, and both the frequency division number setting signals DVCNT1 and DVCNT2 are set. The frequency division number P is set to be designated.

  When the timing generator 15 asserts the switching enable signal EN, the frequency division sequence control circuit 18 sets the fraction setting signal DVCNT1 for the master variable integer frequency divider 1A to a state in which the frequency division number P is designated. Then, the frequency division number setting signal DVCNT2 for the slave variable integer frequency divider 1B is set to a state in which the frequency division number P is designated. The route selection signal MXCNT and the frequency division number setting signal DVCNT1 are not changed in the current cycle.

  When the current cycle is completed and the next cycle is entered, and the timing generator 15 asserts the switching timing signal EN again in accordance with the output frequency division signals DO1 and DO2, the frequency division sequence control circuit 18 generates the path selection signal MXCNT as a variable integer. In addition to setting the output signal of the frequency divider 1B, the data stored in the master / slave register 16 is set to a state indicating that the variable integer frequency divider 1B is the master. At this time, the frequency division number setting signal DVCNT1 for the variable integer frequency divider 1A is set to a state indicating the frequency division number P + 1. As a result, the time difference between the frequency-divided signals output from the master and the slave with respect to the P + 0.5 frequency-divided signal is always set to a state in which the frequency-divided signal from the master changes rapidly. When the sub-frequency-divided signal DO2 output from the variable integer frequency divider 1B is selected, a final frequency-divided signal DO having an H level period of P + 0.5 clock and an L level period of P / 2 clock is generated. , P + 0.5 division is performed.

(Iii) When the current cycle is the frequency division number P + 0.5 and the next cycle is the frequency division number P:
Assume that the master is the variable integer frequency divider 1A in the current cycle. In this case, in the current cycle, the path selection signal MXCNT is set to select the output frequency division signal DO1 of the master variable integer frequency divider 1A, and the variable frequency division number selection signals DVCNT1 and DVCNT2 are divided. The number P is set.

  In the current cycle, when the switching enable signal EN from the timing generator 15 is asserted, the frequency division sequence control circuit 18 selects the output frequency division signal DO2 of the variable integer frequency divider 1B of the current slave as the path selection signal MXCNT. And the frequency division number setting signal DVCNT1 is set to a state in which the frequency division number P + 1 is designated. The frequency division number setting signal DVCNT2 is maintained in a state in which the frequency division number P is designated. Further, the data stored in the master / slave register 16 is set to a state in which the variable integer frequency divider 1B is designated as a master. As a result, the output signal DO2 of the variable integer frequency divider 1B is selected, and the final frequency-divided signal DO is generated. At this time, the H level period of the final frequency-divided signal DO is extended by 0.5 clocks by the sub-frequency-divided signal DO2, and a P + 0.5 frequency-divided signal is generated.

  When the current cycle is completed, when the switching enable signal EN output from the timing generator 15 is asserted in the next cycle, the frequency division sequence control circuit 18 designates the frequency division number setting signal DVCNT1 and the frequency division number P. Set to the state to be used. The frequency division number setting signal DVCNT2 is maintained in a state in which the frequency division number P is designated, and the path selection signal MXCNT is also maintained in a state in which the output signal DO2 of the master variable integer frequency divider 1B is selected. Thereby, even when the frequency division number P + 0.5 is updated to the frequency division number P, the phase relationship between the output signals of the master and the slave can be maintained in the next cycle. In the next cycle, the final frequency-divided signal DO divided by P is generated in accordance with the output signal DO2 of the variable integer frequency divider 1B of the master.

(Iv) When the current cycle is the frequency division number P + 0.5 and the next cycle is the frequency division number P + 0.5:
Consider a state in which the master is a variable integer frequency divider 1A in the current cycle. At the start of the current cycle, the path selection signal MXCNT is set to select the output frequency division signal DO1 of the master variable integer frequency divider 1A. The frequency division number setting signal DVCNT1 is a state for designating the frequency division number P, and the frequency division number setting signal DVCNT2 is also a state for designating the frequency division number P.

  When the switching enable signal EN output from the timing generator 15 is asserted in the current cycle, the frequency division sequence control circuit 18 selects the output frequency division signal DO2 of the slave variable integer frequency divider 1B as the path selection signal MXCNT. And the data stored in the master / slave register 16 are set to a state indicating that the variable integer frequency divider 1B is the master. At this time, the frequency division number setting signal DVCNT1 for the variable integer frequency divider 1A is set to a state for designating the frequency division number P + 1. In the current cycle, according to the output signal DO2 of the variable integer frequency divider 1B, the H level period of the final divided signal DO becomes P / 2 + 0.5, and the final divided signal DO divided by P + 0.5 is generated.

  When the switching enable signal EN from the timing generator 15 is asserted again in the next cycle, the frequency division sequence control circuit 18 selects the output frequency division signal DO1 of the variable integer frequency divider 1A for the path selection signal MXCNT. At the same time, the data stored in the master / slave register 16 is set to a state indicating that the variable integer frequency divider 1A is the master. At this time, the frequency division sequence control circuit 18 sets the frequency division number setting signal DVCNT1 to a state for designating the frequency division number P, and sets the frequency division number setting signal DVCNT2 to the frequency division number P + 0.5. Set to. According to the output signal DO1 of the variable integer frequency divider 1A, a final frequency-divided signal DO divided by P + 0.5 is generated.

  When the P + 0.5 frequency division operation is continuously executed, the logic states of the hair color selection signal MXCNT and the frequency division number setting signals DVCNT1 and DVCNT2 are inverted in each frequency division clock cycle.

  In the above description, the variable integer frequency dividers 1A and 1B and the output signals DO1, DO2, and DO of the path switching circuit 2 are shown as being single-ended signals. However, these frequency-divided signals DO1, DO2, and DO may be differential signals composed of complementary signals.

  Further, the frequency division number control signals MXCNT, DVCNT1 and DVCNT2 do not need to have their logic states set at the same timing, and are within the time margin for setting the frequency division number control signals MXCNT, DVCNT1 and DVCNT2. It may be controlled individually.

  Further, the time relationship between the H level period and the L level period of the output frequency division signals DO1 and DO2 of the variable integer frequency dividers 1A and 1B at the time of P and P + 1 frequency division is not limited to the relationship shown in FIGS. The time length during which the logical levels of the sub-frequency-divided signals DO1 and DO2 are the same may be increased within a time range in which the frequency-number switching by the frequency-dividing number setting signals DVCNT1 and DVCNT2 can be reflected during the frequency-dividing operation. . When the frequency division control signals MXCNT, DVCNT1 and DVCNT2 are controlled within this long same logic level period, the allowable time range for the frequency division switching timing can be made longer than the allowable range shown in FIG. 5 and FIG. There is. As an example, when the frequency division number is 8, the clock level becomes H level for 5 clock cycles and becomes L level for 3 clock periods, and when the frequency division number is 9, it becomes H level for 5 clock cycles and becomes L level for 4 clock cycles. A frequency-divided signal is generated using a programmable counter. Assume that the phase of the output signal of the master and slave variable integer dividers is 0.5 clock cycles. In this case, 4 clock cycle periods can be secured as the control timing of the frequency division number control signal, and at least 8 clock cycle periods can be secured as two consecutive control timing switches.

  As described above, according to the first embodiment of the present invention, two variable integer frequency dividers that can divide by P and P + 1 are provided in parallel, and the phase of this divided output signal is set to a half clock. The output signals of these frequency dividers are selected by the path selection circuit to generate the final frequency divided signal. Therefore, the time margin of the timing for switching the frequency division number can be increased, and the frequency division number can be accurately changed even for a high-speed input clock signal.

[Embodiment 2]
FIG. 12 is a timing diagram representing an operation of the frequency dividing circuit according to the second embodiment of the present invention. The configuration of the frequency dividing circuit in the second embodiment is the same as that of the frequency dividing circuit according to the first embodiment shown in FIG. Therefore, the same signals as those in the first embodiment are used as the input clock signal and the frequency division number control signal, and these signals are denoted by the same reference numerals in FIG.

  In the operation sequence shown in FIG. 12, switching between P + 0.5 frequency division and P + 1 frequency division is performed. In FIG. 12, the case where the frequency dividing number P is 8 is shown as an example. Hereinafter, with reference to FIG. 12, the switching operation between the 9 frequency division and the 8.5 frequency division will be described.

  In FIG. 12, the period from time T0 to time T5 is a period during which the frequency division operation is performed. During this period, the path selection signal MXCNT is at the H level, and the sub-frequency-divided signal DO1 output from the variable integer frequency divider 1A is selected and output as the final frequency-divided signal DO. Frequency division number setting signals DVCNT1 and DVCNT2 are both at the H level, and a frequency division operation of 9 is designated for variable integer frequency dividers 1A and 1B. Accordingly, during this period, a frequency-divided signal of 9 is output in accordance with the output signal of the master variable integer frequency divider 1A.

  A period between time T5 and time T6 is a period of 8.5 frequency division operation. In this period, the path selection signal MXCNT is switched to the L level at time T6a during the period in which both the sub-divided signals DO1 and DO2 are at the H level, and the slave variable integer frequency divider 1B at that time outputs the sub Select the divided signal DO2. Further, the frequency division number setting signal DVCNT2 is set to L level, and the frequency division number P of the variable integer frequency divider 1B is designated to be frequency division by 8. Frequency division number setting signal DVCNT1 is maintained at the H level.

  Therefore, in the period T5 to T6, the final frequency division signal DO is 4.5 clock cycles in the H level period and 4 clock cycle periods in the L level period, and the final frequency division signal DO in the period of 8.5 clock cycles. Is generated.

  Next, the 8.5 frequency dividing operation is switched to the 9 frequency dividing operation, and the 9 frequency dividing operation is performed again in the period from time T6 to time T7. At time T6, when the sub divided signal DO2 output from the variable integer frequency divider 1B rises to H level, the sub divided signal DO1 output from the slave variable integer frequency divider 1A is still at the L level. Then, it rises to H level after a half clock cycle elapses.

  For example, at time T7a when both of the sub-divided signals DO1 and DO2 are at the H level, the frequency division number setting signal DVCNT2 is raised again to the H level, and the variable integer frequency divider 1B performs the frequency dividing operation by 9 specify. The path selection signal MXCNT is maintained at the L level, and the frequency division number setting signal DVCNT1 is maintained at the H level. Therefore, the sub-frequency-divided signal DO2 is selected as the final frequency-divided signal DO, and the final frequency-divided signal DO divided by 9 is generated in accordance with the frequency-dividing operation by 9 of the variable integer frequency divider 1B.

  In the case of continuously obtaining the frequency division signal of 9, the variable integer frequency dividers 1A and 1B are both set to the frequency division operation of 9, and the sub frequency division signal output from the master is selected. When the 8.5 frequency division signal is continuously obtained, the path selection signal is switched every clock cycle, and the frequency division number setting signals DVCNT1 and DVCNT2 are alternately switched by the frequency division operation and the frequency division operation of 8. The frequency division number of the master variable integer frequency divider is set to the frequency division operation of 8, and the frequency division number of the slave variable integer frequency divider is set to the frequency division operation of 9.

  As shown in FIG. 12, the time margin of the frequency division control signal when switching from the frequency division 9 operation to the frequency division 8.5 operation is 3.5 clock cycle periods from time T6b to time T6c. Even at the time of switching the frequency division operation by 9, there is a time margin for setting the frequency division control signal during the 3.5 clock cycle period from time T7b to time T7c.

  Further, there is at least a 5.0 clock cycle period from the time T6c to the time T7b before the frequency division number control signal is once set and then set. Therefore, the setting of the frequency division control signal for executing the 8.5 frequency division operation can be performed at an arbitrary time during 3.5 clock cycles. In addition, there is a time margin of 8.5 clock cycles until the setting of the frequency division number control signal for performing the next frequency division operation.

  On the other hand, the time margin of the frequency dividing number control signal in switching from the frequency dividing operation of 9 to the frequency dividing operation of 8.5 is similarly 3.5 clock cycles, and after the frequency dividing number control signal is once set. Next, there is at least a period of 5.5 clock cycles before the 8.5 frequency division operation is set. Therefore, there is a time margin of 9 clock cycles for switching from the 9 frequency dividing operation to the 8.5 frequency dividing operation.

  As described above, even when the frequency dividing number is switched between P + 1 and P + 0.5, the time margin for setting the frequency dividing number control signal is P / 2−0.5 clock cycles, and the frequency dividing number The interval of the state control of the number control signal is at least (P + 1) /2+0.5 clock cycle period. Therefore, the setting interval of the frequency division number control signal can be lengthened, and the frequency division number control signal can be controlled at a low speed.

  As the configuration of the control circuit for realizing the operation timing shown in FIG. 12, the configuration of the control signal generation unit described in Embodiment 1 with reference to FIG. 11 can be used. According to the frequency division number in frequency division number selection circuit 17, frequency division sequence control circuit 18 sets the state (logical value) of frequency division number control signals MXCNT, DVCNT1 and DVCNT2 in a predetermined sequence.

[Embodiment 3]
13 to 15 are timing diagrams showing the operation of the frequency dividing circuit according to the third embodiment of the present invention. In the third embodiment, the frequency dividing operation is performed with three types of frequency dividing numbers P, P + 0.5, and P + 1. 13 to 15 show an operation sequence when the frequency dividing number P is 8 as an example.

  The overall configuration of the frequency divider used in the third embodiment of the present invention is the same as that of the frequency divider shown in FIG. 1, and the frequency division control signal and the input clock signal are the same as those in the first embodiment. These signals are used. Therefore, the same reference numerals as those in the first embodiment are used for these input clock signal and frequency division number control signal. Hereinafter, with reference to FIGS. 13 to 15 in sequence, the frequency dividing operation according to the third embodiment of the present invention will be described as an example where the frequency dividing number P is 8.

  First, referring to FIG. 13, the operation when the frequency dividing number P is sequentially switched to 8, 8.5, and 9 will be described.

  In FIG. 13, the period between time T0 and time T8 is the divide-by-8 operation period. In this case, in the initial state of this cycle, path selection signal MXCNT is set to H level, and frequency division number setting signal DVCNT1 is at L level. At time T8a, the frequency division selection signal DVCNT2 falls to the L level, and the frequency division number of the variable integer frequency divider 1B is set to 8. The state of the route selection signal MXCNT and the frequency division number setting signal DVCNT1 is maintained.

  In this state, the output signal DO1 of the variable integer divider 1A is selected as the final divided signal DO. Therefore, in the period T0-T8, the variable integer frequency divider 1A operates as a master, and a frequency-divided signal with a frequency division number of 8 is generated.

  In the cycle starting from time T8, the variable integer frequency divider 1A is the master and the variable integer frequency divider is the slave. The frequency division number of these variable integer frequency dividers 1A and 1B is 8 at time T8. In this cycle, in order to realize the 8.5 frequency division operation, at time T9a, the path selection signal MXCNT is set to the L level, and the output signal DO2 of the variable integer frequency divider 1B is selected as the final frequency division signal DO. . At this time, the frequency division number selection signal DVCNT1 is set to the H level, and the frequency division number of the variable integer frequency divider 1A is set to 9. Variable frequency division number selection signal DVCNT2 is maintained at the L level.

  Therefore, in the cycle between time T8 and time T9, a signal divided by 8.5, in which the H level period is 4.5 clock cycles and the L level period is 4 clock cycles, is generated.

  In the period between time T9 and time T10, the 9-frequency division operation is executed. The frequency division number selection signal DVCNT1 is set to the H level at the previous time T9a. At the time T9 at the start of this cycle, the phase of the output frequency division signal DO1 of the variable integer frequency divider 1A is variable integer frequency division. The half-clock cycle is delayed from the frequency-divided signal DO2 output from the device 1B, and the phase relationship between the frequency-divided signals output from the master and the slave is maintained.

  At time T10a, the frequency division number setting signal DVCNT2 is set from L level to H level, and the frequency division number of the variable integer frequency divider 1B is set to 9. The frequency division number setting signal DVCNT1 of the variable integer frequency divider 1A is maintained at the H level, and the variable integer frequency divider 1A continues the frequency division operation of 9. The path selection signal MXCNT is at the L level, and selects the output signal of the master variable integer frequency divider 1B. Therefore, in this case, the frequency-divided signal DO2 output from the variable integer frequency divider 1B operating as a master is a frequency-divided signal by 9, and the final frequency-divided signal DO is a signal that has been frequency-divided by 9 according to the sub-frequency-divided signal DO2. can get.

  In the frequency dividing sequence shown in FIG. 13, the time margin for setting the frequency dividing number control signal is 3.5 clock cycles. The time margin between switching of the frequency division number control signal is 4.5 clock cycles from time T8c to time T9b. In this case, there is a total of 8.0 clock cycles. On the other hand, in the case of dividing from 8.5 clock division to 9 divisions, the period from time T9c to time T10b is 5 clock cycles, so there is a time margin of 8.5 clock cycles from time T9c to time T10c. Exists.

  FIG. 14 shows the frequency dividing operation when the frequency dividing number P is 8, and the frequency dividing operation of 9, the frequency dividing operation of 8.5, and the frequency dividing operation of 8 are successively executed.

  From time T0 to time T11, the variable integer frequency divider 1A operates as a master, and a final frequency-divided signal DO is generated according to the output signal DO1. In this case, frequency division number selection signals DVCNT1 and DVCNT2 are both set to the H level, and variable integer frequency dividers 1A and 1B are both performing a frequency division operation of 9. Therefore, in this period T0 to T11, a signal divided by 9 is generated as the final divided signal DO.

  In the period from time T11 to time T12, 8.5 frequency division operation is executed. At time T11, the variable integer frequency divider 1A operates as a master, and the sub-frequency-divided signal DO1 is selected and output as the final frequency-divided signal DO.

  At time T12a when both the sub-divided signals DO1 and DO2 are at the H level, the path selection signal MXCNT falls from the H level to the L level, and the frequency division number setting signal DVCNT2 of the variable integer frequency divider 1B is set to the L level. Then, the variable integer frequency divider is caused to execute the dividing operation by 8. The frequency division number setting signal DVCNT1 for the variable integer frequency divider 1A is at the H level, and the variable integer frequency divider 1A executes the frequency division operation by 9.

  Therefore, after time T12a, final frequency division signal DO is generated according to sub frequency division signal DO2 output from variable integer frequency divider 1B, and H level period is 4.5 clock cycles and L level period is 4.0 clock cycles. A period is generated and a signal divided by 8.5 is generated.

  In the period from the next time T12 to time T13, the divide-by-8 operation is executed. At time T12, the divided signal DO1 output from the variable integer divider 1A is delayed in phase by a half clock cycle from the divided signal DO2 output from the variable integer divider 1B. The phase relationship of the output signal of the instrument is maintained.

  At time T13a, the frequency division number selection signal DVCNT1 is set from H level to L level, and the frequency division number of the variable integer frequency divider 1A is set to 8. The path selection signal MXCNT is maintained at the L level, and the variable integer frequency divider 1B operates as a master. The variable integer frequency divider 1B performs a frequency division operation. Therefore, in the cycle from time T12 to time T13, a signal divided by 8 according to the signal DO2 generated by the variable integer frequency divider 1B is generated as the final frequency-divided signal DO.

  By setting the frequency division number of the slave variable integer frequency divider 1A to 8 at time T13a, the phase relationship between the output signals of the master and slave can still be maintained at time T13.

  Also in the frequency dividing sequence shown in FIG. 14, the time margin of the switching timing of the frequency dividing number control signal is 3.5 clock cycles from time T12b to time T12c and from time T13b to time T13c. The frequency division number control interval is 4.5 clock cycles from time T12c to time T13b. In this case, there is a time margin of 8 clock cycles from time T12c to time T13c. On the other hand, when the state of the frequency division number control signal is changed between time T0 and time T11, there is a time margin of 5.5 clock cycles and 3.5 clock cycles, which is a total of 9 clock cycles.

  Therefore, even in this case, the switching timing margin of the frequency division number control signal and the time margin of the switching interval can be set sufficiently large in proportion to the frequency division number P, and the frequency division number can be switched at a low speed operation. Can do.

  FIG. 15 is a timing chart showing an operation in the case where the frequency division number P is 8 and the frequency division by 8, the frequency division by 9, and the frequency division by 8 are continuously executed.

  In the period between time T0 and time T14, the divide-by-8 operation is performed. At the start of this cycle, the path selection signal MXCNT is set to the H level, the variable integer frequency divider 1A operates as a master, and the output sub-divided signal DO1 is selected and output as the final divided signal DO. The At this time, the frequency division number setting signals DVCNT1 and DVCNT2 are both at the L level, and both the variable integer frequency dividers 1A and 1B are performing the frequency division operation.

  In the period between time T14 and time T15, the 9-frequency division operation is executed. At time T14, the variable integer frequency divider 1A is selected as the master, and the sub-frequency-divided signal DO1 is selected and output as the final frequency-divided signal DO. At this time, as set in the previous cycle, both the variable integer frequency dividers 1A and 1B are performing the divide-by-8 operation.

  At time T15a when both of the sub-divided signals DO1 and DO2 are at the H level, the frequency division number setting signals DVCNT1 and DVCNT2 are both set to the H level, and the variable integer frequency dividers 1A and 1B are caused to execute the dividing operation by 9. The path selection signal MXCNT is maintained at the H level, and the variable integer frequency divider 1A operates as a master. Therefore, a signal divided by 9 is output as the final divided signal DO in accordance with the output signal DO1 of the variable integer frequency divider 1A.

  Next, in the period between time T15 and time T16, the divide-by-8 operation is performed. At time T15, variable integer frequency dividers 1A and 1B are both performing a frequency division operation of 9. At time T16a when both the sub-divided signals DO1 and DO2 are at the H level, the frequency dividing number setting signals DVCNT1 and DVCNT2 are both set to the L level, and both the variable integer frequency dividers 1A and 1B are caused to execute the dividing operation by 8. The path selection signal MXCNT is at the H level, and the variable integer frequency divider 1A operates as a master. Therefore, a signal divided by 8 is generated as the final frequency division signal DO according to the sub frequency division signal DO1. By changing the frequency dividing numbers of the variable integer frequency dividers 1A and 1B to 8, the phase relationship between the output signals of the master and slave is maintained at the start of the next cycle.

  In FIG. 15, when the frequency dividing operation and the frequency dividing operation are executed alternately, both frequency division number selection signals DVCNT1 and DVCNT2 are changed. This is because the phase relationship between the master and slave output signals is maintained in any cycle.

  In the operation sequence shown in FIG. 15, the setting time margin of the frequency division number control signal is 3.5 clock cycles from time T15b to time T15c and from time T16b to time T16c. On the other hand, there is at least a 5.5 clock cycle period from time T15c to time T16b as the time margin of the frequency division number control signal switching interval, and from time T16b to the next frequency division control signal switching timing. The interval is at least 4.5 clock cycles. Therefore, the state of the frequency division number control signal can be switched with a sufficient margin.

  As described above, in the case of changing from any of the dividing frequency of 8, 8, 8.5 and 9 to another dividing number, that is, P dividing, P + 0.5 dividing and P + 1 dividing Even in the switching of the frequency division number of the final frequency division signal between the circumferences, the time margin of the frequency division number control signal is 3.5 (= P / 2-0. 5) Exists for more than clock cycles. In addition, there is a time margin of at least 4.5 clock cycles (= P / 2 + 0.5 clock cycles) before the frequency division number control signal is once set and then subsequently set. Thereby, the setting interval of the frequency division number control signal is wide, and the frequency division number control signal can be controlled at a low speed.

  In the third embodiment as well, the configuration described with reference to FIG. 11 in the first embodiment can be used as the configuration for generating the frequency division number control signals MXCNT, DVCNT1 and DVCNT2. . In the frequency division sequence control circuit (FIG. 9), a frequency division number control signal is generated corresponding to the frequency division sequence in accordance with the set frequency division number.

[Embodiment 4]
FIG. 16 schematically shows a structure of a variable fractional frequency divider circuit according to the fourth embodiment of the present invention. In FIG. 16, the variable fractional frequency dividing circuit includes two variable integer frequency dividers 21A and 21B and sub frequency division signals DO1 and DO2 output from these variable integer frequency dividers 21A and 21B, as in the first embodiment. Includes a path switching circuit 2 that selects the signal according to the path selection signal MXCNT.

  Both the variable integer frequency dividers 21A and 21B can execute a fractional operation using two consecutive integers P and P + 1 as a frequency division number. The variable integer frequency divider 21A is supplied with a clock signal CLK1 having a duty of 50%, and the variable integer frequency divider 21B is supplied with a clock signal CLK1B having a duty of 50% complementary to the clock signal CLK1. The frequency division numbers of the variable integer frequency dividers 21A and 21B are set by frequency division number setting signals DVCNT1 and DVCNT2, respectively.

  In the configuration of the variable fractional frequency dividing circuit shown in FIG. 16, single-ended clock signals CLK1 and CLK1B are applied to the positive phase inputs of variable integer frequency dividers 21A and 21B, respectively. The clock signals CLK1 and CLK1B are complementary to each other. Therefore, at the time when the variable integer dividers 21A and 21B start dividing (when the H-level sub-divided signal is generated), the input clock signal CLK1 There is a phase difference of half clock cycle period.

  The variable integer dividers 21A and 21B have the same internal configuration, and are merely different in the phases of the clock signals CLK1 and CLK1B to be applied. Therefore, path switching circuit 2 also selects output signals DO1 and DO2 of variable integer frequency dividers 21A and 21B according to path selection signal MXCNT in the same manner as described in the first to third embodiments. Therefore, even in the operation of the variable fractional frequency dividing circuit shown in FIG. 16, the same operation as that described in the first to third embodiments can be realized.

  In the fourth embodiment, the variable integer frequency dividers 21A and 21B operate sufficiently fast even when a circuit that operates according to a single-ended clock signal instead of a differential clock signal is prepared as a library macro. It is possible to realize a variable fractional frequency dividing circuit capable of switching fractions with a margin even at times.

[Embodiment 5]
FIG. 17 schematically shows a configuration of a fractional frequency dividing circuit according to the fifth embodiment of the present invention. Also in the variable fractional frequency dividing circuit shown in FIG. 17, two variable integer frequency dividers 22 and 23 and a path switching circuit 2 are provided. The variable integer divider 22 generates the sub-divided signal DO1 in synchronization with the rising of the clock signal CLK2 having a duty of 50%. During the dividing operation, the variable integer divider 22 follows two integers according to the dividing number setting signal DVCLT1. A frequency division operation is executed at either P or P + 1.

  The variable integer frequency divider 23 generates a sub-frequency-divided signal DO2 in synchronization with the fall of the clock signal CLK2 having a duty of 50%, and divides the frequency by one of the frequency-dividing numbers P and P + 1 according to the frequency-dividing number setting signal DVCNT2. Perform the action.

  The path switching circuit 2 selects one of the output signals DO1 and DO2 of the variable integer frequency dividers 22 and 23 according to the path selection signal MXCNT and generates a final frequency division signal DO.

  In the configuration of the variable fractional frequency dividing circuit shown in FIG. 17, only one clock signal CLK2 is used, and the trigger edges of the input clock signals at which the frequency dividers 22 and 23 start the frequency dividing operation are different from each other. Therefore, the frequency division operation start timings of output signals DO1 and DO2 of variable integer frequency dividers 22 and 23 are shifted by a half clock cycle period of input clock signal CLK2, and are the same as those shown in the first to fourth embodiments so far. An operation similar to that of the peripheral circuit can be realized.

  Note that the configuration shown in FIG. 11 can be used as the configuration of the circuit that generates the frequency division number control signal.

  In the configuration of the fractional frequency dividing circuit according to the fifth embodiment of the present invention, even when a single-ended input clock signal is commonly supplied to a variable integer frequency divider, the trigger edge of the frequency division operation is a half cycle of the input clock signal. Therefore, the frequency dividing operation can be accurately performed with the set frequency dividing number, and the same effects as those of the first to fourth embodiments can be obtained.

[Embodiment 6]
FIG. 18 schematically shows a structure of a variable fractional frequency dividing circuit according to the sixth embodiment of the present invention. The configuration of the variable fractional frequency dividing circuit shown in FIG. 18 is different from the configuration of the variable fractional frequency dividing circuit shown in FIG. 1 in the following points. That is, a differential conversion circuit (SD) 25 that receives an input clock signal CLK2 with a duty of 50% and generates differential clock signals CLK3 and CLK3B with a duty of 50% is provided in the preceding stage of the variable integer frequency dividers 1A and 1B. . Differential clock signals CLK3 and CLK3B from the differential conversion circuit 25 are respectively applied to the positive phase input and the negative phase input of the variable integer frequency divider 1A, and the negative phase input and the adjustment of the variable integer frequency divider 1B. Is given to the phase input.

  The other configuration of the variable fractional frequency dividing circuit shown in FIG. 18 is the same as that of the variable fractional frequency dividing circuit shown in FIG. 1, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  For example, the differential conversion circuit 25 is configured by a differential amplifier circuit that differentially amplifies the reference voltage and the input clock signal CLK2, for example, and converts a single-ended signal into a differential signal. The differential conversion circuit 25 only needs to have a function of converting a single-ended signal into a differential signal, and its internal configuration is not particularly limited.

  In the case of the configuration of the variable fractional frequency dividing circuit shown in FIG. 18, the frequency dividing operation can be performed according to one single-ended input clock signal CLK, and differential clock signals CLK3 and CLK3B are supplied from differential converting circuit 25. Therefore, the differential clock signals CLK3 and CLK3B that are out of phase by a half clock cycle can be accurately supplied to the variable integer frequency dividers 1A and 1B, respectively. Further, the same effects as those of the frequency dividing circuits of the first to fifth embodiments can be obtained.

[Embodiment 7]
FIG. 19 schematically shows a structure of a variable fractional frequency dividing circuit according to the seventh embodiment of the present invention. In the variable fractional frequency dividing circuit shown in FIG. 19, two variable integer frequency dividers 26A and 26B are provided in parallel. The variable integer frequency dividers 26A and 26B are different from the variable integer frequency dividers 1A and 1B shown in FIG. 1 in the following points. That is, variable integer frequency dividers 26A and 26B have their current consumption reduced according to frequency-divided power save signals DIVPS1 and DIVPS2. When the operating current is reduced during the frequency dividing operation, the operating speed is reduced, and the frequency dividing number is increased from the set frequency dividing number. Therefore, when the operating currents of the variable integer frequency dividers 26A and 26B are reduced according to the frequency-divided power save signals DIVPS1 and DIVPS2, the operating current is reduced to the extent that the frequency-dividing operation is not adversely affected.

  In variable integer frequency dividers 26A and 26B, the input clock signal and the frequency division number setting signal applied to each are the same as those in the first embodiment, and the respective frequency dividing operations themselves are shown in the first embodiment. This is the same as the frequency dividing operation of each of the variable integer frequency dividers 1A and 1B, and detailed description of these signals and frequency dividing operation is omitted.

  Sub-frequency-divided signals DO1 and DO2 output from variable integer frequency dividers 26A and 26B are selected by path switching circuit 2 in accordance with path selection signal MXCNT, and final frequency-divided signal DO is generated. When the P frequency dividing operation is continuously performed, in the variable integer frequency dividers 26A and 26B, the output signal of the variable integer frequency divider that operates as the master is used as the final frequency divided signal, and the variable integer frequency component that operates as the slave is used. The output signal of the peripheral is not used. By reducing the operating current of the variable integer frequency divider that operates as the slave, the current consumption is reduced without affecting the frequency-divided signal.

  FIG. 20 schematically shows a structure of variable integer frequency divider 26A according to the seventh embodiment of the present invention. The variable integer frequency divider 26B has the same configuration.

  In FIG. 20, a variable integer frequency divider 26 </ b> A receives the input clock signals CLK <b> 1 and CLK <b> 1 </ b> B by the positive phase input and the negative phase input, respectively, and divides the operating current to the divider main body 30. Current sources 31a and 31b to be supplied are included.

  The frequency divider main body 30 is composed of a program counter or a flip-flop train, and performs a frequency dividing operation with the frequency dividing number P or P + 1 to generate the sub frequency dividing signal DO1. The upper current source 31a supplies current from the power supply node VCC to the frequency divider main body 30 in accordance with the frequency-divided power save signal DIVPS1. Lower current source 31b discharges the operating current from frequency divider main body 30 to the ground node in accordance with frequency-divided power save signal DIVPS1. The amount of current supplied from these current sources 31a and 31b is adjusted according to the divided power save control signal DIVPS1. As an example, current sources 31a and 31b are formed of two parallel MOS current source transistors, one of which is always on to charge / discharge current, and the other is selectively turned on / off according to divided power save signal DIVPS1. Is set. Thereby, the operating current amount of the frequency divider main body 30 is adjusted between the current driving by the two MOS current source transistors and the current driving by the one current source transistor.

  Instead, the voltage level of the divided power save signals DIVPS1 and DIVPS2 is set to an intermediate voltage level between the power supply voltage VCC and the ground voltage, and the amount of current flowing through the current sources 31a and 31b is reduced. Also good.

  FIG. 21 schematically shows a structure of a portion for generating a frequency dividing number control signal according to the frequency dividing circuit according to the seventh embodiment of the present invention. The configuration of the frequency division number control signal generation unit shown in FIG. 21 is different from the configuration of the frequency division number control signal generation unit shown in FIG. 11 in the following points. That is, frequency division sequence control circuit 35 generates frequency division power save signals DIVPS1 and DIVPS2 in addition to frequency division number control signals MXCNT, DVCNT1, and DVCNT2.

  The frequency division sequence control circuit 35 continuously executes P frequency division or P + 1 frequency division according to the frequency division number of the final frequency division signal DO set in the frequency division number setting circuit 17, and at which point P It is possible to discriminate whether to shift from frequency division to P + 0.5 frequency division or P + 1 frequency division to P + 0.5 frequency division.

  Further, according to the master / slave identification data (flag) stored in the master / slave register 16, the frequency division sequence control circuit 35 determines which of the variable integer frequency dividers 26A and 26B is a master and which is a slave. Can be identified. Therefore, the divided power save signal DIVPS1 or DIVPS2 for the slave variable integer frequency divider is asserted to reduce the operating current of the slave variable integer frequency divider.

  Switching between the master and the slave is performed when the P + 0.5 frequency division operation is executed. Therefore, before starting the P + 0.5 frequency division, the frequency division power save signal DIVPS1 or DIVPS2 for the variable integer frequency divider of the slave at that time is negated, and the operating current of the variable integer frequency divider of the slave is restored to the original state. Then, the variable integer frequency divider changed from the slave to the master is caused to execute the P frequency division or P + 1 frequency division operation.

  The timing of returning the operating current of the slave variable integer frequency divider to the original state and the amount of reduced current are determined by the frequency divider body 30 of the variable integer frequency dividers 26A and 26B according to the input clock signals CLK1 and CLK1B. It may be determined in consideration of the pull-in time until the P or P + 1 frequency division is accurately executed.

  In the above description, the operating current of the slave variable integer frequency divider is reduced. However, the operating current of the slave variable integer divider is completely stopped, and the current consumption of the slave variable integer divider is restored to the original operating state before the start of the P + 0.5 division. The states of the peripheral power save signals DIVPS1 and DIVPS2 may be set. In this case, the current sources 31a and 31b in the configuration shown in FIG. 20 need only be set to the cutoff state in the slave variable integer frequency divider.

  The voltage level of the power supply voltage (VCC) supplied to the frequency divider main body 30 may be changed by the frequency-divided power save signals DIVPS1 and DIVPS2. In this case, the operating power supply voltage of the slave variable integer frequency divider is lowered.

  As described above, in the seventh embodiment of the present invention, the current consumption of the slave integer frequency divider is reduced, and the current consumption of the entire frequency divider circuit can be reduced.

  In the seventh embodiment of the present invention, a single-ended clock signal may be used as the input clock signal.

[Embodiment 8]
FIG. 22 schematically shows a structure of a variable fractional frequency dividing circuit according to the eighth embodiment of the present invention. In FIG. 22, the variable fractional frequency dividing circuit is in accordance with two variable integer frequency dividers 37A and 37B, path switching circuit 2, and frequency division number transmission signals CNTD1 and CNTD2 from two variable integer frequency dividers 37A and 37B. And a route selection signal generation circuit 38 that generates a route selection signal MXCLT2.

  The variable integer frequency divider 37A receives the clock signals CLK1 and CLK1B having a duty of 50% at the positive phase input and the negative phase input, respectively, and divides the clock signals CLK1 and CLK1B by either the frequency division number P or P + 1 according to the frequency division number setting signal DVCNT3. The sub-frequency signal DO1 is generated by performing the frequency operation, and the frequency division state notification signal D12 indicating the frequency division state is supplied to the variable integer frequency divider 37B. The variable integer frequency divider 37A further generates a frequency division number transmission signal CNTD1 indicating the frequency division number setting status and supplies it to the path selection signal generation circuit 38. The frequency division state notification signal D12 is a signal indicating the phase of the sub frequency division signal DO1, and is generated according to the sub frequency division signal DO1.

  The variable integer frequency divider 37B receives the input clock signals CLK1 and CLK1B at the negative phase input and the positive phase input, respectively, and performs a frequency division operation at either the frequency division number P or P + 1 according to the frequency division number setting signal DVCNT3. A frequency division number transmission signal CNTD2 indicating a frequency division number setting status is generated and transmitted to the path selection signal generation circuit 38, and a frequency division state notification signal D21 is further generated to generate a variable frequency division signal DO2. To container 37A.

  The frequency division state notification signals D12 and D21 correspond to the states of the respective sub frequency division signals DO1 and DO2, and the variable integer frequency dividers 37A and 37B follow the frequency division state notification signals D12 and D21, respectively. It determines whether it is operating as a master or a slave.

  When the frequency division number transmission signals CNTD1 and CNTD2 from these variable integer frequency dividers 37A and 37B indicate the same frequency division number, the path selection signal generation circuit 38 sets the path selection signal MXCNT1 unchanged and changes its state. If the frequency division number transmission signals CNTD1 and CNTD2 indicate different frequency division numbers, the route selection signal generation circuit 38 changes the state of the route selection signal MXCNT2 and exchanges the master and the slave. To do.

  The path switching circuit 2 receives the path selection signal MXCNT2 at the selection input S, selects one of the output signals DO1 and DO2 of the variable integer frequency dividers 37A and 37B, and generates a final frequency division signal DO. Next, the operation principle of the variable fractional frequency dividing circuit according to the eighth embodiment shown in FIG. 22 will be described.

  The variable integer frequency dividers 37A and 37B generate frequency division state notification signals D12 and D21 indicating the frequency division operation start timing (rising timing of the sub frequency division signal), respectively, and send them to the other variable integer frequency dividers 37B and 37A. Communicate each. The variable integer frequency dividers 37A and 37B respectively identify which frequency division state is faster by 0.5 clock cycles based on the frequency division state notification signals D12 and D21. It is determined that it is a master.

  When P + 0.5 frequency division operation is instructed by a frequency division number setting signal DVCNT3 from a control unit (not shown) from outside, a period in which both output signals DO1 and DO2 of variable integer frequency dividers 37A and 37B are at the H level. The variable integer frequency divider of the master sets the frequency division number to P + 1, and the variable integer frequency divider of the slave sets to P frequency division. Further, after this setting, frequency division number transmission signals CNTD1 and CNTD2 indicating the frequency division number are generated from the master and slave variable integer frequency dividers and supplied to the path selection signal generation circuit 38.

  Now, when P + 0.5 frequency division is instructed by the frequency division number setting signal DVCNT3, the frequency division number of the master variable integer frequency divider at the beginning of this cycle is set to P + 1, and the slave variable integer frequency divider is The frequency division number set by P division and indicated by the frequency division number transmission signals CNTD1 and CNTD2 is different. At this time, the path selection signal generation circuit 38 switches the logic state of the path selection signal MXCNT2 and switches the selection path in the path switching circuit 2. In this state, the slave variable integer frequency divider performs the P frequency division operation, and the master variable integer frequency divider performs the P + 1 frequency division operation. Therefore, an operation similar to the operation described in the first embodiment is performed, the final frequency-divided signal DO whose H level period is increased by 0.5 clocks is generated, and the P + 0.5 frequency-divided signal is generated.

  On the other hand, when P frequency division is instructed by the frequency division number setting signal DVCNT3, the variable integer frequency divider of the master at the beginning of the cycle is set to P, and the variable integer frequency divider of the slave also sets the frequency division number. Set to P. Accordingly, the frequency division number transmission signals CNTD1 and CNTD2 are both set to a state instructing the P frequency division operation, and the logic levels thereof are the same, and the path selection signal generation circuit 38 maintains the logic state of the path selection signal MXCNT2. However, the selection path of the path switching circuit 2 is maintained without being switched. Thereby, an operation similar to the operation described in the first embodiment is realized, and a P frequency division signal is generated as the final frequency division signal DO according to the output signal of the master variable integer frequency divider.

  When the frequency division number setting signal DVCNT3 instructs P + 1 frequency division operation, the master variable integer frequency divider at the beginning of the cycle sets the frequency division number to P + 1, and the slave variable integer frequency divider also Set the frequency division number to P + 1. Accordingly, the frequency division number transmission signals CNTD1 and CNTD2 from the master and slave variable integer frequency dividers have the same logic state, and the path selection signal generation circuit 38 determines the logic of the path selection signal MXCNT2 for the path switching circuit 2. Maintain state. Thereby, an operation similar to the operation described in the second embodiment is realized, and the P + 1 frequency-divided signal from the master is selected and output as the final frequency-divided signal DO.

  FIG. 23 schematically shows an example of the configuration of variable integer frequency divider 37A shown in FIG. The variable integer frequency divider 37B also has the same configuration and differs only in the internal signal.

  In FIG. 23, a variable integer frequency divider 37A includes a P / P + 1 frequency dividing circuit 40 that divides the frequency by one of two consecutive integers P and P + 1, and whether the variable integer frequency divider 37A is a master or a slave. A master / slave determination circuit 42 for determining whether or not, a switching timing generation circuit 44 for generating a frequency division number switching timing, a master / slave instruction flag MSF from the master / slave determination circuit 42, and an external control circuit A frequency division number setting unit 46 that generates a frequency division number transmission signal CNTD1 according to the frequency division number setting signal DVCNT3 is included.

  P / P + 1 frequency dividing circuit 40 corresponds to variable integer frequency divider 1A in the first embodiment, and performs a frequency dividing operation according to differential clock signals CLK1 and CLK1B having a duty of 50%.

  The master / slave determination circuit 42 receives the output signal DO1 of the P / P + 1 frequency dividing circuit 40 and the output signal DO2 of the counterpart variable integer frequency divider 37B shown in FIG. 22 as frequency division state notification signals D12 and D21, respectively. When the rising of the divided state notification signal D12 to the H level is earlier than the rising of the divided state notification signal D21, the master / slave instruction flag MSF is instructed by the variable integer frequency divider 37A as the master. Set to state. On the other hand, when the divided state notification signal D21 rises at a timing earlier than the rising of the divided state notification signal D12, the master / slave determination circuit 42 sets the master / slave instruction flag MSF to a state for designating the slave. To do. As a configuration of the master / slave determination circuit 42, for example, a configuration of a phase detection circuit that detects a phase difference between an input clock signal and an output clock signal in a PLL can be used.

  Frequency division state notification signals D12 and D21 correspond to sub frequency division signals DO1 and DO2, respectively, and switching timing generation circuit 44 asserts switching enable signal ENA1 when both are at the H level.

  When the switching enable signal ENA1 is asserted, the frequency division number setting unit 46 divides the frequency division number setting signal DVCNT1 according to the master / slave instruction flag MSF and the frequency division number setting signal DVCNT3 from the master / slave determination circuit 42. The state is set to indicate either the number P or P + 1. Next, the state of the frequency division number setting signal DVCNT1 is held until the switching enable signal ENA is asserted.

  The frequency division number setting unit 46 divides the frequency division number selection setting signal DVCNT1 when the frequency division number setting signal DVCNT3 indicates P + 0.5 frequency division, or when the master / slave instruction flag MSF indicates the master. On the other hand, when the master / slave instruction flag MSF indicates the slave, the frequency division setting signal DVCNT1 is set to the state where the frequency division number P is specified.

  On the other hand, when frequency division number setting signal DVCNT3 instructs P frequency division, in both cases where master / slave instruction flag MSF instructs the master and slaves, frequency division number setting unit 46 A frequency division number setting signal DVCNT1 is set so as to perform the P frequency division operation. When the frequency division number setting signal DVCNT3 designates P + 1 frequency division, the frequency division number setting signal DVCNT1 is selected so that the frequency division number P + 1 is selected even when the master / slave instruction flag MSF designates either master or slave. Set.

  The variable integer frequency divider 37B shown in FIG. 22 has the same configuration as that of the variable integer frequency divider 37A shown in FIG. 23, and only the generated signal is different. Thereby, each of the variable integer frequency dividers 37A and 37B can determine its own state and set the frequency division number according to the frequency division number of the designated final frequency division signal.

  FIG. 24 schematically shows an example of the configuration of path selection signal generation circuit 38 shown in FIG. In FIG. 24, a path selection signal generation circuit 38 includes a match determination circuit 50 that determines whether the frequency division number transmission signals CNTD1 and CNTD2 match or does not match, and path switching that generates a path selection signal MXCNT2 according to the output signal of the match determination circuit 50. A control circuit 52 is included.

  The coincidence determination circuit 50 determines whether or not the logic levels of the frequency division number transmission signals CNTD1 and CNTD2 coincide with each other when the switching enable signals ENA1 and ENA2 from the variable integer frequency dividers 37A and 37B are both asserted.

  The path switching control circuit 52 determines the logic level of the output signal of the coincidence determination circuit 50 when both the switching enable signals ENA1 and ENA2 are asserted, and sets the state of the path selection signal MXCNT2 according to the determination result. The path switching control circuit 52 enters a latched state when the switching enable signals ENA1 and ENA2 are both negated. As an example, the coincidence determination circuit 50 is composed of, for example, an EXOR circuit. When the output signal of the EXOR circuit is at the H level and indicates a mismatch, the logical state of the output signal of the path switching control circuit 52 is changed to select a path. The signal MXCNT2 is changed to switch the master / slave. In this case, the path switching control circuit 52 may be constituted by a T flip-flop, and the output signal of the EXOR circuit may be given to its clock input.

  FIG. 25 is a diagram schematically showing an example of the configuration of a part that generates the frequency division number setting signal DVCNT3. In FIG. 25, the frequency division number setting signal generator generates a frequency division number setting circuit 62 for setting the frequency division number of the final frequency division signal (DO), and the frequency division number set by the frequency division number setting circuit 62. A frequency division sequence determination unit 64 that determines a frequency division sequence is included.

  In frequency division number setting circuit 62, for example, the frequency division number of final frequency division signal DO generated in a PLL frequency synthesizer is set. The frequency division sequence determination unit 64 determines the P frequency division, P + 0.5 frequency division, and P + 1 frequency division sequences according to the set frequency division number, and performs frequency division in synchronization with the input clock signal CLK1 according to the determined sequence. A frequency setting signal DVCNT3 is generated. At this time, the frequency dividing sequence determining unit 64 knows the frequency dividing number in the next cycle in advance, counts this input clock signal CLK1, and sets the frequency dividing number setting signal DVCNT3 at the start of each frequency dividing cycle. Set the state. Alternatively, the frequency division sequence determination unit 64 may set the frequency division number setting signal DVCNT3 to indicate the frequency division number in the next cycle during the period when the final frequency division signal DO is at the L level. In this case, at the start of the next cycle, the final frequency division signal of the next cycle is maintained in a state indicating the frequency division number, and this state is maintained until the final frequency division signal DO becomes L level.

  As described above, according to the eighth embodiment of the present invention, the variable integer frequency divider is provided with a circuit for generating the frequency division number selection signal, and the master variable integer frequency division is performed according to the frequency division number transmission signal. The transmission path of the sub-divided signal is switched by setting a device. Therefore, only the frequency division number setting signal (DVCNT3) for designating the frequency division number in each frequency division cycle need only be externally supplied, the number of control signals can be reduced, and the wiring area and power consumption can be reduced. be able to.

[Embodiment 9]
FIG. 26 schematically shows a structure of a variable fractional frequency dividing circuit according to the ninth embodiment of the present invention. In FIG. 26, variable integer frequency dividers 70A and 70B are provided in parallel, and a path switching circuit 2 for selecting output signals DO1 and DO2 of these variable integer frequency dividers 70A and 70B in accordance with path selection signal MXCNT is provided. It is done.

  Variable integer frequency dividers 70A and 70B differ in configuration from variable integer frequency dividers 1A and 1B shown in FIG. 1 in the following points. That is, these variable integer frequency dividers 70A and 70B are reset in frequency division operation in accordance with the frequency division reset signal DVRST, and start the frequency division operation from the initial value again. When these variable integer frequency dividers 70A and 70B are constituted by programmable counters, for example, the count operation is reset in accordance with frequency division reset signal DVRST, the count value returns to the initial value, and the count operation is performed again. Execute frequency division. On the other hand, when variable integer frequency dividers 70A and 70B are formed of flip-flop trains, frequency-divided reset signal DVRST is applied to the reset input of the signal of each flip-flop train, and each is set to an initial state.

  Other configurations of variable integer frequency dividers 70A and 70B are the same as those of variable integer frequency dividers 1A and 1B of the frequency dividing circuit according to the first embodiment shown in FIG. 1, and frequency division number setting signals DVCNT1 and DVCNT2 Accordingly, the differential clock signals CLK1 and CLK1B having a duty of 50% are frequency-divided by the frequency dividing number P or P + 1 to generate sub-frequency-divided signals DO1 and DO2, respectively.

  Similarly to the case of the first embodiment, path switching circuit 2 selects one of the output signals of variable integer frequency dividers 70A and 70B in accordance with path selection signal MXCNT and generates final frequency division signal DO. Therefore, the frequency dividing operation itself excluding the resetting operation of the fractional frequency dividing circuit shown in FIG. 26 is the same as the frequency dividing operation of the frequency dividing circuits of the first to third embodiments.

  The frequency division reset signal DVRST is asserted when the phase difference between the output signals DO1 and DO2 of the variable integer frequency dividers 70A and 70B exists for a half clock cycle or more of the input clock signal CLK1. That is, when the power is turned on, there is a case where the divided signals DO1 and DO2 of the variable phasing dividers 70A and 70B deviate by more than a half clock cycle of the input clock signal CLK1 due to an error in circuit startup time. When such a difference occurs, it is impossible to accurately perform frequency division with a step size of 0.5. By using the frequency division reset signal DVRST, the frequency division signals DO1 and DO2 having a phase difference of 0.5 clock cycle can be accurately generated, and the frequency division operation with fractional precision can be executed.

  FIG. 27 is a diagram schematically showing an example of the configuration of a part that generates the frequency division reset signal DVRST. In FIG. 27, the frequency division reset signal generator generates a phase difference detection circuit 76 that detects the phase difference between the output signals DO1 and DO2 of the variable integer frequency dividers 70A and 70B, and a reset signal according to the output signal of the phase difference detection circuit 76. A reset signal generating circuit 77 for generating DVRST.

  The phase difference detection circuit 76 includes, for example, a mismatch detection circuit that generates a signal corresponding to a period in which the logic levels of the sub-divided signals DO1 and DO2 are different, a circuit that charges a capacitive element in accordance with an output signal of the mismatch detection circuit, It is comprised with the charge potential detection circuit of an element. This capacitive element is discharged when the phase difference between the sub-frequency-divided signals DO1 and DO2 matches 0.5 clock. When the charging potential of the capacitive element becomes equal to or higher than a predetermined level, it is determined that the phase difference is half a clock or more, and the frequency division reset signal DVRST is asserted.

  Instead of this, the phase difference detection circuit 76 may be configured by a counter that counts periods in which the logic states of the sub-frequency-divided signals DO1 and DO2 are different with respect to 0.5 clocks. When the count value of the counter exceeds a predetermined value, it is determined that the phase difference is equal to or greater than half a clock, and the frequency division reset signal DVRST is asserted.

  The critical value of the phase difference in the case where the frequency division reset signal DVRST is asserted may not be a half clock cycle, and is appropriately determined according to, for example, a synchronization pull-in period of a PLL frequency synthesizer in which a variable fractional frequency dividing circuit is used. It may be determined.

  As described above, according to the ninth embodiment of the present invention, when the phase difference between the output signals of the two variable integer dividers is equal to or greater than a predetermined value of 0.5 clock cycles, for example, The frequency dividing operation is reset. Therefore, in addition to the effect of the first embodiment, it is possible to accurately generate a frequency-divided signal having a phase difference of 0.5 clock cycle and execute the frequency-dividing operation.

Note that the configurations of the fractional frequency dividing circuits of the first to ninth embodiments may be used in appropriate combination.
[Embodiment 10]
FIG. 28 schematically shows a structure of a variable fractional frequency dividing circuit according to the tenth embodiment of the present invention. In FIG. 28, N + 1 variable integer frequency dividers 80 having the same configuration are provided in parallel. In the following description, these variable integer frequency dividers are denoted by symbols DIV0 to DIVN in order to distinguish them from each other. Variable integer frequency divider DIVk (one of k = 0 to N) receives differential clock signals CLK4k and CLK4kB having a duty of 50% at the positive phase input and the negative phase input, respectively, and divides by frequency division number P or P + 1. An operation is performed to generate a sub-divided signal DOk. These variable integer frequency dividers DIV0 to DIVN have their frequency division numbers set according to frequency division number setting signals DVCNT40 to DVCNT4N.

  A path switching circuit 82 is provided for selecting the output signals DO0-DON of the variable integer frequency dividers DIV0-DIVN. The path switching circuit 82 selects one of the output signals DO0-DON of the variable integer frequency dividers DIV0-DIVN according to the path selection signal MXCNT3, and generates the final frequency-divided signal DO.

  FIG. 29 shows an example of the phase relationship between clock signals CLK40, CLK40B-CLK4N and CLK4NB supplied to variable integer frequency dividers DIV0 to DIVN shown in FIG. In FIG. 29, clock signals CLK4k and CLK4 (k + 1) applied to variable integer frequency dividers DIVk and DIV (k + 1) are out of phase by ΔT. Here, ΔT is T / (N + 1), and T is one clock cycle period of the input clock signals CLK40 to CLK4N. Here, it is an integer satisfying 0 ≦ J <N and N ≧ 1.

  Therefore, the phase of the input clock signal CLK4J supplied to the variable integer frequency divider DIVJ is delayed by the period J · ΔT with respect to the input clock signal CLK40. On the other hand, the input clock signal CLK4N applied to the variable integer frequency divider DIVN is delayed by a period N · ΔT with respect to the input clock signal CLK40. Next, the operation of the variable fractional frequency dividing circuit shown in FIG. 28 will be described. 30 to 32 are timing charts showing the operation of the variable fractional frequency dividing circuit shown in FIG. Hereinafter, the frequency division operation switching of the variable fractional frequency dividing circuit shown in FIG. 28 will be described with reference to FIGS.

  First, with reference to FIG. 30, a description will be given of a case where P + A / (N + 1) frequency division is performed from the state where the J-th variable integer frequency divider DIVJ serves as a master and performs frequency division operation. To do. A is an integer of 0 <A <N + 1. In contrast to the output signal DOJ of the master variable integer frequency divider DIVJ, the slave variable integer frequency divider delays its output signal by ΔT as its number is incremented by 1. This delay amount is determined by the divided signal DON. And cyclically changed under DO0 and incremented.

  When the P + A / (N + 1) frequency division is performed, the MOD (A + J, N + 1) th is generated by the path selection signal MXCNT3 at the time ta when the output signals DO0-DON of the variable integer frequency dividers DIV0-DIV are all at the H level. That is, the division number of the variable integer divider (DIVk) corresponding to the result of the modulo (N + 1) of (A + J), that is, the remainder number of (A + J) / (N + 1) is set to P The output signal (DOk) of the variable integer divider (DIVk) whose number is set to P is selected to generate the final divided signal DO.

  At this time, in order to maintain the phase relationship between the output signals of the master and the slave, a frequency division operation is executed prior to the sub-frequency-divided signal DOk in FIG. 30, and the sub-frequency-divided signal rises to the H level first. That is, the frequency division number of the variable integer frequency divider that outputs the sub frequency division signals DOJ to DO (k−1) is set to P + 1, and the frequency division number of the remaining variable integer frequency dividers is set to P. By this operation, the final frequency-divided signal DO has the H level period extended by A / (N + 1) clock cycles, and P + A / (N + 1) frequency division is realized. The output signal of the variable integer frequency divider of the slave is delayed in phase with respect to the output signal of the variable integer frequency divider of the adjacent numbers sequentially by ΔT.

  The state selection of the path selection signal MXCNT and the frequency division number setting signals DVCNT40 to DVCNT4N is performed during a period when all the sub frequency division signals DO0 to DON are at the H level. This H level period is at least P / 2−N / (N + 1) clock cycle periods. Therefore, as described in the ninth embodiment, if the frequency division number P is 4, there is a timing margin of 1.5 clock cycles or more, and the frequency division number is switched with a sufficient margin. Can do.

  Next, with reference to FIG. 31, the operation when the P + 1 frequency dividing operation is performed next with the variable integer frequency divider DIVJ performing the frequency dividing operation as a master will be described.

  In this case, as shown in FIG. 31, at the time tb, all the variable integer frequency dividers DIV0 to DIVN are all divided during the period when the output signals DO-DON of the variable integer frequency dividers DIV0 to DIVN are all at the H level. Set to P + 1. The path selection signal MXCNT3 continuously selects the output signal DOJ of the Jth variable integer frequency divider DIVJ. As a result, P + 1 frequency division can be executed while maintaining the phase relationship between the master and slave output signals.

  Next, with reference to FIG. 32, an operation when the P-th frequency division is performed next from the state where the J-th variable integer frequency divider DIVJ is performing the frequency division operation as a master will be described. In this case, this corresponds to the case where the coefficient A in the P + A / (N + 1) frequency division is 0. At time tc when all the sub-frequency-divided signals DO0-DON are at the H level, MOD (0 + J, A + 1) is generated by the path selection signal MXCNT3. That is, the output signal DOJ of the J-th variable integer frequency divider DIVJ is continuously selected. At this time, since the variable integer frequency divider DIVJ is a master and there is no variable integer frequency divider that performs a frequency dividing operation prior to the variable integer frequency divider DIVJ of this master, all the variable integer frequency dividers Set the frequency division number of DIV0-DIVN to P. As a result, a P-divided signal is generated as the final divided signal DO. Also, the phase relationship between the master and slave output signals is maintained.

  As described above, by providing N + 1 variable integer frequency dividers in parallel and enabling each variable integer frequency divider to perform P or P + 1 frequency division operations, fine accuracy in 1 / (N + 1) clock units. The fractional frequency can be set with.

  FIG. 33 schematically shows a structure of a portion for generating frequency division number control signals MXCNT3 and DVCNT40-DVCNT4N shown in FIG. 33, a frequency division control signal generation circuit 100 includes a switching timing generation circuit 102 that generates a frequency division number switching timing, a DO frequency division number setting circuit 104 that sets the frequency division number of the final frequency division signal DO, A frequency dividing sequence setting circuit 106 that sets a frequency dividing sequence according to the frequency dividing number set by the frequency dividing number setting circuit 104, a master register 108 that stores information indicating a master variable integer frequency divider, and frequency division number control A frequency division control signal generation circuit 110 for generating signals MXCNT3 and DVCNT40-DVCNT4N.

  When the switching enable signal ENC from the switching timing generating circuit 102 is activated, the frequency dividing control signal generating circuit 110 receives the final frequency dividing number instruction signal FDR from the frequency dividing sequence setting circuit 106 and the master stored in the master register register 108. Frequency division number control signals MXCNT3 and DVCNT40-DVCNT4N are generated in accordance with instruction data MM.

  Switching timing generation circuit 102 asserts switching enable signal ENC when output signals DO0-DON of variable integer frequency dividers DIV0-DIVN are all at the H level.

  The DO frequency division number setting circuit 104 stores information indicating the frequency division number required for the final frequency division signal DO. The frequency division number information stored in the DO frequency division number setting circuit 104 may be fixedly stored in advance in a ROM or the like, or may be appropriately set by a user according to an application or the like.

  The frequency division sequence setting circuit 106 includes, for example, a table memory that stores the final frequency division number and information indicating the sequence of each frequency division number in correspondence with each other. A numerical instruction signal FDR is generated. The frequency division sequence setting circuit 106 may be configured to update the final frequency division number instruction signal FDR when the final frequency division signal DO is at L level.

  The frequency division control signal generation circuit 110 generates the frequency division number instruction signal FDR and the master instruction signal data stored in the master register 108 when the switching enable signal ENC is asserted, that is, when the frequency division signals DO0 to DON are all at the H level. In accordance with MM, necessary operations are executed to set and output the states of frequency division number control signals MXCNT3 and DVCNT40-DVCNT4N.

  FIG. 34 is a flowchart showing the operation of the frequency division control signal generation circuit 110 shown in FIG. Hereinafter, the frequency division control signal generation operation of the frequency division number control signal generation unit shown in FIG. 33 will be described with reference to FIG.

  34, first, the master variable integer frequency divider is set to an initial state (MM = K) (step SP1), and then the frequency division number of the final frequency division signal DO is set to the frequency division number setting circuit 104. (Step SP2). Here, K is an integer that satisfies 0 ≦ K ≦ N.

  According to the set frequency division number of the final frequency division signal, the frequency division number indication signal FDR of the final frequency division signal is set to the initial value P + B / (N + 1) (step SP3). Here, B is an integer that satisfies 0 ≦ B ≦ N + 1.

  Next, a frequency division operation is started, and the initially set master and slave execute the frequency division operation according to the frequency division number (default value; for example, frequency division number P) determined by the frequency division number setting signal in the default state. (Step SP4). At this time, each of the variable integer frequency dividers DIV0 to DIVN starts a frequency dividing operation according to a given clock signal.

  When the frequency-dividing cycle starts and all the sub-frequency-divided signals DO0-DON are at the H level, the frequency-dividing signal generation circuit 110 receives the final frequency-dividing instruction signal FDR given from the frequency-division sequence setting circuit 106, and the current cycle The frequency division number of the final frequency division signal is identified (step SP5). When the final frequency division number instruction signal FDR designates the frequency division number P or P + 1 (when B = 0 or N + 1), the frequency division control signal generation circuit 110 maintains the initially set master, For variable integer frequency dividers DIV0 to DIVN, corresponding variable frequency division number setting signals DVCNT0 to DVCNTN are set to a state indicating frequency division number P + B / (N + 1). As a result, the frequency division number of the variable integer frequency divider is set to P or P + 1 (step SP6).

  On the other hand, when final frequency division number instruction signal FDR indicates a fractional frequency division number (when B is an integer from 1 to N), frequency division control signal generation circuit 110 executes the following operation. . That is, the number K of the variable integer frequency divider of the current master is set to the number of MOD (K + B, N + 1). Further, the frequency division number setting signal DVCNT of the variable integer frequency divider from number K to MOD (K + B, N + 1) -1 is set to a state in which the frequency division number P + 1 is designated, and the frequency division for the remaining variable integer frequency dividers is performed. The number setting signal DVCNT is set to a state for designating the frequency dividing number P (step SP7).

  When the frequency division number for the sub frequency division signal is designated and the switching enable signal ENC from the switching timing generation circuit 102 is asserted, the frequency division control signal generation circuit 110 receives the path selection signal MXCNT3 in the definite state and the frequency division signal. Number selection signals DVCNT0 to DVCNTN are output. Further, the master instruction data MM of the master register 108 is set to a value indicating the number MOD (K + B, N + 1) of the master variable integer frequency divider in the next frequency dividing cycle (step SP8). Thereby, in the current cycle, the frequency dividing operation designated by the final frequency dividing number instruction signal FDR is executed.

  It is determined whether or not a frequency division operation end instruction is given in step SP9. If this frequency division operation end instruction is not given, the process returns to step SP2 again to execute a series of frequency division operations. This frequency division end instruction is generated by, for example, power shutdown or operation mode end (for example, a transmission / reception stop instruction when used in a PLL frequency synthesizer such as a portable terminal. When the end of frequency division is instructed in step SP9) The frequency dividing operation ends.

  As described above, a plurality of variable integer frequency dividers each capable of dividing by two consecutive integers P and P + 1 are provided in parallel, and each dividing operation is divided by 1 / (N + 1) clock cycles. The operation is configured to be executed, and the frequency dividing operation can be performed with finer fractional accuracy.

[Example of change]
FIG. 35 schematically shows a structure of a modification of the variable fractional frequency dividing circuit according to the tenth embodiment of the present invention. The variable frequency dividing circuit shown in FIG. 35 differs from the configuration of the variable fractional frequency dividing circuit shown in FIG. 28 in the following points. That is, clock delay generation circuit 120 is provided for variable integer frequency dividers DIV0 to DIVN.

  Clock delay generation circuit 120 includes buffers 122a and 122b that receive differential clock signals CLK1 and CLK1B having a duty of 50%, delay circuits DLK1 to DLKN that delay output clock signals of buffer 122a by time ΔT, and buffers 122b, respectively. Delay circuits DLKB1-DLKBN for delaying the output clock signals by time ΔT are included. Here, the delay time ΔT is exactly ΔT = T / (N + 1).

  Clock signals from buffers 122a and 122b are applied to variable integer frequency divider DIV0 as clock signals CLK40 and CLK40B, respectively. Delay circuits DLK1, DLKB1,..., DLKJ, DLKBJ,..., DLKN, DLKBN are provided corresponding to variable integer frequency dividers DIV1,. From delay circuits DLK1 and DLKB1, differential clock signals CLK41 and CLK41B having a duty of 50% are generated and applied to variable integer frequency divider DIV1.

  From delay circuits DLKJ and DLKBJ, differential clock signals CLK4J and CLK4JB having a duty of 50% delayed by J · ΔT with respect to input clock signals CLK1 and CLK1B are generated and applied to variable integer frequency divider DIVJ. From delay circuits DLKN and DLKBN, differential clock signals CLK4N and CLK4NB having a duty of 50% delayed by N · ΔT with respect to input clock signals CLK1 and CLK1B are generated and applied to variable integer frequency divider DIVN.

  That is, assuming that i is an integer from 1 to N, differential clock signals CLKi and CLKBi with a duty of 50% having delay time i · ΔT with respect to input clock signals CLK1 and CLKB1 are generated from delay circuits DLKi and DLKBi, Is provided to the variable integer divider DIVi.

  The other configuration of the variable fractional frequency dividing circuit shown in FIG. 35 is the same as that of the variable fractional frequency dividing circuit shown in FIG. 28, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. .

  In the configuration shown in FIG. 35, only a pair of differential clock signals CLK1 and CLK1B are externally supplied as input clock signals, and clock signal CLK41 is externally supplied to each of variable integer frequency dividers DIV1-DIVN. Further, it is not necessary to generate and give CLK41B-CLK4N and CLKNB individually, and the wiring layout area can be reduced.

  Note that the variable fractional frequency dividing circuit according to the tenth embodiment of the present invention may also be used in combination with any of the configurations of the first to ninth embodiments.

  As described above, according to the tenth embodiment of the present invention, a plurality of frequency division operations can be performed with frequency division numbers P and P + 1 in accordance with a plurality of frequency division clock signals whose phases are shifted by ΔT (= T / (N + 1)). Variable integer frequency dividers are provided in parallel. Thereby, in addition to the effects of the first to ninth embodiments, a frequency-divided signal can be generated with finer fractional accuracy.

  By applying the present invention to a frequency dividing circuit that divides the frequency with fractional accuracy, it is possible to realize a frequency dividing circuit that accurately divides the high-speed input clock signal by the fractional frequency. In particular, when applied to a PLL frequency synthesizer or the like, a frequency-divided signal having a desired frequency-dividing ratio can be accurately generated even for a high-speed input clock signal.

  1A, 1B Variable integer frequency divider, 2 path switching circuit, 21A, 21B, 22, 23 Variable integer frequency divider, 25 Differential clock generation circuit, 26A, 26B Variable integer frequency divider, 30 frequency divider body, 31a , 31b Current source, 37A, 37B variable integer frequency divider, 38 path selection signal generation circuit, 70A, 70B variable integer frequency divider, DIV0-DIVN variable integer frequency divider, 82 path switching circuit, 120 clock delay generation circuit.

Claims (8)

N + 1 frequency dividers which are provided in parallel with each other and divide and output a clock signal applied according to a frequency division number setting signal by at least one of the continuous integers P and P + 1. The N + 1 frequency dividers are numbered sequentially from 0 to N, and the Jth frequency divider in the N + 1 frequency dividers is a clock provided to the 0th frequency divider. A clock signal having a phase difference of J / (N + 1) clock cycles is given to the signal, and N is an integer of 1 or more,
A frequency dividing circuit comprising a path switching circuit that selects any one of output signals of the N + 1 frequency dividers according to a path selection signal and outputs the selected signal as a final frequency division signal. The selection signal is MOD (A + J, N + 1) when changing from P division of the final division signal to P + A / (N + 1) division with the output signal of the Kth divider selected. The output signal of the second frequency divider is selected, and the frequency division number setting signal sets the frequency division number of the MOD (A + J, N + 1) th frequency divider to P, and the MOD (A + J, N + 1). The frequency division number is set to P + 1 for the frequency divider that starts the frequency division operation earlier than the first frequency divider, and the frequency division number is set to P for the remaining frequency dividers. Where A is an integer greater than or equal to 0 and less than or equal to N, and MOD (A + J, N + 1) represents a modulo N + 1 operation on A + J;
When the frequency division number of the final frequency division signal is changed to P + 1 division while the output signal of the J-th frequency divider is selected, all the frequency division numbers of the frequency divider are set to P + 1. The frequency dividing circuit according to claim 1, wherein the frequency division number selection signal is selected so that the path selection signal is continuously selected to select an output signal of the J-th frequency divider.   3. The frequency dividing circuit according to claim 1, wherein each of the frequency dividers includes means for reducing an operating current according to a frequency divided power save signal when the path selection signal designates another frequency divider. N is 1, and the N + 1 frequency dividers include first and second frequency dividers,
Each said divider is
Means for mutually transmitting signals indicating their frequency division states;
Set the frequency division number according to the frequency division state of the other party transmitted from the transmission means, the frequency division state of the other party, and the signal specifying the frequency division number of the final frequency division signal from the outside, and the set A frequency division number setting means for generating a frequency division number transmission signal indicating the frequency division number,
The frequency divider further comprises:
The path selection for the path switching circuit according to the frequency division number transmission signal provided in common to the first and second frequency dividers and transmitted from the frequency division number setting means of the first and second frequency dividers The frequency dividing circuit according to claim 1, further comprising a path selection signal generating circuit that generates a signal.   5. The frequency dividing circuit according to claim 1, wherein the clock signal is a single-ended 50% duty clock signal.   5. The circuit according to claim 1, further comprising a circuit that generates a differential clock signal having a duty of 50% from a clock signal having a duty of 50% given from outside of a single end to generate a clock signal for the N + 1 frequency dividers. Any one of the frequency divider circuits.   The clock delay generation circuit further includes a clock delay generation circuit for generating a clock signal for the N + 1 frequency dividers in accordance with an input clock signal given from the outside. A clock signal delayed by j / (N + 1) clock cycles with respect to the input clock signal is generated and provided to the j th frequency divider, where j is an integer from 0 to N. Item 5. The frequency dividing circuit according to any one of Items 1 to 4.   5. The frequency divider according to claim 1, wherein each of the frequency dividers resets a frequency dividing operation when a reset control signal indicates that a phase difference between output signals of the frequency divider is larger than a predetermined value. Divider circuit.

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