JP2005026721A - Resistor network and a/d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the accuracy of a resistance value of a resistance network which is used as an A/D converter for generating a reference voltage. <P>SOLUTION: In this resistance network, dummy blocks 10 and 11 are placed on both sides of the arrangement position of blocks B<SB>1</SB>to B<SB>N</SB>including normal resistance elements R<SB>1</SB>to R<SB>L</SB>. Both pitches between the dummy block 10 and the block B<SB>1</SB>, and between the dummy block 11 and the block B<SB>N</SB>are made equal to the mutual pitches between adjacent ones of the blocks B<SB>1</SB>to B<SB>N</SB>. For this purpose, the dummy blocks 10 and 11 are made to have the same outline as the other blocks B<SB>1</SB>to B<SB>N</SB>. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a reference voltage generation circuit that generates a reference voltage serving as a standard for analog / digital conversion (hereinafter referred to as A / D conversion) using a resistor network, and an A / D converter having the reference voltage generation circuit. In particular, an A / D having a resistor network for generating a plurality of reference voltages having a uniform potential difference with little error, a reference voltage generating circuit using the resistor network, and a reference voltage generating circuit using the resistor network The present invention relates to a converter (hereinafter referred to as ADC).

FIG. 14 shows an outline of the configuration of an ADC having a reference voltage generation circuit formed of a conventional resistor network. In FIG. 14, reference numeral 1 is a reference voltage generating circuit configured by using a resistor network and generates a reference voltage by dividing a reference voltage (V _rb , V _rt ) by resistance, and 2 is a reference voltage and input voltage of the reference voltage generating circuit 1. A comparator array 3 for determining the magnitude relationship with (V _in ) is a logic unit for converting the comparison result of the comparator array 2 into a digital code.

The resistor network is formed by connecting regular unit resistance elements in series between power supply terminals 4 and 5 to which reference voltages V _rb and V _rt are applied. An M-bit ADC requires 2 ^M regular unit resistance elements. Hereinafter, the unit resistance element is simply referred to as a resistance element. In a multi-bit ADC, when the value of M increases, the size of the resistor network is reduced. Therefore, as shown in FIG. 15, several to dozens of regular resistor elements R _{1 to} R _L are often arranged in one block. As a result, a resistance network is formed by N-folding back for each of these blocks B _{1 to} B _N. One block is composed of a regular series resistor configured by arranging a plurality of regular resistance elements R _{1 to} R _L on a straight line at equal intervals and connecting them in series. When A / D conversion is performed by comparing the upper digit and the lower digit by a plurality of comparisons, for example, when comparing the upper digit and the lower digit in two, between each block B _{1 to} B _N Are provided with taps 6 for comparison of the upper digits, and taps 7 are provided between the regular resistance elements R _{1 to} R _L for comparison of the lower digits.

In general, in a multi-bit ADC, the unit reference voltage (1LSB) generated in this type of resistor network is very small. For example, when the difference (V _rt −V _rb ) of the reference voltage applied to the reference voltage generation circuit of the 10-bit ADC is 1V, 1LSB is 1 / 1024V, that is, approximately 1 mV, which is a very small value. If the reference voltage is not generated accurately, the ADC cannot perform conversion with sufficient accuracy. That is, in order to improve the conversion accuracy, the accuracy of the resistance value of the regular resistance element constituting the reference voltage generation circuit 1 may be improved.

  Further, in a multi-bit ADC, the reference voltage has an S-shaped error due to the flow of charge at the time of comparison. FIG. 20 shows the state of an S-shaped error for a 10-bit precision ADC when the conversion speed is 20 MS / s, the resistance values of all regular resistance elements are 500 Ω, and the input capacitance of each voltage comparator is 4 pF. It is a graph to show. In FIG. 20, the vertical error represents the percentage error of the tap voltage, and the horizontal axis represents the position of the regular resistance element.

This S-shaped error is proportional to the resistance value of the entire normal resistance element. As means for reducing the S-shaped error, intermesh resistance elements IR _{1 to} IR _u having small resistance values are often inserted in parallel with the resistance network as shown in FIG. The intermesh resistive element IR ₁ includes a terminal opposite to the terminal to which the regular resistive element R ₂ is connected among the regular resistive elements R ₁ of the block B _{1 and} the regular resistive element R of the block B _2. resistance element R ₂ regular among the _first terminal is connected between the opposite terminals of the terminal that is connected. The intermesh resistive element IR ₂ includes a terminal opposite to the terminal to which the regular resistive element R ₂ is connected among the regular resistive elements R ₁ of the block B ₃ , and a block B _{4 not shown.} Among the terminals of the regular resistance element R _{1 and} the terminal opposite to the terminal to which the regular resistance element R ₂ is connected. Thus connected between the odd-numbered blocks and the even-numbered blocks normal resistive element R ₁ terminal, forming repeating such arrangement to block B _N-1 and the block B _N.

At this time, in order to make the voltage value coincide between the connection node of the intermesh resistance element and the connection node of the resistance network (between A and B, between A ′ and B ′, etc.), The ratio of the resistance value (including the resistance of the wiring between the regular resistance elements) and the resistance value of the intermesh resistance element (including the resistance of the wiring between the nodes) must be controlled to be constant. For example, if the ratio of resistance values between the nodes of the resistor network is 2: 1: 1:... 1: 1: 2, the ratio of resistance values between the nodes at both ends of each intermesh resistance element is also 2: 1: 1: ... must match 1: 2 Since it is designed by repeating the same pattern except between the nodes of the blocks B ₁ and B ₂ and between the nodes of the blocks B _N-1 and B _N , it is easy to match the ratio, but the design patterns are different at both ends. Therefore, since the regular resistance elements having the same pattern as those blocks do not exist outside the blocks B ₁ and B _N , it is difficult to match the ratio. For this reason, the voltage values do not match between the nodes A and B and the nodes A ′ and B ′, and the accuracy of the reference voltage is lowered.

A conventional reference voltage generation circuit using a resistance network uses a resistance network configured as shown in FIG. 15. Even if each regular resistance element is formed in the same shape, the difference in density of the arrangement of blocks is different. As a result, the regular resistance element finish is not uniform between the blocks B ₁ and B _N at both ends of the resistor network and the inner blocks B _{2 to} B _N-1 . The regular resistance elements of the coarse blocks B ₁ and B _N arranged so that the number of regular resistance elements per unit area is reduced, that is, the regular resistance elements of the block in which the other blocks exist only on one side, It is thicker than the regular resistance elements of the densely arranged blocks B _{2 to} B _N−1 , that is, the resistance elements of the blocks having other blocks on both sides thereof.

Therefore, the resistance value of each of the blocks B ₁ .about.B _N is the block B _1, B _N is larger than the block B ₂ ~B _N-1. When a reference voltage is generated using such a resistor network, a voltage rise is larger in the block B ₁ at one end of the resistor network than in the inner blocks B _{2 to} B _N-1 , and an inner voltage is generated in the block B _N at the other end. A voltage drop larger than that of the blocks B _{2 to} B _N-1 occurs. Originally, as indicated by the dotted line in FIG. 16, the resistance value increases in proportion to the increase in the number of resistors, and the reference voltage also increases in proportion to the increase in resistance value. However, since the resistance values of the blocks B ₁ and B _N are larger than those of the other blocks, they are bent as shown by the solid line in FIG. This reference voltage error has caused the integral nonlinearity (INL) of the ADC output as shown in FIG. However, FIG. 17 schematically shows INL, and does not show an error due to a quantization error or noise.

The same phenomenon is observed between the normal resistance elements R ₁ and R _L at both ends in each block and the internal normal resistance elements R _{2 to} R _L−1 . Also in this case, the resistance values of the regular resistance elements R ₁ and R _L at both ends of each block B _{1 to} B _N are larger than the inside regular resistance elements R _{2 to} R _L-1 , and the reference voltage and The relationship with the normal number of resistive elements is not proportional. Therefore, as shown in FIG. 18, the value of the reference voltage appearing at the terminal of each normal resistance element deviates from the ideal distribution. As shown in FIG. 19, this error causes INL when the output of the ADC is viewed in units of blocks. However, the INL shown in FIG. 19 is also schematically shown and does not show an error due to a quantization error or noise.

A reference voltage generating circuit using a resistor network with an intermesh resistor element uses a resistor network as shown in FIG. 21, and is generally a connection node between the block B ₁ and the intermesh resistor element IR _1. Between the connection node between the block B ₂ and the intermesh resistance element IR _1, and between the connection node between the block B _N-1 and the intermesh resistance element IR _u , the block B _N and the intermesh resistance element IR _u . The resistance value between the connection nodes (the combined resistance of the resistance network and the intermesh resistance element) is larger than the resistance value between the connection nodes between the inner blocks such as the blocks B _{3 to} B _{N-2 and} the intermesh resistance element. Become. The distribution of the reference voltage in this case is shown in FIG. In this case, since the combined resistance value is large between the nodes related to the blocks B ₁ and B ₂ and between the nodes related to the blocks B _N−1 and B _N , the reference voltage distribution is the power supply voltage V _rb. The distribution from the first power supply terminal 4 to the node A is larger than the ideal distribution, and from the node A ′ to the second power supply terminal 5 to which the power supply voltage _Vrt is applied is smaller than the ideal distribution. As a result, ADC, when converting a low voltage close to the power supply voltage V _rb, since the reference voltage is higher than the ideal value, outputs a code indicating the value smaller than the actual value of the input voltage V _in If you happen to occur. Such a malfunction is less likely to occur as the voltage approaches the intermediate voltage between the power supply voltages V _rb and V _rt . Furthermore, when converting a high voltage close to the power supply voltage V _rt, since the reference voltage is lower than the ideal value, when outputting code indicating the actual value greater than the value of the input voltage V _in is generated To do. FIG. 23 shows a conceptual diagram of INL corresponding to this case. However, quantization errors and noise errors are not shown.

  Since the present invention has been made to solve the above problems, the accuracy of the reference voltage output by the reference voltage generation circuit having the above resistor network, which is often used in a multi-bit A / D converter, is improved. The purpose is to increase. At the same time, another object is to reduce the integral nonlinearity of the output in the ADC.

  The resistor network according to the present invention is arranged on the semiconductor substrate with first and second power supply terminals provided on the semiconductor substrate and arranged in a straight line on the semiconductor substrate at approximately equal intervals, and the first and second power supply terminals. It has a plurality of regular resistance elements connected in series in the current path connecting the terminals and having almost the same shape. They have almost the same shape and are arranged at equal intervals and almost in parallel. A plurality of regular series resistors connected in series between the first and second power supply terminals and an annular formed on the semiconductor substrate so as to surround the plurality of regular series resistors. A dummy block, and the dummy blocks are arranged substantially in parallel with the regular series resistors and at both ends on both arrangement direction sides of the region where the plurality of regular series resistors are arranged in parallel. Regular series resistor On the other hand, the regular series resistors are arranged so as to have substantially the same interval as the regular series resistors. The regular resistor elements arranged at both ends of the linear array are arranged so as to have substantially the same interval as the regular resistor elements, and the plurality of regular series resistors are arranged in parallel. Both the arrangement direction sides of the region having a width equal to or larger than the normal resistance element width, and on both extension line direction sides of the linear arrangement of the normal resistance elements, the length of the normal resistance element or more. And is formed simultaneously with the same material as the series resistor.

  The A / D converter according to the present invention performs conversion from an analog signal to a digital signal by using a reference voltage generated by using the resistor network according to the present invention.

  According to the resistance network of the present invention, the annular dummy block formed on the semiconductor substrate so as to surround the whole of the plurality of regular series resistors is arranged in the region where the plurality of regular series resistors are arranged in parallel. On both sides of the arrangement direction, it is arranged so that it is substantially parallel to the regular series resistor and to have the same interval as the regular series resistor between the regular series resistors arranged at both ends, On both sides of the linear line of normal resistance elements, the distance between the normal resistance elements and the normal resistance elements arranged at both ends of the linear line of normal series resistors is almost the same. It is arranged so that it has the same interval, and on both sides of the arrangement direction side of the region where a plurality of regular series resistors are arranged in parallel, it has a width greater than the regular resistance element width and the regular resistance element linear shape On both sides of the extended line direction Since it has a width equal to or greater than the length of the regular resistance element and is formed simultaneously with the same material as the series resistor, the regular resistance element arranged at both ends of the plurality of regular resistance elements by the dummy block The same situation can be created as if the same shape of resistive elements were placed on both sides of each of the two, and the shape of each regular resistive element that makes up the resistor network was uniformly finished, so that accurate resistance division was possible. As a result, the reference voltage that can be generated in the resistor network approaches an ideal distribution, and the error that a normal resistance element near both ends of the series resistor has a higher resistance value than other resistance elements can be improved. There is an effect.

  In addition, according to the A / D converter of the present invention, since the reference voltage generated using the resistor network of the present invention is used, the integral nonlinearity when converting from an analog signal to a digital signal is improved. There is an effect that can be.

Embodiment 1 FIG.
Hereinafter, the resistance network according to the first embodiment of the present invention will be described. 1 is a plan view showing the structure of a resistor network according to Embodiment 1 of the present invention. In FIG. 1, 6 is a tap for outputting a reference voltage for A / D conversion of the upper digit, 7 is a tap for outputting a reference voltage for A / D conversion of the lower digit, and 8 is a regular resistor. Wirings 10 and 11 between the elements R _{1 to} R _L are dummy blocks provided on both sides of the arrangement region of the blocks B _{1 to} B _N. The resistor network including the blocks B _{1 to} B _N and the dummy block are formed on one semiconductor substrate. The regular series resistor included in the block B ₁ has one end connected to the first power supply terminal 4 and the other end connected to the other end of the regular series resistor of the adjacent block B ₂ . The regular series resistor included in the block B _N has one end connected to the second power supply terminal 5 and the other end connected to the other end of the regular series resistor of the adjacent block B _N-1. Yes. The regular series resistors included in each of the even-numbered blocks B _{2 to} B _N-2 are connected at one end to one end of the regular series resistors included in the right block, and the other end is connected to the left side. It is connected to the other end of the regular series resistor included in the block. Note that the positions of one end and the other end of the regular series resistor included in each of the blocks B _{1 to} B _N and the dummy series resistors of the dummy blocks 10 and 11 and the position of each resistance element are aligned in the vertical direction. Yes.

The dummy blocks 10 and 11 are composed of dummy series resistors in which dummy resistor elements formed at the same time in the same process so as to have the same shape as a regular resistor element are connected in series with a wiring 13 connecting between the dummy resistor elements 12. Is done. The dummy resistance element 12 includes a dummy series resistor and a block made of the dummy resistance element 12 in parallel with a straight line along which regular resistance elements R _{1 to} R _L constituting the other blocks B _{1 to} B _N are arranged. The regular resistor elements R _{1 to} R _{L of} B ₁ are arranged so that the distance from the regular series resistors formed of the regular resistor elements R _{1 to} R _L is the same as the distance a between the regular series resistors constituting each block. Further, the blocks B _{1 to} B _N , 10 and 11 are arranged so that the distance between the dummy resistance elements 12 is the same as the distance between adjacent normal resistance elements R _{1 to} R _L.

Thereby, all the blocks B _{1 to} B _N of the resistor network that generate the actual reference voltage are arranged with the same congestion degree. When the left and right directions are viewed from the respective blocks B _{1 to} B _N , the scenes are the same, that is, the same blocks B _{1 to} B _N or dummy blocks 10 and 11 are arranged on the left and right of any block B _{1 to} B _N. The Rukoto. More specifically, resistance elements having substantially the same shape are arranged on the left and right sides of the respective regular resistance elements R _{1 to} R _L , and substantially the same wiring 8 or left and right of the wiring 8 connecting the resistance elements R _{1 to} R _L. 13 is provided. Therefore, the shape of each regular resistance element constituting the resistor network is uniformly finished and accurate resistance division is performed, so that the reference voltage approaches an ideal distribution as shown in FIG. As a result, the error of the resistance value that has conventionally occurred near the both ends of the resistor network is improved.

In the first embodiment, the regular resistance elements R _{1 to} R _L are arranged at equal intervals, and the dummy resistance elements 12 are arranged at equal intervals according to the regular resistance elements R _{1 to} R _L. And the regular series resistors included in the blocks B _{1 to} B _N may be substantially the same in shape, and the regular resistor elements R _{1 to} R _L or dummy resistors constituting them may be used. The elements 12 do not have to be arranged at regular intervals. Here, the shape being almost the same means that some deformation due to an error in the process or the like is regarded as the same.

Embodiment 2. FIG.
Next, a resistance network according to the second embodiment of the present invention will be described. FIG. 3 is a plan view showing the configuration of a resistor network according to Embodiment 2 of the present invention. 3, 20 and 21 at both ends of the series resistor of each of the blocks B ₁ .about.B resistance element of _{regular N} constituting the R ₁ to R _L extension on a sequence of and each block B ₁ .about.B _N This is a dummy resistance element group including a plurality of dummy resistance elements 22 arranged on the outside, and the other parts having the same reference numerals as those in FIG. 1 correspond to the same reference numerals in FIG.

Each dummy resistance element 22, a resistance element R _1, R _L of the normal adjacent thereto, the same distance as the distance b with to and from the normal resistive element normal resistive element R ₁ to R _L respectively adjacent It is arranged to have.

Thereby, the regular resistance elements R _{1 to} R _L in each block are all arranged with the same degree of congestion. When the vertical direction is viewed from the regular resistance elements R _{1 to} R _L , the scenes are the same, that is, the regular resistance elements R _{1 to} R _{L or} the vertical resistance elements R _{1 to} R _L above and below all the regular resistance elements R _{1 to} R _L. The dummy resistance element 22 is arranged. Therefore, finish uniform shape of the resistance element R ₁ to R _L of each normal constituting the resistor network, for accurate resistance division is made, in each block B in ₁ .about.B _N as shown in FIG. 4 Each reference voltage approaches an ideal distribution. As a result, the error of the resistance value that has conventionally occurred in the vicinity of both ends of the normal series resistor, for example, the normal resistance elements R ₁ and R _L is improved.

  The first embodiment and the second embodiment can also be used in combination, and in that case, the uniformity of the resistance value between the blocks and between the regular resistance elements in the block can be improved at the same time.

  In the description of the resistor network according to the second embodiment, the case where the block interval is uniform has been described. However, even when the block interval is not uniform, the resistance value between the regular resistor elements is similar to the above embodiment. Uniformity can be improved.

Furthermore, as shown in FIG. 5, it can also be applied to those using intermesh resistance element IR ₁ ~IR _u. In this case, the dummy resistance element group 20 is arranged between the intermesh resistance elements IR _{1 to} IR _u and the regular resistance element R ₁ .

  At this time, as shown in FIG. 6, a regular resistance element that serves both as an intermesh resistance element and as a dummy resistance element may be provided. In FIG. 6, reference numeral 23 denotes an element that doubles as a dummy resistance element and an intermesh resistance element. These elements 23 are formed by dividing the intermesh resistance element and functioning as a dummy resistance. However, the resistance value of the element 23 is set low so as to function as an intermesh resistance element. With this configuration, the area occupied by the resistor network can be reduced.

Embodiment 3 FIG.
Next, a resistance network according to Embodiment 3 of the present invention will be described. FIG. 7 is a plan view showing the structure of a resistor network according to Embodiment 3 of the present invention. In FIG. 7, 10A and 10B are dummy blocks provided on both sides of the arrangement region of the blocks B _{1 to} B _N including the regular series resistors, and the other reference numerals are the same as those in FIG. It is a part corresponding to.

The dummy blocks 10A and 11A are formed of the same material as the resistance elements R _{1 to} R _L. For example, if the resistance elements R _{1 to} R _L are formed of polysilicon, the dummy blocks 10A and 11A are also formed of the same polysilicon. The dummy blocks 10A and 11A are formed simultaneously with the resistance elements R _{1 to} R _L.

The dummy blocks 10A and 11A are formed to have a width W2 that is equal to or greater than the width W1 of each of the resistance elements R _{1 to} R _L. Further, the dummy blocks 10A and 11A are formed to have a length L2 that is not less than the length L1 of the regular series resistor.

From this, the blocks B _{1 to} B _N of the resistor network that generate the actual reference voltage are all arranged with the same degree of congestion in a pseudo manner. When the left and right directions are viewed from the respective blocks B _{1 to} B _N , the scenes are substantially the same, that is, the same blocks B _{1 to} B _N or dummy blocks 13 are arranged on the left and right of any block B _{1 to} B _N. It will be. Therefore, the shape of each regular resistance element constituting the resistor network is uniformly finished and accurate resistance division is performed, so that the reference voltage approaches an ideal distribution as shown in FIG. As a result, the error of the resistance value that has conventionally occurred near the both ends of the resistor network is improved.

Embodiment 4 FIG.
Next, a resistance network according to Embodiment 4 of the present invention will be described. FIG. 8 is a plan view showing the structure of a resistor network according to Embodiment 4 of the present invention. In FIG. 8, 13 is an annular dummy block provided around the arrangement region of the blocks B _{1 to} B _N including the regular series resistors, and the other reference numerals are the same as those in FIG. It is a part corresponding to.

The dummy block 13 is formed of the same material as the resistance elements R _{1 to} R _L. For example, if the resistance elements R _{1 to} R _L are made of polysilicon, the dummy block 13 is also made of the same polysilicon. The dummy block 13 is formed simultaneously with the resistance elements R _{1 to} R _L.

Further, the dummy block 13 is formed on both sides of the arrangement area of the blocks B _{1 to} B _N so as to have a width W 3 that is greater than or equal to the width W _{1 of} each of the resistance elements R _{1 to} R _L.

From this, the blocks B _{1 to} B _N of the resistor network that generate the actual reference voltage are all arranged with the same degree of congestion in a pseudo manner. When the left and right directions are viewed from the respective blocks B _{1 to} B _N , the scenes are almost the same, that is, the same blocks B _{1 to} B _N or dummy blocks 10A and 11A are arranged on the left and right of any block B _{1 to} B _N Will be.

  Therefore, the shape of each regular resistance element constituting the resistor network is uniformly finished and accurate resistance division is performed, so that the reference voltage approaches an ideal distribution as shown in FIG. As a result, the error of the resistance value that has conventionally occurred near the both ends of the resistor network is improved.

Further, the dummy block 13, a resistance element R _1, R _L of the normal adjacent thereto, the same distance b to the interval b having between normal resistive element normal resistive element R ₁ to R _L respectively adjacent It is arranged to have. Then, the dummy block 13, in both the extension direction of the arrangement of the resistance elements R ₁ to R _L, having a resistance element R ₁ to R length L3 than the width W4 of _L.

As a result, the regular resistance elements R _{1 to} R _L in each block are all arranged with the same degree of congestion in a pseudo manner. When the vertical direction is viewed from the normal resistance elements R _{1 to} R _L , the scenes are almost the same, that is, the normal resistance elements R _{1 to} R _L above and below all the normal resistance elements R _{1 to} R _L. Or the dummy block 13 will be arrange | positioned. Therefore, finish uniform shape of the resistance element R ₁ to R _L of each normal constituting the resistor networks, since the exact resistance division is made, in each block B in ₁ .about.B _N as shown in FIG. 4 Each reference voltage approaches an ideal distribution. As a result, the error of the resistance value that has conventionally occurred in the vicinity of both ends of the normal series resistor, for example, the normal resistance elements R ₁ and R _L is improved.

  The dummy block 13 is grounded to the ground. The dummy block 13 mitigates the influence of noise generated on the resistance network other than the resistance network. As a result, when this resistor network is incorporated as the reference voltage generation circuit 1 in the A / D converter shown in FIG. 14, for example, the resistor network can generate an accurate reference voltage. Accuracy can be achieved.

Embodiment 5 FIG.
Next, a resistance network according to Embodiment 5 of the present invention will be described. FIG. 9 is a plan view showing the structure of a resistor network according to Embodiment 5 of the present invention. 9, the tap 6 for outputting a reference voltage for A / D conversion of high-order digits, the tap for outputting a reference voltage for performing low-order digits of the A / D converter 7, Sr ₁ ~Sr _k is A plurality of normal resistance elements F _{1 to} F _L arranged on one straight line and connected in series, and a plurality of normal resistance elements G _{1 to} G _L arranged on a straight line parallel to the straight line and connected in series The normal series resistors DS ₁ and DS ₂ in which a plurality of normal resistance elements F _{1 to} F _L and G _{1 to} G _L are connected in series in a U shape by connecting one end thereof A plurality of dummy resistance elements 30 ₁ to 30 _L arranged on one straight line and connected in series, and a plurality of dummy resistance elements 31 _{1 to} 31 _L arranged on a straight line parallel to the straight line and connected in series A plurality of dummy resistance elements 30 ₁ to 30 _L by connecting one end thereof. , 31 _{1 to} 31 _L connected in series in a U-shape, 32 is a dummy intermesh resistance element connected between the node n1 and the node n3, and 33 is between the node n2 and the node n4. connected dummy intermesh resistor element, IR ₁ ~IR _k is intermesh resistor connecting a serial resistor Sr ₁ to SR _k of the respective ends of the normal.

Serial resistor Sr ₁ and Sr _k regular is a serial resistor regular provided at the end of the serial resistor Sr ₁ to SR _k of the plurality of normal. Node n1, and who terminals not connected to the resistance element F ₂ adjacent normal of the terminal normal resistive element F ₁ of the series resistor Sr ₁ regular, dummy resistor element of the dummy serial resistor DS ₁ 31 is a connection node connected to a terminal of which is not connected to the dummy resistance device 31 ₂ of the _first terminal. Node n2 is the direction of the terminal that is not connected to the resistance element F ₂ adjacent normal among regular terminals resistive element F ₁ of the series resistor Sr _k regular, dummy resistor element of the dummy serial resistor DS ₂ 31 is a connection node connected to a terminal of which is not connected to the dummy resistance device 31 ₂ of the _first terminal. The node n3 is a connection node to which the first power supply terminal 4 ′, the dummy intermesh resistance element 32, and the dummy resistance element 30 ₁ of the dummy series resistor DS ₁ are connected. The node n4 is a connection node to which the second power supply terminal 5 ′, the dummy intermesh resistance element 33, and the dummy resistance element 31 ₁ of the dummy series resistor DS ₂ are connected.

The spacing between the resistance elements of adjacent normal serial resistor Sr ₁ to SR _k of legitimate, regular resistive elements arranged in a first straight line constituting the series resistor Sr ₁ to SR _k of the normal This is the same as the distance c between F _{1 to} F _L and the regular resistance elements G _{1 to} G _L arranged on the second straight line. Further, the distance between adjacent elements in each of the normal resistance elements F _{1 to} F _L, the distance between adjacent elements in the normal resistance elements G _{1 to} G _{L, and} the adjacent elements in the dummy resistance elements 30 ₁ to 30 _L. And the distance between adjacent elements in the dummy resistance elements 31 _{1 to} 31 _L are set to be the same. This setting for the on is for a serial resistor Sr ₁ to SR _k and dummy serial resistor DS _1, DS ₂ of the normal can be easily formed into the same shape, the series resistance of these legitimate sr ₁ to sR _k and if to form a dummy serial resistor DS _1, DS ₂ in substantially the same shape, regular resistive element _{F 1 ~F L, G 1 ~G} L and the dummy resistance device 30 ₁ to 30 _L , 31 _{1 to} 31 _L need not be arranged at equal intervals. However, the series resistor composed of the regular resistor elements F _{1 to} F _L and the series resistor body composed of the regular resistor elements G _{1 to} G _L are configured so as to have the same resistance value. It is formed in the same shape.

As shown in FIG. 9, dummy intermesh resistors 32 and 33 and dummy series resistors DS ₁ and DS ₂ are added outside the power supply terminals to which the power supply voltages V _rb and V _rt are applied. Then, the other end of the dummy intermesh resistance element 32 is connected to the first power supply terminal 4 ′ to which the pseudo reference voltage V _rb ′ (<V _rb ) that is the first power supply voltage is supplied. Further, the other end of the dummy intermesh resistor 33 is connected to the second power supply terminal 5 ′ to which the pseudo reference voltage V _rt ′ (> V _rt ) that is the second power supply voltage is supplied. Connecting terminals which is not connected to the dummy resistance device 30 ₂ of the dummy serial resistor dummy resistance device 30 _first terminal of the DS ₁ to the first power supply terminal 4 '.

At this time, the voltage values of the power supply voltages V _rb ′ and V _rt ′ are adjusted so that the nodes n1 and n2 to which the reference voltage is applied as the original power supply terminals of the resistor network become the reference voltages V _rb and V _rt. . Since the resistor networks connected between the nodes n1 and n2 all repeat the same pattern, it becomes easy to match the ratio of resistance values between the nodes. Therefore, for example, the potential difference between the nodes A and B and between the nodes A ′ and B ′ can be made smaller than before, the accuracy of the reference voltage generated by the resistor network can be increased, and the error of the reference voltage can be reduced.

Also in this case, as described in the second embodiment, on the extended line of the regular resistor elements F _{1 to} F _L as shown in FIG. 10 and the extended line of the regular resistor elements G _{1 to} G _L. A plurality of dummy resistance elements 40 arranged on the line may be arranged, and the same effect as in the second embodiment is obtained.

Further, as described in the second embodiment, a regular resistance element that combines the function of the intermesh resistance element and the function of the dummy resistance element as shown in FIG. 11 may be provided. In FIG. 11, reference numerals 45a and 45b denote elements that function as dummy resistance elements and intermesh resistance elements. These elements 45a, 45b divides the intermesh resistance element IR ₁ shown in FIG. 10 is obtained by a shape to act as a dummy resistor. However, the resistance values of the elements 45a and 45b are set to be low so as to function as intermesh resistors, and the two resistance elements 45a and 45b are set to function as one intermesh resistance element. With this configuration, the area occupied by the resistor network can be reduced.

In the reference voltage generation circuit shown in FIG. 9, the values of the power supply voltages V _rb ′ and V _rt ′, which are pseudo reference voltages, are adjusted while monitoring the voltage values of the nodes n1 and n2 that must be the reference voltage. There must be. The reference voltage generation circuit shown in FIG. 12 is improved so that the adjustment is not necessary. In FIG. 12, 50 is an operational amplifier having a non-inverting input terminal connected to the first power supply terminal 4, an inverting input terminal connected to the node n1, and an output terminal connected to the node n3, and 51 is connected to the second power supply terminal 5. 9 is an operational amplifier having a connected non-inverting input terminal, an inverting input terminal connected to the node n2, and an output terminal connected to the node n4, and other parts denoted by the same reference numerals as those in FIG. It is a part corresponding to the part.

Since the inverting input terminal and the non-inverting input terminal of the operational amplifiers 50 and 51 connected in this way are imaginary short, the node n1 is almost equal to the same voltage V _rb as the power supply terminal 4, and the node n2 is the power supply terminal. 5 is almost equal to the same voltage V _rt as 5. At this time, the voltage V _rb ′ is applied to the node n3 from the output terminal of the operational amplifier 50, and the voltage V _rt ′ is applied to the node n4 from the output terminal of the operational amplifier 51.

  Since the operational amplifiers 50 and 51 adjust the voltages output to the nodes n3 and n4, it is not necessary to adjust the voltages at the nodes n3 and n4 from the outside of the reference voltage generation circuit, which is compared with the reference voltage generation circuit shown in FIG. Handling becomes easier.

  Further, the reference voltage generation circuit shown in FIG. 13 has the same advantages as the reference voltage generation circuit shown in FIG. 12 with respect to the reference voltage generation circuit shown in FIG. In FIG. 13, 60 has an inverting input terminal connected to the first power supply terminal 4, a non-inverting input terminal connected to the node n1, and an output terminal for amplifying and outputting the potential difference between these input terminals. An operational amplifier 61 is an N-channel MOS transistor having a source connected to the third power supply terminal 64 for providing a ground potential, a drain connected to the node n3, and a gate connected to the output terminal of the operational amplifier 60, 62 An operational amplifier having an inverting input terminal connected to the power source terminal 5 of the second power source, a non-inverting input terminal connected to the node n2, and an output terminal for amplifying the potential difference between these input terminals, and 63 is a power source voltage Vdd. P having a source connected to the fourth power supply terminal 65, a gate connected to the output terminal of the operational amplifier 62, and a drain connected to the node n4 A Yaneru MOS transistor, the others Figure 9 the same reference numerals is a portion corresponding to the same code portion of Fig. By inserting the transistors 61 and 63 into the outputs of the operational amplifiers 60 and 62, the size of the operational amplifiers 60 and 62 can be reduced as compared with the operational amplifiers 50 and 51 shown in FIG. This is because the operational amplifiers 60 and 62 can control the voltages at the nodes n3 and n4 only by driving the transistors 61 and 63. The transistors 61 and 63 are preferably optimized in size so as to operate in the saturation region.

  In the reference voltage generation circuit shown in FIGS. 12 and 13, the dummy blocks 10 and 11 of the first embodiment can also be used. Further, the dummy resistance element groups 20 and 21 of the second embodiment can be used. Moreover, these can also be used in combination.

Embodiment 6 FIG.
Next, an ADC according to Embodiment 6 of the present invention will be described. Among the configurations of the conventional ADC shown in FIG. 14, the configuration of the resistor network shown in FIG. 1, FIG. 7, or FIG. In this case, INL in the upper digit conversion is improved.

  Further, in the configuration of the conventional ADC shown in FIG. 14, the configuration of the resistance network shown in FIG. 3, FIG. 5, FIG. 6, or FIG. In this case, INL in lower digit conversion is improved.

  Also, the reference voltage generation circuit described in any of FIGS. 9 to 13 can be used for the configuration of the resistor network 1 in the configuration of the conventional ADC shown in FIG. In this case, it is possible to eliminate the voltage value mismatch between the nodes A and B and between the nodes A ′ and B ′ generated by the intermesh resistance element.

It is a top view which shows the structure of the resistance network by Embodiment 1 of this invention. It is a graph which shows the relationship between the reference voltage which generate | occur | produces in the resistance network shown in FIG. 1, and the position of a resistive element. It is a top view which shows the structure of the resistance network by Embodiment 2 of this invention. It is a graph which shows the relationship between the reference voltage distribution in one block of the resistance network shown in FIG. 3, and the position of a resistive element. It is a top view which shows the structure of the resistance network by the 2nd aspect of Embodiment 2 of this invention. It is a top view which shows the structure of the resistance net | network by the 3rd aspect of Embodiment 2 of this invention. It is a top view which shows the structure of the resistance network by Embodiment 3 of this invention. It is a top view which shows the structure of the resistance network by Embodiment 4 of this invention. It is a top view which shows the structure of the reference voltage generation circuit by Embodiment 5 of this invention. It is a top view which shows the structure of the reference voltage generation circuit by the 2nd aspect of Embodiment 5 of this invention. It is a top view which shows the structure of the reference voltage generation circuit by the 3rd aspect of Embodiment 5 of this invention. It is a top view which shows the structure of the reference voltage generation circuit by the 4th aspect of Embodiment 5 of this invention. It is a top view which shows the structure of the reference voltage generation circuit by the 5th aspect of Embodiment 5 of this invention. It is a block diagram which shows the outline | summary of a structure of ADC which has a reference voltage generation circuit using a resistance network. It is a top view which shows the structure of the conventional resistance net | network. It is a graph which shows the relationship between the reference voltage which the resistance network shown in FIG. 15 generate | occur | produces, and the position of a resistive element. It is a graph which shows the integral nonlinearity of the output of ADC which applied the resistance network of FIG. It is a graph which shows the relationship between the reference voltage distribution in one block of the resistance network shown in FIG. 15, and the position of a resistive element. It is a graph which shows the integral nonlinearity in one block of ADC to which the resistance network of FIG. 15 is applied. It is a graph which shows the S-shaped error of the conventional resistance net | network. It is a top view which shows the structure of the reference voltage generation circuit using the conventional intermesh resistance element. 22 is a graph showing a relationship between a tap position of the reference voltage generation circuit shown in FIG. 21 and a reference voltage. FIG. 22 is a graph showing an integral nonlinearity of the output of the ADC using the reference voltage generation circuit shown in FIG. 21.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reference voltage generation circuit, 2 Comparator array, 3 Logic part, 4, 5 Power supply terminal, 6, 7 Tap, 8 wiring 10, 11, 10A, 11A, 13 Dummy block, 20, 21 Dummy resistance element group, Sr ₁ to SR _k serial resistor, DS _1, DS ₂ dummy serial _{resistor, R 1 ~R L, F 1} ~F L, G 1 ~G L normal resistance _{element, 30 1 ~30 L, 31 1} ~31 L , 40, 45a, 45b Dummy resistor element, 32, 33 Dummy intermesh resistor element, 50, 51, 60, 62 Operational amplifier.

Claims (2)

First and second power supply terminals provided on a semiconductor substrate;
On the semiconductor substrate, a plurality of regular lines arranged in a straight line and arranged at approximately equal intervals and connected in series in a current path connecting the first and second power supply terminals and having substantially the same shape. A plurality of regular series resistors having resistance elements, having substantially the same shape as each other, arranged at equal intervals and substantially in parallel with end portions, and connected in series between the first and second power supply terminals Body,
An annular dummy block formed on the semiconductor substrate so as to surround the whole of the plurality of regular series resistors,
The dummy block is
In both arrangement direction sides of the region where the plurality of regular series resistors are arranged in parallel, each of the regular series resistors is arranged in parallel with the regular series resistors and at both ends. Are arranged so as to have substantially the same interval as the interval between the series resistors, and on both sides of the linear arrangement of the regular resistor elements, the linear series of the regular series resistors are respectively provided. The regular resistance elements arranged at both ends of the array are arranged so as to have substantially the same spacing as the regular resistance elements.
On both sides of the region in which the plurality of regular series resistors are arranged in parallel, the width is equal to or larger than the width of the regular resistance elements, and both extended line directions of the linear arrangement of the regular resistance elements On the side, it has a width greater than the length of the regular resistance element,
A resistance network formed simultaneously with the same material as the series resistor. 2. An A / D converter, wherein a reference voltage generated using the resistor network according to claim 1 is used to perform conversion from an analog signal to a digital signal.

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