CN101908887B - DA (Digital Analogy) conversion device - Google Patents
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Abstract
The invention relates to a DA (Digital Analogy) conversion device. The DA conversion device is provided with a first resistor group (R*), a second resistor group (RH*), a first switch group (SW*) and a second switch group (SWH*), reference voltages are applied to two ends of the first resistor group (R*) and the second resistor group (RH*), the first switch group (SW*) outputs the voltage to the second resistor group (RH*) from the node (N*) in the first resistor group, wherein the voltage is determined according to the node selected by the binary digit of the first region of an input digital value, the second switch group (SWH*) outputs the voltage determined according to the node selected by the binary digit of the second region of the input digital value from the node (NH*) in the second resistor group, and the square resistance of the second resistor group is higher than that of the first resistor group. When any one of the node among resistors in the second resistor group is selected, at least two nodes in the first resistor group are selected; and when any one of the nodes at two ends in the second resistor group is selected, one node in the first resistor group is selected. Thereby, the conversion precision of the DA conversion device can be improved and the arrangement area can be reduced.
Description
Technical field
The present invention relates to resistance serial type DA (digital-to-analog) converting means in semiconductor integrated circuit.
Background technology
High-resolution DA converting means is widely used in integrated circuit (hereinafter referred to as IC).In control system, it is dull that the output characteristic of DA converting means requires.That is to say, the DNL of DA converting means (differential nonlinearity) requires in ± scope below 1LSB, and in other a lot of solutions, resistance string type is dull in essence.In addition, in the control of vehicle control or special industrial use, the environment temperature with the IC of DA converting means can reach 150 ℃～200 ℃, even under such limiting condition, resistance string also must guarantee linear.In addition, in IC design, from the viewpoint of cost, require the chip area of DA converting means will do smallerly.
As resistance serial type DA converting means, the DA converting means of the resistance string of position (MSB) use of the highest order that possesses supplied with digital signal and the resistance string of position (LSB) use of lowest order is disclosed in patent documentation 1.
Patent documentation 1: TOHKEMY 2001-244816 communique
Yet, while generating output valve by electric resistance partial pressure, in technology in the past, for realizing the high DA converting means of conversion precision, must increase the arrangement areas of chip power resistance.
Summary of the invention
Therefore, the object of the invention is to, provide a kind of can improve conversion precision, dwindle the DA converting means of arrangement areas.
In order to achieve the above object, relevant DA converting means of the present invention, possesses:
Resistance serializer circuit, it has the 2nd resistance group that the 1st resistance group that a plurality of resistors are connected in series and a plurality of resistor are connected in series, and at above-mentioned the 1st resistance group's two ends, applies reference voltage,
The 1st output unit, its voltage off-take point in above-mentioned the 1st resistance group, will give above-mentioned the 2nd resistance group according to determined the 1st Voltage-output of voltage off-take point of the binary digit selection in the 1st region of input digital code,
The 2nd output unit, its voltage off-take point in above-mentioned the 2nd resistance group, gives predetermined output point by determined the 2nd Voltage-output of voltage off-take point of selecting according to the binary digit in the 2nd region different from above-mentioned the 1st region,
Above-mentioned the 2nd resistance group's square resistance is higher than above-mentioned the 1st resistance group's square resistance,
While having selected any in the voltage off-take point between each resistor in above-mentioned the 2nd resistance group according to the binary digit in above-mentioned the 2nd region, according to the binary digit in above-mentioned the 1st region, select at least two voltage off-take points in above-mentioned the 1st resistance group,
While having selected any in the voltage off-take point at the two ends in above-mentioned the 2nd resistance group according to the binary digit in above-mentioned the 2nd region, according to the binary digit in above-mentioned the 1st region, select a voltage off-take point in above-mentioned the 1st resistance group.
In addition, in order to achieve the above object, relevant DA converting means of the present invention, possesses:
Resistance serializer circuit, it has the 2nd resistance group that the 1st resistance group that a plurality of resistors are connected in series and a plurality of resistor are connected in series, and at above-mentioned the 1st resistance group's two ends, applies reference voltage,
The 1st selected cell, its voltage off-take point in above-mentioned the 1st resistance group, the voltage off-take point that selection is corresponding with the binary digit in the 1st region of input digital code,
The 2nd selected cell, its voltage off-take point in above-mentioned the 2nd resistance group, selects the corresponding voltage off-take point of binary digit in 2nd region different from above-mentioned the 1st region,
The 1st output unit, it will give above-mentioned the 2nd resistance group according to the 1st definite Voltage-output of the voltage off-take point of above-mentioned the 1st selected cell selection,
The 2nd output unit, it will give predetermined output point according to the 2nd definite Voltage-output of the voltage off-take point of above-mentioned the 2nd selected cell selection,
Above-mentioned the 2nd resistance group's square resistance is higher than above-mentioned the 1st resistance group's square resistance,
While having selected any one in the voltage off-take point between each resistor in above-mentioned the 2nd resistance group according to the binary digit in above-mentioned the 2nd region, according to the binary digit in above-mentioned the 1st region, select at least two voltage off-take points in above-mentioned the 1st resistance group,
While having selected any one in the voltage off-take point at the two ends in above-mentioned the 2nd resistance group according to the binary digit in above-mentioned the 2nd region, according to the binary digit in above-mentioned the 1st region, select a voltage off-take point in above-mentioned the 1st resistance group.
Invention effect
According to the present invention, can improve the conversion precision of DA converting means, dwindle arrangement areas.
Accompanying drawing explanation
Fig. 1 is the block diagram as the resistance serial type DA converting means 100 of embodiments of the present invention.
Fig. 2 is the detailed circuit diagram of the resistance string DA circuit I 2 of DA converting means 100.
Fig. 3 has meaned the table of the binary digit of input digital code D (12:0) and the ON/OFF state relation of the 1st and the 2nd switch group.
Fig. 4 is for the well-balanced PN switching circuit of resistance string.
Fig. 5 has possessed output buffer and for the example of the rail-to-rail DA converting means of the RC filter of power supply noise change.
Symbol description in figure:
CA-capacitor
C-the 1st control signal
CH-the 2nd control signal
D-digital code
I1-decoder
I2-resistance string DA circuit
MN1-NMOS transistor
MP1-PMOS transistor
Node (voltage off-take point) in N0～N128-the 1st resistance group
Node (voltage off-take point) in NH0～NH64-the 2nd resistance group
OUT-output voltage (lead-out terminal)
RA-resistance
Resistor in R0～R127-the 1st resistance group
Resistor in RH0～RH63-the 2nd resistance group
The 1st grade of array of S1-
The 2nd grade of array of S2-
Switch in SW0～SW128-the 1st switch group
Switch in SWH0～SWH64-the 2nd switch group
VA, VB-end
VCC-supply voltage
VSS-ground
X2-buffer
Embodiment
Below, formation and the function thereof for the high resolution resistance serial type DA converting means of the execution mode as DA converting means of the present invention describes.High resolution resistance serial type DA converting means be the INL (integral nonlinearity) and the DNL (differential nonlinearity) that have been enhanced be the circuit of feature, be formed on IC chip.Concrete, DA converting means comprises the 1st resistance string corresponding with the position (MSB) of highest order, with the 2nd resistance string corresponding to position (LSB) of lowest order, a plurality of switches of connection the 2nd resistance string and the 1st resistance string, control the logical circuit of a plurality of switch ON/OFF.
The 1st resistance string consists of the low resistor of square resistance, and the 2nd resistance string is compared with the square resistance of the 1st electric resistance array, and the resistor high by square resistance forms.For obtaining good linearity, the unit resistance of the 2nd resistance string is compared than with the unit resistance ratio of the 1st resistance string, enough high.Also have, the arrangement areas of the 2nd resistance string on IC is less than the arrangement areas of the 1st resistance string on IC.
In addition, by a switch that makes to connect in a plurality of switches of the 1st resistance string and the 1st resistance string, be ON, switch continuously the method for MSB, can more improve DNL.
Also have, under the high temperature of 150～200 ℃, the magnitude of leakage current increase due to MOS switch, tends to make linearity seriously deteriorated.In order to solve such problem, by forming MOS switch with the size of balance than the PMOS transistor forming and nmos pass transistor for magnitude of leakage current.
Below, to being described in detail of the resistance serial type DA converting means of the execution mode as DA converting means of the present invention.Resistance serial type DA converting means, possesses decoder module and resistance string module as main formation.Decoder module is according to the digital code being transfused to, for generating the control signal of controlling for resistance string module.Resistance string module, has: the 1st resistance string (the 1st resistance group) that a plurality of resistors that are connected in series form, the 2nd resistance string (the 2nd resistance group) forming for the 1st switch group of the 1st resistance string, a plurality of resistors of being connected in series and for the 2nd switch group of the 2nd resistance string.
In the situation of the DA converting means of K (=N+M) position (N is that more than 2 integer, M is more than 2 integers), the 1st resistance string performance possesses the function of the MSB portion of 2N resistor, the 2nd resistance string, and performance possesses the function of the LSB portion of 2M resistor.
When the total of the resistance value of each resistor in the 1st resistance string is set as 50～500 Ω, if the total of the resistance value of each resistor in the 2nd resistance string is set as 10～50 times of total of the resistance value of each resistor in the 1st resistance string, can obtain good linearity.
Each resistor in the 1st resistance string, for example, consist of diffusion resistance or the such low square resistance of polysilicon resistance, each resistor in the 2nd resistance string, and the high square resistance such by the polysilicon resistance without Implantation forms.
By using and compare the resistor of the type that square resistance is high with the 1st resistance string in the 2nd resistance string, can compare with the converting means of DA in the past with equal accuracy, by less layout size, design this resistance serial type DA converting means.
The 1st and the 2 two resistance string, according to the switch of controlling from the signal of decoder module, be connected.On each node of the 1st resistance string, connect the individual switch of total (2N+1), on each node of the 2nd resistance string, connected the individual switch of total (2M+1).Each node is equivalent to be positioned at the voltage off-take point of each resistor ends.Decoder module, according to the input digital code for determining that the 1st which resistor of resistance string should connect with the 2nd resistance series winding, carries out decoding to the N position of high-order side.In addition, decoder module, according to the input digital code for determining that the 2nd which node of resistance string should be connected with the outlet side of DA converting means, carries out decoding to the M position of low level side.
Except the timing that the binary digit of the N position (MSB) of high-order side switches, according to the binary digit of input digital code, node in the 1st resistance string, select two adjacent nodes as the node connecing with the 2nd resistance series winding, the node in the 2nd resistance string, select a node as the node being connected with outlet side.
And in the timing of switching at the N position of high-order side (MSB) binary digit, the connection destination of the 2nd resistance string is switched on a high position of the 1st resistance string or the resistor of a low level.In this switching timing, not according to the binary digit of input digital code, node in the 1st resistance string, select two adjacent nodes as the node connecing with the 2nd resistance series winding, but a node in the node in the 1st resistance string is chosen as to the node connecing with the 2nd resistance series winding.That is to say, in two adjacent switches that are connected with two adjacent nodes in the 1st resistance string, only a switch is ON.For example, when the M position of low level side of input digital code is 0, in two adjacent switches that are connected with two adjacent nodes in the 1st resistance string, a switch is ON.
Like this, in the timing of switching at the N position of high-order side (MSB) binary digit, according to input digital code, by making in two adjacent switches an only switch, be ON (by selecting a node in the node in the 1st resistance string), with according to the digital code of this input, make the situation that two adjacent switches are ON compare (with selecting the situation of two adjacent nodes and comparing), can make DNL reduce by 50%.
The 1st switch group being formed by a plurality of switches that connect with the 1st resistance series winding, be a plurality of voltage off-take points in the 1st electric resistance array, determined the 1st Voltage-output of voltage off-take point of selecting given to the 1st output unit at the two ends of the 2nd resistance string according to the binary digit in the 1st region of the digital code of input.In addition, the 2nd switch group being formed by a plurality of switches that connect with the 2nd resistance series winding, be a plurality of voltage off-take points in the 2nd resistance string, determined the 2nd Voltage-output of voltage off-take point of selecting given to the 2nd output unit of predetermined output point according to the binary digit in the 2nd region different from the 1st region.
The 1st switch group, when the binary digit in the 2nd region is 0, using the determined voltage of voltage off-take point of selecting according to the binary digit in the 1st region as the 1st Voltage-output, when the binary digit in the 2nd region is the value beyond 0, using two determined voltages of voltage off-take point selecting according to the binary digit in the 1st region as the 1st Voltage-output.
The 1st switch group, from the voltage off-take point of the 1st resistance string, optionally switches the connection destination at the 2nd resistance string two ends.An end in two ends of the 2nd resistance string both sides, by putting in order of the resistor in the 1st resistance string, by the switch in the 1st switch group, be optionally connected with the odd number voltage off-take point in the 1st resistance string, another end puts in order by the resistor in the 1st resistance string, by the switch in the 1st switch group, is optionally connected with the even number voltage off-take point in the 1st resistance string.In addition, the 2nd switch group, from the voltage off-take point of the 2nd resistance string, optionally switches the connection destination of predetermined output point.
But in high temperature application, the leakage current of switch can make the linearity of DA converting means output decline significantly.Therefore, the mode with the leakage current coupling of each switch of cmos switch, designs this cmos switch evenly by height, makes it under the environment temperature of 150～200 ℃ of left and right, also can suppress linear remarkable decline.
Form the PMOS transistor of cmos switch and the size of nmos pass transistor, according to the magnitude of leakage current of inputting from supply voltage (VCC) to switch with from switch, be input to the mode that equates of the magnitude of leakage current of (VSS) determine.Therefore, can make the 1st or the impact of the impedance variation of the 2nd resistance string minimum.Its result offsets by magnitude of leakage current, has reduced the linear decline being caused by leakage current, compares with the formation that magnitude of leakage current is not offseted, and INL has been enhanced 5～10 times.
Below, the embodiment to resistance serial type DA converting means, describes with reference to accompanying drawing.
Fig. 1 is the block diagram of the resistance serial type DA converting means 100 of K (=N+M) position (N is that more than 2 integer, M is more than 2 integers).In order to make explanation simple, make K=13 (position) (MSB:N=7, LSB:M=6).
I1 makes to input the decoder that digital code D (12:0) is decoded into the 1st control signal C (128:0) and two control signals of the 2nd control signal CH (64:0).C (128:0) is for controlling the control signal of the ON/OFF of the 1st switch group connecing with the 1st resistance series winding, and CH (64:0) is for controlling the control signal of the ON/OFF of the 2nd switch group connecing with the 2nd resistance series winding.I2 is the resistance string DA circuit using the voltage of the ground voltage VSS of supply voltage VCC to the 2 reference voltages from the 1st reference voltage as output voltage range.OUT is the output voltage that inputs to rail-to-rail (rail torail) the operational amplifier lead-out terminal of the output point being connected with the input of rail-to-rail operational amplifier (or as).
Decoder I1, generates the control signal of controlling for resistance string DA circuit according to input digital code D (12:0).Resistance string DA circuit I 2, has: the 1st resistance string consisting of a plurality of resistors, the 1st switch group for the 1st resistance string, the 2nd resistance string consisting of a plurality of resistors and for the 2nd switch group of the 2nd resistance string.
Fig. 2 is the detailed circuit diagram of resistance string DA circuit I 2.Resistance string DA circuit I 2, is separated into two arrays.Identical with Fig. 1, for the simplification illustrating, establish N=7 and M=6.
The array S1 of the 1st grade, possesses 128 resistor R0～R127 that are connected in series as the 1st resistance group, possess the node N of one end and each resistor as the 1st switch group
*129 interrupteur SW 0～SW128 that connect.These resistors form the MSB of DA converting means 100.
The array S2 of the 2nd grade, possesses 64 resistor RH0～RH63 that are connected in series as the 2nd resistance group, possess the node NH of one end and each resistor as the 2nd switch group
*65 interrupteur SW H0～SWH64 that connect.
The object of DA converting means with the resistance string type of separation structure is, array S2 does not become the load of array S1.In order to reach such object, require the unit resistance of array S2 should be more much bigger than the unit resistance of array S1.
Total resistance value with respect to each resistor in the 1st resistance group is 50～500 Ω, and the total resistance value of each resistor in the 2nd resistance group is compared with the total resistance value of each resistor in the 1st resistance group, is 10～50 times.Therefore, can guarantee good linearity.
In addition, by using the resistor of the different type of square resistance, arrangement areas is fully dwindled.If the 1st resistance group's resistor is used to diffusion resistance or the polysilicon resistance of square resistance low (10～30 Ω/ (ohm/square)), the 2nd resistance group's resistor is used to the polysilicon square resistance of undoped square resistance high (300～2000 Ω/), use the situation of identical square resistance to compare with the 1st resistance group with the 2nd resistance group, can dwindle all shared arrangement areas of resistance group.
Interrupteur SW H0～SWH64, will according to the region, position of the high-order side with input digital code D (12:0) in abutting connection with and according to the M position (LSB) in the region, position of the low low level side in position than high-order side, the voltage that the node of selecting 65 node NH0～NH64 in the 2nd resistance group determines transfers to OUTPUT.
The function of decoder I1 shown in Fig. 1 performance the 1st selected cell: select the node corresponding with the binary digit in the region, position of the high-order side of the digital code D (12:0) of input the node N0～N128 in the 1st resistance group, also bring into play the function of the 2nd selected cell simultaneously: select the node corresponding with the binary digit in a region of the low level side of the digital code D (12:0) inputting the node NH0～NH64 in the 2nd resistance group.
Decoder I1, according to the binary digit in the region, position of the high-order side of the digital code D being transfused to (12:0), control the switching action of the 1st switch group, according to the binary digit in the region, position of the low level side of the digital code D being transfused to (12:0), control the switching action of the 2nd switch group.
The switching action of the 1st switch group is controlled by decoder I1, thus, an end in the end of the 2nd resistance group's both sides is connected on a node in the 1st resistance group, another end in the end of the 2nd resistance group's both sides, is connected on a node of a resistor and this node adjacency.In addition, the switching of the 2nd switch group action is controlled by decoder I1, and lead-out terminal OUT is connected with a node in the 2nd resistance group.
Fig. 3 has meaned the table of the binary digit of input digital code D (12:0) and the ON/OFF state relation of the 1st and the 2nd switch group.
When input digital code D (12:0) is 000H (when D (12:6)=00H and D (5:0)=00H), because a SW0 in 129 switches is ON, node N0 is connected to end VB (end VA is not connected with the arbitrary node in the 1st resistance group) thus.On the other hand, when input digital code D (12:0) is 000H, because a SWH0 in 65 switches is ON, the node NH0 being connected with end VB is thus connected to lead-out terminal OUT.
When input digital code D (12:0) becomes the value from 001H to 03FH (while comprising 1 in the binary digit of D (5:0)), because SW0 is ON, when node N0 is connected to end VB, because SW1 is ON, node N1 is connected to end VA (SW2～SW128 is all OFF).On the other hand, when input digital code D (12:0) is while becoming the value from 001H to 03FH, along with the increase of the value of the D (5:0) in the region, position of low level side, SWH1～SWH63 becomes ON one by one by ascending order.Because any in SWH1～SWH63 is ON, any of node NH1～NH63 is connected to lead-out terminal OUT.
When input digital code D (12:0) is 040H (when D (12:6)=01H and D (5:0)=00H), because a SW1 in 129 switches is ON, node N1 is connected to end VA (end VB is not connected with the arbitrary node in the 1st resistance group).On the other hand, when input digital code D (12:0) is 040H, because a SWH64 in 65 switches is ON, the node NH64 being connected with end VA is connected to lead-out terminal OUT.
When input digital code D (12:0) becomes the value from 041H to 07FH (while comprising 1 in the binary digit of D (5:0)), because SW1 is ON, node N1 is connected to end VA, because SW2 is ON, node N2 is connected to end VB (SW0, SW3～SW128 are all OFF) thus simultaneously.On the other hand, when input digital code D (12:0) is while becoming the value from 041H to 07FH, along with the increase of the value of the D (5:0) in the region, position of low level side, SWH63～SWH1 becomes ON one by one by descending.Because any in SWH63～SWH1 is ON, any in node NH63～NH1 is connected to lead-out terminal OUT thus.
When input digital code D (12:0) is 080H (when D (12:6)=02H and D (5:0)=00H), because a SW2 in 129 switches is ON, node N2 is connected to end VB (end VA is not connected with the arbitrary node in the 1st resistance group) thus.On the other hand, when input digital code D (12:0) is 080H, because a SWH0 in 65 switches is ON, the node NH0 being connected with end VB is connected to lead-out terminal OUT.
The flow process later to Fig. 3, identical with above-mentioned explanation, the description thereof will be omitted.
Like this, in the timing of switching at the binary digit of the N position of high-order side (MSB), not making adjacent two switches in the 1st switch group is ON, and only making a switch is ON.Therefore the DNL in the time of, can making MSB change reduces by 50%.
That is to say, when selecting any in the node NH1～NH63 between each resistor in the 2nd resistance group according to the binary digit in the region, position of low level side, according to the binary digit in the region, position of high-order side, select two nodes in the 1st resistance group; On the other hand, during any in the node NH0, the NH64 that select the two ends in the 2nd resistance group according to the binary digit in the region, position of low level side, according to the binary digit in the region, position of high-order side, select a node in the 1st resistance group.
For example, when input digital code D (12:0) is 040H, not making two switches of SW1 and SW2 is ON, and only making SW1 is ON, and making SW2 is OFF.Now, if make SW1 and SW2, be ON simultaneously, by the path of SW2, NH0, NH64, SW1, current direction the 2nd resistance group.Therefore,, even if SWH64 is ON, the impact of the lower voltage causing due to current direction the 2nd resistance group, can not make the voltage of node N1 correctly pass to lead-out terminal OUT.Yet, owing to only making SW1, be that ON, SW2 are OFF, the lower voltage causing so there is not current direction the 2nd resistance group, so by the ON of SWH64, can make the voltage of node N1 correctly pass to lead-out terminal OUT.
Equally, when input digital code D (12:0) is 080H, not making two switches of SW2 and SW3 is ON, and only making SW2 is ON, and making SW3 is OFF.Now, if SW2 and SW3 are ON simultaneously, by the path of SW3, NH64, NH0, SW2, current direction the 2nd resistance group.Therefore,, even if SWH0 is ON, the impact of the lower voltage causing due to current direction the 2nd resistance group, can not make the voltage of node N2 correctly pass to lead-out terminal OUT.Yet, owing to only having SW2, be that ON, SW3 are OFF, thus the lower voltage that current direction the 2nd resistance group causes be there is not, so by the ON of SWH0, can make the voltage of node N2 correctly pass to lead-out terminal OUT.
Therefore, in the above-described embodiment, due to the improvement of DNL or INL, improved DA conversion precision, and the 2nd resistance group and the 1st resistance faciation ratio, square resistance is high, can dwindle arrangement areas thus.
Also have, about DA converting means of the present invention, be not defined as the purposes of rail-to-rail (rail to rail).With respect to supply voltage, can at random set output voltage range.In addition, also can use the reference voltage that does not rely on supply voltage.
Fig. 4 is the switching circuit being used in SW0～SW128 and SWH0～SWH64.The cmos switch that uses PMOS transistor MP1 and nmos pass transistor MN1 to form.Certainly, in common application (such as the application of only being used at normal temperatures, non-rail-to-rail application etc.), for the active component of switch, even the only transistorized switch formation of PMOS or only the switch formation of nmos pass transistor also can fully be tackled.
While using, by the use of cmos switch, can carry out the compensation of balance leakage current in the application of high temperature.When vehicle-mounted purposes or specific industrial use, exist the environment temperature of DA converting means to reach the situation of 150～200 ℃ of high temperature.Under these circumstances, due to the substrate leakage stream of a great deal of occurring, in the above-mentioned the 1st and the 2nd resistance group's etc. array resistors, flow through leakage current, the linearity of DA conversion is by deteriorated.That is to say, due to the generation of leakage current, each magnitude of voltage being generated by array resistors changes, and it is large that the error of the output valve of DA converting means becomes.
Therefore, for PMOS transistor and nmos pass transistor, use leakage current to be compensated PMOS transistor and the nmos pass transistor of such size or ratio.The leakage current of PMOS transistor MP1 flows to drain electrode (the sub-SWI of switch input terminal) from substrate (VCC), and the leakage current of nmos pass transistor MN1 flows to substrate (VSS) from drain electrode (the sub-SWI of switch input terminal).According to the suitable ratio of PMOS transistor and nmos pass transistor, can make the magnitude of leakage current that flows into resistance string minimize.
Fig. 5 is the embodiment that is attached with the rail-to-rail DA converting means of the buffer that has suppressed power supply noise.Resistance R A is inserted between the 1st resistance group of supply voltage VCC and resistance R 0～R127.Resistance R A makes supply voltage VCC be depressured to supply voltage VIN, and supply voltage VIN is the power supply of resistance string DA circuit I 2.Even if make supply voltage VIN be depressured to half of supply voltage VCC, because the gain A of rail-to-rail buffer X2 is set as 2, so rail-to-rail (rail to rail) characteristic of the DA converting means shown in Fig. 5 is also maintained.By append capacitor CA between resistance R A and the power input part of resistance string DA circuit I 2, form RC filter.By RC filter, can suppress the change of supply voltage VCC.
Above, preferred embodiments of the present invention have been disclosed for illustrative, the present invention is not defined as the above embodiments, interiorly can append various distortion and displacement to above-described embodiment not departing from the scope of the present invention.
For example, between the 1st resistance group and the 2nd resistance group, possess amplifier, this amplifier amplifies for the voltage that the 1st resistance all living creatures is become, and gives the 2nd resistance group by the Voltage-output after amplification.
In addition, owing to not making two the adjacent switches in the 1st switch group, be ON, only making a switch is ON, the timing of switching as the binary digit of the N position (MSB) of high-order side, in the above-described embodiment, exemplified with the situation of " D (5:0)=00H ".Yet, according to the corresponding relation (Fig. 3) between the binary digit of D (12:0) and the ON/OFF state of the 1st and the 2nd switch group, also can be by making the ON/OFF state of the 1st and the 2nd switch group be offset to the upside of row, at " during D (5:0)=FFH ", only making a switch is ON.
Claims (5)
1. a DA converting means, possesses:
Decoder module, it,, according to input digital code, generates the control signal of controlling for resistance string;
Resistance serializer circuit, when described DA converting means is K=M+N position, described resistance serializer circuit has the 1st resistance group and 2N the 2nd resistance group that resistor is connected in series that 2M resistor is connected in series, two ends described the 1st resistance group apply reference voltage, wherein M is more than 2 integer, N is more than 2 integer
The 1st output unit, its voltage off-take point in described the 1st resistance group, will give described the 2nd resistance group according to determined the 1st Voltage-output of voltage off-take point of the binary digit selection in the 1st region of input digital code,
The 2nd output unit, its voltage off-take point in described the 2nd resistance group, gives predetermined output point by determined the 2nd Voltage-output of voltage off-take point of selecting according to the binary digit in the 2nd region different from described the 1st region,
This DA converting means is characterised in that,
Described the 2nd resistance group's square resistance is higher than described the 1st resistance group's square resistance,
While having selected any in the voltage off-take point between each resistor in described the 2nd resistance group according to the binary digit in described the 2nd region, according to the binary digit in described the 1st region, select at least two voltage off-take points in described the 1st resistance group,
While having selected any in the voltage off-take point at the two ends in described the 2nd resistance group according to the binary digit in described the 2nd region, according to the binary digit in described the 1st region, only select a voltage off-take point in described the 1st resistance group,
The switching of the switch forming according to the leakage current by between substrate and drain electrode equates mutually and the flow direction of described leakage current is contrary nmos pass transistor and PMOS transistor, selects voltage off-take point,
The transistorized described leakage current of described PMOS is from described flow of substrates to described drain electrode, and the described leakage current of described nmos pass transistor flows to described substrate from described drain electrode.
2. DA converting means according to claim 1, is characterized in that,
During according to any in the voltage off-take point comprising in the binary digit in described the 2nd region between 1 each resistor of selecting in described the 2nd resistance group, according to the binary digit in described the 1st region, select at least two voltage off-take points in described the 1st resistance group
According in the binary digit in described the 2nd region, do not comprise 1 select in the voltage off-take point at the two ends in described the 2nd resistance group any time, according to the binary digit in described the 1st region, select a voltage off-take point in described the 1st resistance group.
3. DA converting means according to claim 1 and 2, is characterized in that,
While selecting any in the voltage off-take point between each resistor in described the 2nd resistance group according to the binary digit in described the 2nd region, according to the binary digit in described the 1st region, by the putting in order of the resistor in described the 1st resistance group, select odd number voltage off-take point and even number voltage off-take point in described the 1st resistance group.
4. DA converting means according to claim 1 and 2, is characterized in that,
Described the 1st voltage, exports as the voltage that is applied in described the 2nd resistance group's two ends.
5. a DA converting means, possesses:
Resistance serializer circuit, when described DA converting means is K=M+N position, described resistance serializer circuit has the 1st resistance group and 2M the 2nd resistance group that resistor is connected in series that 2N resistor is connected in series, two ends described the 1st resistance group apply reference voltage, wherein, M is more than 2 integer, and N is more than 2 integer
The 1st selected cell, its voltage off-take point in described the 1st resistance group, the voltage off-take point that selection is corresponding with the binary digit in the 1st region of input digital code,
The 2nd selected cell, its voltage off-take point in described the 2nd resistance group, selects the corresponding voltage off-take point of binary digit in 2nd region different from described the 1st region,
The 1st output unit, it will give described the 2nd resistance group according to the 1st definite Voltage-output of the voltage off-take point of described the 1st selected cell selection,
The 2nd output unit, it will give predetermined output point according to the 2nd definite Voltage-output of the voltage off-take point of described the 2nd selected cell selection,
This DA converting means is characterised in that,
Described the 2nd resistance group's square resistance is higher than described the 1st resistance group's square resistance,
While having selected any one in the voltage off-take point between each resistor in described the 2nd resistance group according to the binary digit in described the 2nd region, according to the binary digit in described the 1st region, select at least two voltage off-take points in described the 1st resistance group,
While having selected any one in the voltage off-take point at the two ends in described the 2nd resistance group according to the binary digit in described the 2nd region, according to the binary digit in described the 1st region, only select a voltage off-take point in described the 1st resistance group,
The decoder that generates the control signal of controlling for described the 1st resistance string and described the 2nd resistance string according to the digital code that is transfused to is selected described voltage off-take point.
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| CN200910145740.3A CN101908887B (en) | 2009-06-05 | 2009-06-05 | DA (Digital Analogy) conversion device |
| JP2010063508A JP5477093B2 (en) | 2009-06-05 | 2010-03-19 | DA converter |
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| CN200910145740.3A CN101908887B (en) | 2009-06-05 | 2009-06-05 | DA (Digital Analogy) conversion device |
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| CN101908887B true CN101908887B (en) | 2014-04-30 |
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| JP6196794B2 (en) * | 2013-03-29 | 2017-09-13 | ローム株式会社 | D / A converter |
| CN105188204B (en) * | 2015-08-26 | 2017-09-01 | 中国科学院上海高等研究院 | D/A converting circuit and method for AMOLED column drive circuits |
| CN107025882A (en) * | 2016-01-29 | 2017-08-08 | 上海和辉光电有限公司 | The circuit and method of a kind of diminution source driving area |
| CN108023594B (en) * | 2016-11-04 | 2020-08-04 | 无锡华润上华科技有限公司 | Control system of resistance segmented digital-to-analog converter |
| CN109921794B (en) * | 2019-03-06 | 2021-07-23 | 东北大学 | Asynchronous over-level sampling analog-to-digital converter with variable hysteresis |
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| US5969657A (en) * | 1997-07-22 | 1999-10-19 | Analog Devices, Inc. | Digital to analog converter |
| US5952948A (en) * | 1997-09-24 | 1999-09-14 | Townsend And Townsend And Crew Llp | Low power liquid-crystal display driver |
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| CN1192612A (en) * | 1997-03-04 | 1998-09-09 | 合泰半导体股份有限公司 | Digital/analgue converter |
| CN101056106A (en) * | 2006-04-12 | 2007-10-17 | 曹先国 | Digital-analog converter |
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| JP5477093B2 (en) | 2014-04-23 |
| JP2010283803A (en) | 2010-12-16 |
| CN101908887A (en) | 2010-12-08 |
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