WO2018123201A1

WO2018123201A1 - Differential-output d/a converter and a/d converter

Info

Publication number: WO2018123201A1
Application number: PCT/JP2017/036636
Authority: WO
Inventors: 悠藤本; 智裕根塚; 牧原　哲哉; 森永　剛
Original assignee: 株式会社デンソー
Priority date: 2016-12-28
Filing date: 2017-10-10
Publication date: 2018-07-05
Also published as: JP2018107771A

Abstract

A differential-output D/A converter according to the present disclosure is provided with: decoders (2p, 2n) for converting inputted data into thermometer code; a positive-side capacitor array (3p, 3Ap, 3Bp, 3Cp) comprising a plurality of unit capacitors (Cp) having one end connected to a positive-side output terminal, and a switch (SWp) for switching the other end of the unit capacitors so as to connect to a positive-side reference voltage or a negative-side reference voltage in accordance with the thermometer code; and a negative-side capacitor array (3n, 3An, 3Bn, 3Cn) comprising a plurality of unit capacitors (Cn) having one end connected to a negative-side output terminal, and a switch (SWn) for switching the other end of the unit capacitors so as to connect to the positive-side reference voltage or the negative-side reference voltage in accordance with the thermometer code. The positive-side and negative-side capacitor arrays are disposed in an discretionary first direction. The unit capacitors constituting each of the arrays are arranged in a second direction orthogonal to the first direction. The unit capacitors corresponding to the thermometer code in the positive-side and negative-side capacitor arrays are disposed so as to be point-symmetrical with respect to the center of the arrays as the symmetry point.

Description

Differential output type D / A converter and A / D converter

Cross-reference of related applications

This application is based on Japanese Application No. 2016-255670 filed on Dec. 28, 2016, the contents of which are incorporated herein by reference.

The present disclosure relates to a differential output type D / A converter including a capacitor array and an A / D converter using the D / A converter.

For D / A converters and A / D converters that use the principle of charge redistribution in capacitor arrays, if these capacitors are arranged, for example, in a straight line on a semiconductor substrate, the influence of the in-plane film thickness gradient is further reduced. It becomes easy to receive. Then, since the nonlinearity error and the differential nonlinearity error are deteriorated, it becomes a problem how to form a large number of capacitors on the semiconductor substrate. In view of this, various layout methods have been proposed in the past, for example, as shown in

Patent Documents

1 and 2.

JP 2002-100991 A Japanese Patent No. 3844392

According to the conventionally proposed layout method, even if an in-plane gradient exists on the substrate, an effect of reducing the influence to some extent can be obtained. However, in the configuration of Patent Literature 1, the arrangement corresponding to the odd-numbered capacitors of the thermometer code is not targeted and is affected by variations. Further, the configuration of Patent Document 2 has a problem that the wiring between the capacitors and the switches connected to them becomes complicated, and the area occupied by the capacitor array and the parasitic capacitance increase.

The present disclosure provides a differential output type D / A converter that can reduce the influence of an in-plane gradient existing on a semiconductor substrate without increasing the area of the capacitor array and without complicating the wiring, and the D / A An object of the present invention is to provide an A / D converter using the A converter.

According to one aspect of the present disclosure, the decoder includes a decoder that converts input data into a thermometer code, and a positive and negative capacitor array having a plurality of unit capacitors corresponding to the thermometer code. Then, the positive capacitor array and the negative capacitor array are arranged in an arbitrary first direction, and the unit capacitors constituting each array are arranged in a second direction orthogonal to the first direction. Further, the unit capacitors corresponding to the thermometer code in the positive and negative capacitor arrays are arranged so as to be symmetric with respect to each other with the center of the array as a symmetric point.

Thus, by adopting the differential output configuration, the variation in the capacitance gradient in the direction in which the unit capacitors are arranged and arranged is canceled by the positive and negative capacitor arrays. Therefore, the integral nonlinearity error of the D / A converter can be reduced without increasing the arrangement area of the capacitor array and without complicating the wiring.

Also, according to one aspect of the present disclosure, in the positive-side and negative-side capacitor arrays, at least part of the unit capacitors corresponding to the same thermometer code are arranged at positions facing each other. As for the other unit capacitors, similarly to the first aspect, the unit capacitors corresponding to the thermometer code are arranged so as to be point-symmetric with respect to the center of the array of the other unit capacitors.

With this configuration, when a hybrid type or a 2-stage / weighted type D / A converter is constituted by a plurality of D / A converters, a layout of wiring for connecting the plurality of D / A converters. At least a part of the unit capacitor can be arranged so that the area becomes as small as possible.

The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is a diagram schematically showing a layout of each unit capacitor in a capacitor array constituting a D / A converter in the first embodiment. FIG. 2 is a diagram showing a capacitor array constituting the D / A converter, FIG. 3 is a functional block diagram showing the overall configuration of the D / A converter, FIG. 4 is a diagram schematically showing the layout of each unit capacitor in the capacitor array constituting the D / A converter in the second embodiment. FIG. 5 is a diagram schematically showing the layout of each unit capacitor in the capacitor array constituting the D / A converter in the third embodiment. FIG. 6 is a diagram schematically showing the layout of each unit capacitor in the capacitor array constituting the D / A converter in the fourth embodiment. FIG. 7 is a diagram schematically showing the layout of each unit capacitor in the capacitor array constituting the D / A converter in the fifth embodiment. FIG. 8 is a diagram schematically showing the layout of each unit capacitor in the capacitor array constituting the D / A converter in the sixth embodiment. FIG. 9 is a diagram schematically showing the layout of each unit capacitor in the capacitor array constituting the D / A converter in the seventh embodiment. FIG. 10 is a diagram illustrating a configuration of an A / D converter in the eighth embodiment. FIG. 11 is a diagram illustrating a configuration of an A / D converter in the ninth embodiment. FIG. 12 is a diagram showing a configuration of a resistance array type D / A converter, FIG. 13 is a diagram (No. 1) showing the configuration of another resistor array type D / A converter as a modification, FIG. 14 is a diagram (No. 2) showing the configuration of another resistor array type D / A converter as a modification, FIG. 15 is a diagram illustrating a configuration of an A / D converter in the tenth embodiment.

(First embodiment)
As shown in FIG. 3, the D / A converter 1 of the present embodiment is a differential output type, and the number of bits is, for example, “5”. The input 5-bit binary code is converted into a thermometer code of “32” by the positive and

negative thermometer decoders

2p and 2n, respectively. The converted positive and negative thermometer codes are input to the positive and

negative capacitor arrays

3p and 3n. The negative thermometer code is the positive inversion.

As shown in FIG. 2, the positive side and negative

side capacitor arrays

3p and 3n include 32 unit capacitors Cp1 to Cp32 and Cn1 to Cn32. The numbers given to each unit capacitor correspond to the thermometer code. One end of each of the unit capacitors Cp1 to Cp32 is connected to the DACp output terminal, and the other end is connected to one of the reference voltages REFp and REFn via the changeover switches SWp1 to SWp32. Similarly, one end of each of the unit capacitors Cn1 to Cn32 is connected to the DACn output terminal, and the other end is connected to one of the reference voltages REFp and REFn via the changeover switches SWn1 to SWn32.

The feature of this embodiment is the layout of the unit capacitors in the positive side and negative

side capacitor arrays

3p and 3n, as shown in FIG. The unit capacitors Cp1 to Cp32 of the positive capacitor array 3p are arranged in the order in which the value of the thermometer code changes from small to large along the X direction shown in the figure. On the other hand, the negative side capacitor array 3n is located in the −Y direction in the figure of the positive side capacitor array 3p, and the unit capacitor Cn1 to Cn32 has a thermometer code value along the X direction shown in the figure. They are arranged in the order of changing from large to small, that is, in the reverse order of the capacitor array 3p on the positive side. In the first column, the unit capacitors Cp1, Cn32 face each other in the Y direction, and in the 32nd column, the unit capacitors Cp32, Cn1 face each other in the Y direction. The Y direction corresponds to the first direction, and the X direction corresponds to the second direction.

In this case, the space between the 16th column and the 17th column is the center of the array indicated by “x” in the figure. With the center as the symmetry point, the unit capacitors Cp1 to Cp32 and the unit capacitors Cn1 to Cn32 are arranged in a positional relationship that is point-symmetric with each other. By adopting such an arrangement form, the slope of the capacitance variation in the X direction is canceled, and the integral nonlinearity error is reduced.

As described above, according to the present embodiment, the

decoders

2p and 2n that convert input data into thermometer codes, and positive and negative capacitor arrays 3p having a plurality of unit capacitors corresponding to each thermometer code, 3n. Then, the positive capacitor array 3p and the negative capacitor array 3n are arranged in the Y direction, and the unit capacitors constituting each array 3 are arranged along the X direction.

Furthermore, the unit capacitors Cp and Cn corresponding to each thermometer code in the positive and

negative capacitor arrays

3p and 3n are arranged so as to be symmetrical with respect to each other with the center of the array 3 as a symmetric point. Specifically, the unit capacitors Cp and Cn constituting the positive side and negative

side capacitor arrays

3p and 3n are arranged in the order corresponding to the thermometer code.

In this way, with the D / A converter 1 as a differential output configuration, the variation in the capacitance gradient in the X direction in which the unit capacitors Cp and Cn are arranged side by side is canceled by the positive and

negative capacitor arrays

3p and 3n. . Therefore, the integral nonlinearity error of the D / A converter 1 can be reduced without increasing the arrangement area of the capacitor array 3 and without complicating the wiring.

(Second Embodiment)
Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different parts will be described. In the second embodiment, as shown in FIG. 4, in the positive capacitor array 3Ap, the unit capacitor Cp1, the 32nd column unit capacitor Cp2, the second column unit capacitor Cp3, the 31st column in the first column in the X direction. The unit capacitors Cp4 and the like are arranged so that the value of the thermometer code sequentially increases from the outside to the center of the array 3Ap. The unit capacitor Cp31 is located in the 16th column, and the unit capacitor Cp32 is located in the 17th column.

On the other hand, in the negative side capacitor array 3An, each thermometer code includes a unit capacitor Cn1, a unit capacitor Cn2, a unit capacitor Cn2, a unit capacitor Cn3, a unit capacitor Cn4, and a second column. Corresponding unit capacitors are arranged in the reverse order of the capacitor array 3Ap on the positive side. The unit capacitor Cn32 is located in the 16th column, and the unit capacitor Cn31 is located in the 17th column.

In other words, in the positive side capacitor array 3Ap, unit capacitors corresponding to odd-numbered thermometer codes are arranged from the first column to the sixteenth column, and correspond to the thermometer code of the even number from the 32nd column to the 17th column. Unit capacitors are arranged. In the negative capacitor array 3An, the relationship between the odd number and the even number is reversed. The unit capacitors Cp1 to Cp32 and the unit capacitors Cn1 to Cn32 are arranged in a positional relationship that is point-symmetric with respect to the center of the arrays 3Ap and 3An as in the first embodiment. .

Also in the case of the second embodiment configured as described above, since the slope of the capacitance variation in the X direction is canceled between the positive capacitor array 3Ap and the negative capacitor array 3An, the integral nonlinearity error is reduced. .

(Third embodiment)
In the third embodiment, as shown in FIG. 5, each of the positive side capacitor array 3Bp and the negative side capacitor array 3Bn has unit capacitors Cp1 to Cp32 and Cn1 to Cn32 of the array 3 as opposed to the second embodiment. Arrangement is started from the center side, and the arrangement is sequentially performed toward both end sides of the array 3.

That is, in the positive side capacitor array 3Bp, the unit capacitor Cp1 in the 16th column, the unit capacitor Cp2 in the 17th column, the unit capacitor Cp4 in the 15th column, the unit capacitor Cp4 in the 18th column, etc. The thermometer code values are arranged so as to increase sequentially from the outside toward the outside. The unit capacitor Cp31 is located in the first column, and the unit capacitor Cp32 is located in the 32nd column.

On the other hand, in the negative side capacitor array 3Bn, each thermometer code has a unit capacitor Cn1, a unit capacitor Cn2, a unit capacitor Cn2, a unit capacitor Cn3 in the 18th column, a unit capacitor Cn4 in the 15th column, etc. Corresponding unit capacitors are arranged in the reverse order of the positive capacitor array 3Bp. The unit capacitor Cn32 is located in the first column, and the unit capacitor Cn31 is located in the 32nd column.
In the case of the third embodiment configured as described above, the same effects as those of the second embodiment can be obtained.

(Fourth embodiment)
In the fourth embodiment, as shown in FIG. 6, each of the positive capacitor array 3Cp and the negative capacitor array 3Cn is arranged in 2 rows and 16 columns. Unit capacitors Cp1, Cp3,..., Cp31 corresponding to odd-numbered thermometer codes are arranged in the first row: 1st to 16th columns of the positive side capacitor array 3Cp. In the second row: from the first column to the 16th column, unit capacitors Cp2, Cp4,..., Cp32 corresponding to the divisor thermometer code are arranged.

On the other hand, for the negative side capacitor array 3Cn, the row directly opposite to the first row of the positive side capacitor array 3Cp is defined as the first row. In the first row: 1st to 16th columns, unit capacitors Cn31, Cn29,..., Cn1 corresponding to odd thermometer codes are arranged. In the second row: the 1st to 16th columns, unit capacitors Cn32, Cn30,..., Cn2 corresponding to the divisor thermometer codes are arranged. That is, these are in reverse order to the corresponding row arrangement of the positive capacitor array 3pC.

In the above arrangement, the center between the eighth column and the ninth column is the center of the array 3, but the unit capacitors Cp1 to Cp32 and the unit capacitors Cn1 to Cn32 are also point symmetric with respect to the center. Are arranged in a positional relationship.

As described above, according to the fourth embodiment, the unit capacitors Cp1 to Cp32 and Cn1 to Cn32 constituting the positive side and negative side capacitor arrays 3Cp and 3Cn are respectively arranged in two columns along the Y direction. With this configuration, when the number of elements is increased in order to improve the resolution of the D / A conversion, the arrangement length in the X direction is suppressed from increasing, and the degree of freedom of the layout plan including other circuits is increased. be able to.

(Fifth embodiment)
In the fifth embodiment, as shown in FIG. 7, the unit capacitor Cp32 of the positive side capacitor array 3Dp and the unit capacitor Cn32 of the negative side capacitor array 3Dn corresponding to the thermometer code 32 are Y at the left end of the array. Opposite along the direction. The remaining unit capacitors Cp1 to Cp31 and unit capacitors Cn1 to Cn31 are arranged in reverse order to each other as in the first embodiment.

In this case, the center of the array of the unit capacitors Cp1 to Cp31 and Cn1 to Cn31 is Cp16 and Cn16 located in the 17th column, and they naturally face each other along the Y direction. Accordingly, the unit capacitors Cp1 to Cp31 and the unit capacitors Cn1 to Cn31 are also arranged in a positional relationship that is point-symmetric with respect to each other with the center of the array 3 as the symmetry point.

As described above, according to the fifth embodiment, in the positive and negative capacitor arrays 3Dp and 3Dn, the unit capacitors Cp32 and Cn32 corresponding to the same thermometer code “32” are arranged at positions facing each other. The unit capacitors Cp1 to Cp31 and Cn1 to Cn31 are arranged in the same manner as in the first embodiment.

With this configuration, when a hybrid type or a 2-stage / weighted type D / A converter is configured by a plurality of D / A converters, the layout area of the wiring connecting them is minimized. It becomes possible.

(Sixth embodiment)
In the sixth embodiment shown in FIG. 8, in the configuration of the second embodiment, the unit capacitors Cp32 of the positive capacitor array 3Ap and the unit capacitors Cn32 of the negative capacitor array 3An are extracted, and as in the fifth embodiment, Are arranged in the first column as positive and negative capacitor arrays 3A′p and 3A′n, respectively.

In this case, Cn31 located in the 17th column, which is the center of the array of unit capacitors Cp1 to Cp31, and Cn31 located in the 17th column of the array of unit capacitors Cn1 to Cn31 face each other along the Y direction. become. Accordingly, the unit capacitors Cp1 to Cp31 and the unit capacitors Cn1 to Cn31 are also arranged in a positional relationship that is point-symmetric with respect to each other with the center of the array 3 as the symmetry point. In the case of the sixth embodiment configured as described above, the same effect as that of the fifth embodiment can be obtained.

(Seventh embodiment)
In the seventh embodiment shown in FIG. 9, in the configuration of the third embodiment, the unit capacitor Cp31 in the first column of the positive capacitor array 3Bp and the unit capacitor Cp32 in the 32nd column are replaced with the positive capacitor. The array 3B'p is used. In this case, as in the fifth embodiment, the unit capacitor Cp32 and the unit capacitor Cn32 face each other in the Y direction, and the unit capacitor Cp1 and the unit capacitor Cn1 in the 17th column face each other in the same manner. In the case of the seventh embodiment configured as described above, the same effect as that of the fifth embodiment can be obtained.

(Eighth embodiment)
In the eighth embodiment shown in FIG. 10, the successive approximation type 5-bit A / D converter 11 is configured by using the same D / A converter 1A as in the first embodiment. The decoder 2 is not shown. Further, since the positive side and negative side capacitor arrays 3Ep and 3En supply the input voltages VINP and VINN of the A / D converter 11, the changeover switches SWp1 to SWp32 and SWn1 in the switches of the

capacitor arrays

3p and 3n of the first embodiment are used. SWn32 is replaced with a three-input selector switch.

The output terminal TOPp of the positive side capacitor array 3Ep is connected to the non-inverting input terminal of the comparator 12, and the output terminal TOPn of the negative side capacitor array 3nE is connected to the inverting input terminal. A series circuit of switches SWsp and SWsn is connected between the non-inverting input terminal and the inverting input terminal. A common voltage Vcm is applied to a common connection point of the switches SWsp and SWsn.

The output terminal of the comparator 12 is connected to the input terminal of the successive approximation register 13. The output terminal of the successive approximation register 13 is connected to the input terminal of the control circuit 14. The control circuit 14 controls switching of the changeover switches SWp1 to SWp32 and SWn1 to SWn32 in the positive side and negative side capacitor arrays 3Ep and 3En according to the register value input from the successive approximation register 13. Finally, the register value stored in the successive approximation register 13 becomes A / D conversion data.
As described above, according to the eighth embodiment, since the successive approximation type A / D converter 11 is configured using the D / A converter 1A, the A / D conversion accuracy can be improved.

(Ninth embodiment)
As shown in FIG. 11, the ninth embodiment forms an A / D converter 21 as in the eighth embodiment. The A / D converter 21 is the same D / A converter as in the eighth embodiment. It is a hybrid type in which a resistance array type D / A converter 22 is combined with 1B. Since the D / A converter 1B is used for the conversion of the upper 5 bits and the D / A converter 22 is used for the conversion of the lower 7 bits, the A / D converter 21 has a 12-bit configuration.

The positive-side and negative-side capacitor arrays 3Fp and 3Fn constituting the D / A converter 1B are obtained by deleting the change-over switches SWp32 and SWn32 of the positive-side and negative-side capacitor arrays 3Ep and 3En in the sixth embodiment. Instead, output terminals Bp32 and Bn32 of the D /

A converters

22p and 22n are connected to one ends of the unit capacitors Cp32 and Cn32, respectively.

As shown in FIG. 12, the D / A converter 22p is formed of, for example, a segment type, and includes a plurality of unit resistors Ru and 8-bit changeover switches SWrp1 to SWrp8. Between the output terminal Bp32 and the reference voltages REFp and REFn, a series circuit of two unit resistors Ru and a changeover switch SWrp is connected in 8 parallels corresponding to 8 bits. The 8th to 6th bits, which are the upper 3 bits, are configured as an unary-weighted type including only the two unit resistors Ru. The remaining lower 5 bits, the 5th to 1st bits, are configured as an R-2R type in which the upper end on the adjacent upper bit side is connected by the unit resistor Ru in addition to the two unit resistors Ru. The A series circuit of two unit resistors Ru is connected between the upper end of the series circuit corresponding to the first bit and the reference voltage REFn.

As described above, according to the ninth embodiment, the A / D converter 21 is converted into the capacitor array type D / A converter 1B used for the conversion of the higher-order bits corresponding to the input signal and the lower-order bits. A resistor array type D / A converter 22 to be used is provided. Then, the output terminals Bp32 and Bn32 of the D /

A converters

22p and 22n are connected to the unit capacitors Cp32 and Cn32 of the capacitor arrays 3Fp and 3Fn included in the D / A converter 1B so as to be configured in a hybrid type.

That is, when the A / D converter is configured using only the capacitor array type D / A converter 1, the area for configuring the capacitor array increases exponentially as the resolution increases. On the other hand, as in the seventh embodiment, the lower-order bit conversion is performed by the resistor array type D / A converter 22, thereby suppressing an increase in area. Even in the case of such a hybrid type, the wiring capacitance on the D / A converter 22 side and the parasitic capacitance of the wiring connecting the D / A converter 22 and the D / A converter 1B are linear. Since there is no influence, the restrictions on the layout on the D / A converter 1B side do not become severe.

As a modification of the ninth embodiment, the D / A converter 22p may use a string type shown in FIG. 13 or an R-2R type shown in FIG. 14 in addition to the segment type. However, the string type has an advantage that the current variation depending on the code is small, but the number of unit resistors Ru and the changeover switch SWr increases, and the arrangement area increases. In addition, since the output resistance increases, there is a demerit that time is required for settling. On the other hand, the R-2R type has a small arrangement area, but the current variation depending on the code increases.
On the other hand, by making the D / A converter 22 a segment type, it is possible to suppress the current fluctuation depending on the code and to reduce the arrangement area.

(10th Embodiment)
In the tenth embodiment shown in FIG. 15, the D / A converter 1A of the eighth embodiment and the D / A converter 1B of the ninth embodiment are combined to provide a 2-stage weighted A / D converter 31. The unit capacitor Cp1 of the D / A converter 1A and the unit capacitor Cp32 of the D / A converter 1B are connected. Note that “_2” is assigned to the component of the D / A converter 1A, and “_1” is assigned to the component of the D / A converter 1B.

The A / D converter 31 has a 10-bit configuration by converting the upper 5 bits by the D / A converter 1B and converting the lower 5 bits by the D / A converter 1A. The conversion process is performed by the successive approximation register 32 and the control circuit 33.

As described above, according to the tenth embodiment, the 2-stage / weighted A / D converter 31 is configured by combining the D / A converter 1A and the D / A converter 1B. With this configuration, the degree of freedom in laying out the unit capacitors Cp32 and Cn32 is improved, so that the wiring can be shortened to reduce the parasitic capacitance, and the A / D conversion accuracy can be increased.

(Other embodiments)
The layout of each unit capacitor is not limited to that shown in each embodiment, and the unit capacitors corresponding to the thermometer code in the positive and negative capacitor arrays are symmetrical with respect to each other with the center of the array as the symmetry point. Should be arranged as follows.
When at least a part of the unit capacitors corresponding to the same thermometer code are arranged at positions facing each other, the other unit capacitors are arranged in units of other unit capacitors corresponding to the thermometer code. It is sufficient to arrange them so as to be symmetrical with respect to each other with the center of the center of symmetry.

What is necessary is just to change suitably the number of conversion bits of a D / A converter and an A / D converter according to each design.
The A / D converters of the ninth and tenth embodiments may be configured using the D / A converters of the second to seventh embodiments.
Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims

A decoder (2p, 2n) for converting input data into a thermometer code;
A plurality of unit capacitors (Cp) whose one ends are connected to the positive output terminal, and the other ends of the unit capacitors are connected to either the positive reference voltage or the negative reference voltage according to the thermometer cord. A positive capacitor array (3p, 3Ap, 3Bp, 3Cp) composed of switches (SWp) to be switched;
A plurality of unit capacitors (Cn), one end of which is connected to the negative output terminal, and the other end of the unit capacitor are connected to either the positive reference voltage or the negative reference voltage according to the thermometer cord. A negative capacitor array (3n, 3An, 3Bn, 3Cn) comprising switches (SWn) for switching
The positive-side capacitor array and the negative-side capacitor array are arranged in an arbitrary first direction, and unit capacitors constituting each array are arranged in a second direction orthogonal to the first direction,
A differential output type D / A converter in which unit capacitors corresponding to the thermometer code in the positive and negative capacitor arrays are arranged so as to be point-symmetric with respect to the center of the array.
2. The differential output type D / A converter according to claim 1, wherein the unit capacitors constituting the positive side and negative side capacitor arrays (3p, 3n) are arranged in the corresponding order of the thermometer code. .
The unit capacitors constituting the positive-side and negative-side capacitor arrays (3Ap, 3An) are alternately arranged from one end side to the other end side of the array in the corresponding order of the thermometer code, and sequentially to the center side. The differential output type D / A converter according to claim 1, wherein the differential output type D / A converter is disposed so as to face toward the center.
After each unit capacitor constituting the positive side and negative side capacitor arrays (3Bp, 3Bn) starts to be arranged from the center side of the array in the order corresponding to the thermometer code, one direction side, the other direction 2. The differential output type D / A converter according to claim 1, wherein the differential output type D / A converters are arranged alternately toward the side and sequentially toward the outside.
5. The differential output according to claim 1, wherein the unit capacitors constituting the positive-side and negative-side capacitor arrays (3 Cp, 3 Cn) are respectively arranged in two rows in the first direction. Type D / A converter.
A decoder (2) for converting input data into a thermometer code;
A plurality of unit capacitors, one end of which is connected to the positive output terminal, and a switch for switching the other end of the unit capacitor to be connected to either the positive reference voltage or the negative reference voltage according to the thermometer cord ( SWp) positive side capacitor array (3A'p, 3Dp, 3Ep),
A plurality of unit capacitors, one end of which is connected to the negative output terminal, and the other end of the unit capacitor are switched so as to be connected to either the positive reference voltage or the negative reference voltage according to the thermometer code. A negative capacitor array (3A'n, 3Dn, 3En) comprising switches (SWn),
The positive-side capacitor array and the negative-side capacitor array are arranged in an arbitrary direction, and unit capacitors constituting each array are arranged in a direction orthogonal to the direction,
In the positive-side and negative-side capacitor arrays, at least a part of unit capacitors corresponding to the same thermometer code are arranged at positions facing each other,
The other unit capacitor is a differential output type D / A in which unit capacitors corresponding to the thermometer code are arranged symmetrically with respect to each other about the center of the array of the other unit capacitors. converter.
The differential output type D / A converter according to claim 6, wherein the other unit capacitors are arranged in a corresponding order of the thermometer codes.
7. The differential output type D / D according to claim 6, wherein the other unit capacitors are arranged in an inverted positional relationship so as to alternate from one end side to the other end side of the array and sequentially toward the center side. A converter.
7. The differential output type according to claim 6, wherein the other unit capacitors are arranged so as to start outward from the center side of the array, and then alternately toward the one direction side and the other direction side and sequentially toward the outside. D / A converter.
An A / D converter comprising the differential output type D / A converter according to any one of claims 1 to 9.
The D / A converter is provided as a capacitor array type D / A converter (1B) used for conversion of upper bits corresponding to an input signal,
A resistor array type D / A converter (22) used for conversion of the lower bit,
The output terminal of the resistor array type D / A converter is connected to the positive side or negative side output terminal via one of unit capacitors of a capacitor array included in the capacitor array type D / A converter. Item 11. The A / D converter according to Item 10.
The A / D converter according to claim 11, wherein the resistance array type D / A converter is a segment type.
The D / A converter includes an upper D / A converter (1B) used for conversion of upper bits corresponding to an input signal, and a lower D / A converter used for conversion of lower bits corresponding to an input signal. As an A converter (1A),
11. The output terminal of the lower D / A converter is connected to the positive or negative output terminal via one of unit capacitors of a capacitor array included in the upper D / A converter. A / D converter of description.