JP2004533728A5

JP2004533728A5 -

Info

Publication number: JP2004533728A5
Application number: JP2003509521A
Authority: JP
Filing date: 2002-06-25
Publication date: 2008-01-10

Claims

A field effect transistor, in particular a MIS field effect transistor,
a) a ridge of the at least one web types that are disposed on the semiconductor substrate, and the uplift of roux Ebutaipu that having a top surface contact and the side surface,
b) a first gate oxide layer that will be placed on the electromotive of the upper surface Takashi of the web type,
c) a first gate electrode disposed over the first gate oxide layer, a first gate electrodes that have a top surface and side surfaces,
d) and said web type second gate oxide over a portion of the side surface Ru at least the arrangement of uplift of the side surfaces of the portion and the first gate electrode layer,
e) the second gate oxide layer, and a second gate electrodes that will be placed on the upper surface of the gate electrodes of the Contact and first,
f) and a said source and drain regions are disposed on the web-type raised, the field effect transistor.

The second gate oxide layer, said than on a web type of Takashi the side of the electromotive force, on the side of the first gate electrodes are thicker manufacture, according to claim 1 Field effect transistor.

Insulating space Sa is said at the level of the first gate electrodes are disposed on the second gate oxide layer, the field-effect transistor according to claim 1 or 2.

A field effect transistor, in particular a MIS field effect transistor,
a) a ridge of the at least one web types that are disposed on the semiconductor substrate, and the uplift of roux Ebutaipu that having a top surface contact and the side surface,
b) the said web type Takashi and least over a portion of the force of the side surface is also Ru is placed first gate oxide layer,
c) a first gate electrodes disposed on the first gate oxide layer, a first gate electrodes that have a top surface and side,
d) and said web type caused the upper surface Takashi, Contact and second gate oxide layer that will be positioned on the upper surface of the first gate electrodes,
e) a second gate electrodes that will be disposed a gate oxide layer of the second, and on the side surface of the first gate electrodes,
f) said is placed on the web-type raised and a Luso over source region and a drain region, a field effect transistor.

Wherein the raised web type further comprises an edge that is rounded between said side surface of ridge of the upper surface and said web type of raised of said web type, according to any one of claims 1 to 4 Field effect transistor.

Radius of curvature of the edge, the first gate oxide Souma other is proportional to the thickness of the second gate oxide layer, the field-effect transistor according to claim 5.

Between the gate electrode and the source region, further wherein are disposed spacers between the drain region and the gate electrode, the field-effect transistor according to any one of claims 1-6.

The first gate electrodes has a polysilicon layer, the field-effect transistor according to any one of claims 1-7.

The second gate electrodes has a two-layer or polycide layer of polysilicon metal, field effect transistor according to any one of claims 1 to 8.

A portion of the side surface of the uplift the web type covered depending on the gate oxide layer is thus bounded on trench isolation rate cane down, the field effect transistor according to any one of claims 1 to 9 .

The depth of the doping profile of the source region and the drain region, between the uplift of the bottom surface of said web type covered depending on the gate oxide layer, and the bottom surface of the second gate oxide layer height The field effect transistor according to claim 1, wherein the field effect transistor is larger than the difference in thickness.

A method of manufacturing a field effect transistor, in particular a MIS field effect transistor, comprising:
the method comprising a) a semiconductor substrate is provided, a first gate oxide layer is applied on top of the semiconductor substrate, applied to the first gate oxide layer gate electrode layer is the first of which comprises a side surface are the steps,
Even without least that having a b) on plane contact and the side surface a single web type of Takashi outs generated Ru step, a gate oxide layer contact and the first gate electrode layer of the first is the is disposed on the said upper surface of the web-type raised, a step,
a step c) the second gate oxide layer is made green also less over a portion of the side surface of said web type uplift of the side surfaces of the portion and the first gate electrode layer,
The Rukoto d) a second gate electrode layer is applied, the gate electrode layer of the second is placed on the upper surface of said gate oxide layer 2, and the first gate electrode layer Process,
e) a gate electrode layer of the gate electrode layer contact and the second first is patterned to form the first and second gate electrodes comprises the step of the source and drain regions are produced , mETHODS.

Wherein the uplift web type is produced by patterning of a trench for the trench isolation rate cane down method of claim 12.

The trenches for the trench isolation is filled with oxide, and etching back is performed, a result, the portion of the side surface of the uplift web type is exposed, according to claim 13 Method.

The method of claim 14, wherein a CMP step is performed prior to the etch back.

To rounded the edge of the raised of said web type between said side surface of ridge of the top surface and the web-type web-type raised, at least one thermal treatment is performed, according to claim 12 The method according to any one of -15.

The method according to claim 12, wherein each of the gate oxide layers is generated by thermal oxidation.

The second gate oxide layer is produced by selective oxidation, thereby, the second gate oxide layer, said than on a web type of Takashi the side of force, said first gate electrode 18. The method according to any one of claims 12 to 17, wherein the method is made thicker on the side of the pole .

Insulating spacer, said first gate electrode layer is generated after being generated, thereby, at the level of the gate electrodes of the first, an insulating spacer is disposed on the second gate oxide layer The method according to any one of claims 12 to 18.