JP2870472B2 - Vertical field-effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical electric field transistor, and more particularly to a structure of a channel surface thereof.

[0002]

2. Description of the Related Art A conventional vertical field effect transistor of this type has a structure shown in FIG. FIG. 6 is a schematic vertical cross-sectional view of a conventional vertical field effect transistor. In FIG. 6, reference numeral 61 denotes an N ⁺ type semiconductor substrate; 62, an N type epitaxial layer; 63, a P base; N ⁺ source, 65 is a gate oxide film, 66 is polysilicon, 67 is a BPSG film, 68
Indicates aluminum and 69 indicates metal.

[0003] N having a resistivity of about 0.01 Ω-cm⁺ Mold half
The resistivity is 0.3 to 3.0 Ω-cm on the conductive substrate 61 and the thickness is
The N-type epitaxial layer 62 having a thickness of about 4 to 20 μm is formed.
Upper surface of N-type epitaxial layer 62 of the formed semiconductor substrate
At a boundary between adjacent cells of about 1.0 μm
A V-shaped recess having a flat top is formed, and the V
Contact the side of the V-shape so that a channel is formed on the side of the mold.
To expand the P base 63 having a diffusion depth of 0.7 to 1.0 μm.
N with diffused layer and diffusion depth of 0.3 to 0.5 μm ⁺ Source
64 diffusion layers are formed on the surface of the N-type epitaxial layer 62
And a thickness of 400 to 10 so as to cover the surface of the concave portion.
A gate oxide film 65 of about 00 Å is formed.
And then P (phosphorus) was doped at a high concentration of about 500
0 angstrom polysilicon 66 is formed.
You.

Further, a thickness of about 5000 which becomes an interlayer insulating film.
After a BPSG film 67 (boron phosphorus silicate glass) of 10,000 to 10000 Å is formed on the surface,
A contact portion is opened in the SG film 67, and has a thickness of about 2. mm on the surface so as to be connected to the P base 63 and the N ⁺ source 64.
Aluminum 68 having a thickness of 0 to 5.0 μm is deposited thereon, which serves as a source electrode. On the back surface of the semiconductor substrate, an Au-Sb-based metal 69 is deposited, which serves as a drain electrode.

[0005]

In the above-mentioned conventional field-effect transistor, the recess is formed by the LOCOS method. However, the wall surface of the recess is usually formed on the crystal plane (111) from the viewpoint of processing technology. Processing is controlled to be (NIKKIEELECTRONICS, 1994,
9, 5 No. 616). That is, in the most commonly used (100) plane wafer, when a normal square cell is used, the angle of the slope of the concave portion is about 55 °. Further, a method of forming a groove by using a reactive ion etching (RIE) method is also used, but there is a problem that the on-resistance Ron is hard to decrease due to the influence of a crystal defect generated on a side surface of the groove.

The on-resistance Ron during operation is an important parameter in determining the performance of this type of field-effect transistor. However, when the on-resistance Ron is divided into components, the channel resistance Rch, the epitaxial resistance Repi, the substrate When the breakdown voltage between the source and the drain is lowered, the resistance Rch with respect to the entire resistance Ron is reduced.
Ratio increases.

[0007] channel resistance Rch is represented by Rch = 1 / {μ · C OX · (V G -V TH) · W / L}.

[0008] However, mu: inversion layer mobility, C _OX: capacitance, V _G: gate - G Voltage, V _TH: the gate threshold voltage, W: channel width, L: channel length, where mu (inversion layer moves Degree) is known to depend on the crystal plane, and is approximately indicated by the following index.

(011) :( 111) :( 100) is approximately 1: 1.5: 2.0, and (011) :( 11)
1) :( 511) is approximately 1: 1.5: 2.0.

As a result, the inversion layer mobility on the (111) plane in the conventional example is 1.5 times that of the (011) plane.
There is a problem that Ron is higher than the (100) or (511) plane, and as a result, Ron is higher than the (100) or (511) plane.

The surface state density differs depending on the crystal plane, and is (100) or (511) rather than the (111) plane.
The surface is superior, and for this reason, there is a problem that instability occurs more easily in (111) than in (100) or (511) in reliability.

An object of the present invention is to provide a vertical field effect transistor having high inversion layer mobility and excellent reliability.

[0013]

A vertical field effect transistor according to the present invention has a base region of a second conductivity type in a semiconductor substrate of a first conductivity type, and a source region of a first conductivity type in the base region. A concave portion is formed at a boundary portion so as to straddle a base region and a source region of an adjacent cell, an insulating film is formed so as to overlap a surface of the concave portion, and a gate electrode is formed so as to overlap the insulating film. A gate electrode is covered with an interlayer insulating film, and a metal serving as an electrode is attached on the interlayer insulating film so as to connect to a part of the base region and a part of the source region. In a vertical field-effect transistor in which a metal serving as a drain electrode is attached to a lower surface, a wall surface of a concave portion serving as a channel has an angle of 79 ° ± 5 ° with respect to the surface of the semiconductor substrate.

The concave portion may be formed by using the LOCOS method, and the angle of the wall surface of the concave portion with respect to the surface of the semiconductor substrate is determined by a combination of the reactive ion etching (RIE) method and the LOCOS method. It may be formed by processing control.

A semiconductor substrate is a wafer having a {100} main surface and an {011} orientation flat surface, and each side of each cell is parallel and perpendicular to the orientation flat surface. May be processed, using a wafer whose main surface is a {100} surface and whose orientation flat surface is a {001} surface,
Each cell may be processed so that each side is parallel to and perpendicular to the orientation flat surface.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view showing a used wafer and a cell arrangement according to the first embodiment of the present invention,
FIG. 2 is a schematic longitudinal sectional view of the vertical field effect transistor of the present invention, and FIG. 3 is a schematic longitudinal sectional view showing the manufacturing process of the vertical field effect transistor of the first embodiment of the present invention. (A) shows a state where a concave portion serving as a channel portion is etched in a semiconductor substrate, and (b) shows a state where a thermal oxide film is formed in the concave portion. In the figure, reference numeral 11 denotes a wafer, 12 denotes an orientation flat, 13
Is a square cell, 21 is an N ⁺ type semiconductor substrate, 22 is an N type epitaxial layer, 23 is a P base, 24 is an N ⁺ source, 2
5 is a gate oxide film, 26 is polysilicon, 27 is BPS
G film, 28 is aluminum, 29 is metal, 30 is thermal oxide film,
Reference numeral 31 denotes a nitride film, 32 denotes a resist, and 33 denotes a second thermal oxide film.

In the first embodiment, as shown in FIG. 1, a wafer 11 having a {100} principal plane and an {011} orientation flat 12 is used. A square cell 13 is formed so as to be parallel and perpendicular to the plane. Figure 2
FIG. 4 is an AA cross section of the square cell 13 of FIG.
4B and B 'of FIG. 4 show B and B' of the square cell of FIG.

An N-type epitaxial layer 22 having a resistivity of about 0.3 to 3.0 Ω-cm and a thickness of about 4 to 20 μm is formed on an N ⁺ type semiconductor substrate 21 having a resistivity of about 0.01 Ω-cm. A thermal oxide film 30 having a thickness of about 500 angstroms and a nitride film 31 having a thickness of about 1000 angstroms are sequentially formed on the upper surface of the n-type epitaxial layer 22 of the semiconductor substrate, and after predetermined patterning with a resist 32, reactive ion etching is performed. The silicon (Si) is etched to a depth of about 0.8 μm by (RIE) to form a concave portion (FIG. 3A).

After the resist 32 is removed, 1140 ° C.
LOCOS oxidation is performed at a temperature of about 7
A thick second thermal oxide film 33 of 2,000 angstroms is formed on the wall surface of the etched recess [FIG.
(B)].

The angle of the wall of the recess can be controlled to some extent by the etching amount of the recess and the oxide film thickness. FIG. 4 is an explanatory view showing the relationship between the Si etching depth and the angle of the wall of the recess,
(A) is a graph showing the relationship between the Si etching depth and the angle of the wall of the concave portion, (b) is a longitudinal sectional view near the concave portion, in which 42 is an N-type epitaxial layer, 43 is a P base, 44 is an N ⁺ source, 45 is a gate oxide film, 46 is polysilicon, 47
Indicates a BPSG film, 48 indicates aluminum, and θ indicates an angle. FIG.
(A) shows that the angle θ of the wall of the concave portion can be controlled by the Si etching depth.

Thereafter, the nitride film 31 is removed, ion implantation of the P base 23 is performed using the second oxide film 33 as a mask,
⁺ Ion implantation of the source 24 is performed, and the diffusion depth is
A diffusion layer of the P base 23 having a thickness of 7 to 1.0 μm and a diffusion layer of the N ⁺ source 24 having a diffusion depth of 0.3 to 0.5 μm are formed.

Next, after the second oxide film 33 and the thermal oxide film 30 are removed, a gate oxide film 25 having a thickness of about 500 angstroms is formed on the wall surface of the concave portion. After a highly doped polysilicon 26 serving as a gate electrode of about 5000 angstroms is formed, and a BPSG film 27 serving as an interlayer insulating film having a thickness of about 6000 angstroms is formed on the surface, a contact portion is opened at a predetermined position. I do.

Aluminum 2 having a thickness of about 2.0 to 5.0 μm is formed on the surface so as to be connected to P base 23 and N ⁺ source 24.
8 is deposited, which becomes a source electrode, and an Au-Sb-based metal 29 is deposited on the back surface of the semiconductor substrate, which becomes a drain electrode (FIG. 2).

As described above, in such a process, the angle of the wall serving as the channel of the concave portion is controlled by controlling the etching amount (depth) of silicon and the thickness of the LOCOS oxide film. ° or so. In addition, crystal defects generated on the wall surface by etching are:
It is removed at the same time by removing the thick LOCOS oxide film.

As a result, the ion mobility is high, the on-resistance during operation is low, and the surface state density is low.
It is possible to obtain a vertical field effect transistor having stable reliability.

Next, a second embodiment will be described.
FIG. 5 is a perspective view showing a used wafer and cell arrangement according to the second embodiment of the present invention. In the figure, 51 indicates a wafer, 52 indicates an orientation flat, and 53 indicates a square cell.

In the second embodiment, as shown in FIG. 2, a wafer 51 whose principal surface is a {100} plane and whose orientation flat 52 is a {001} plane is used. A square cell 53 is formed to be vertical. Other manufacturing methods and structures are the same as those of the first embodiment.

In this embodiment, the channel surface is paired with the main surface.
Thus, the angle can be set to around 79 ° , and the same effect as in the first embodiment can be obtained.

In the above description of the embodiment, the cells are square cells, but some corners of the square cells may be cut off to form octagon cells.

In this embodiment, the RIE method and the LOC
Although the angle of the channel surface is controlled by a method that is used in combination with the OS method, it is possible to control the angle to within 79 ° ± 5 ° by performing complicated processing control only with the LOCOS method.

The plane of the orientation flat is set to $ 01
The channel plane is {511} plane or {1} plane by setting each side of the square cell to be parallel and perpendicular to the orientation flat plane.
The angle can be easily controlled within 79 ° ± 5 °, but if complicated processing control is performed, the desired angle and angle can be obtained using other surfaces. It is not impossible to do.

[0032]

As described above, according to the present invention, the angle of the wall surface of the concave portion serving as the channel portion provided in the semiconductor substrate can be easily set at around 79 °, and as described above, the ion mobility is reduced. There is an effect that a highly reliable vertical field effect transistor which is large, has a small on-resistance Ron during operation, and has a small surface state density can be obtained.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a used wafer and a cell arrangement according to a first embodiment of the present invention.

FIG. 2 is a schematic vertical sectional view of a vertical field effect transistor of the present invention.

FIG. 3 is a schematic vertical sectional view showing a manufacturing process of the vertical field effect transistor according to the first embodiment of the present invention.
(A) shows a state where a concave portion serving as a channel portion is etched in a semiconductor substrate. (B) shows a state in which a thermal oxide film is formed in the concave portion.

FIG. 4 is an explanatory diagram showing a relationship between a Si etching depth and an angle of a wall of a concave portion. (A) is a graph showing the relationship between the Si etching depth and the angle of the wall of the concave portion. (B) is a longitudinal sectional view near the concave portion.

FIG. 5 is a perspective view showing a used wafer and a cell arrangement according to a second embodiment of the present invention.

FIG. 6 is a schematic longitudinal sectional view of a conventional vertical field effect transistor.

[Explanation of symbols]

11, 51 wafer 12, 52 orientation flat 13, 53 square cell 21, 61 N ⁺ type semiconductor substrate 22, 42, 62 N type epitaxial layer 23, 43, 63 P base 24, 44, 64 N ⁺ source 25, 45, 65 Gate oxide film 26, 46, 66 Polysilicon 27, 47, 67 BPSG film 28, 48, 68 Aluminum 29, 69 Metal 30 Thermal oxide film 31 Nitride film 32 Resist 33 Second thermal oxide film

Claims (5)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type having a base region of a second conductivity type, a source region of a first conductivity type in the base region, and a base region and a source of an adjacent cell. A concave portion is formed at the boundary portion so as to straddle the region, an insulating film is formed so as to overlap the surface of the concave portion,
Further, a gate electrode is formed so as to overlap the insulating film to form a MOS structure. The gate electrode is covered with an interlayer insulating film, and is connected to a part of the base region and the source region above the interlayer insulating film. In a vertical field-effect transistor in which a metal serving as an electrode is deposited and a metal serving as a drain electrode is deposited on the lower surface on the opposite side of the semiconductor substrate, the wall of the concave portion serving as a channel portion is formed of the semiconductor. A vertical field-effect transistor having an angle of 79 ° ± 5 ° with respect to the surface of the substrate. 2. The vertical field effect transistor according to claim 1, wherein said recess is formed by using a LOCOS method. 3. The vertical field effect transistor according to claim 1, wherein an angle of a wall surface of the concave portion with respect to a surface of the semiconductor substrate is determined by a reactive ion etching (RIE) method and a LOCOS method. A vertical field-effect transistor, which is formed by processing control in combination with: 4. The vertical field effect transistor according to claim 2, wherein the semiconductor substrate is a wafer having a {100} principal plane and an {011} orientation flat plane, A vertical field-effect transistor wherein a side is processed so as to be parallel to and perpendicular to the orientation flat surface. 5. The vertical field-effect transistor according to claim 2, wherein the semiconductor substrate is a wafer whose principal surface is a {100} surface and whose orientation flat surface is a {001} surface. A vertical field-effect transistor wherein a side is processed so as to be parallel to and perpendicular to the orientation flat surface.