JP2004529402A5 - - Google Patents

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Publication number
JP2004529402A5
JP2004529402A5 JP2002548785A JP2002548785A JP2004529402A5 JP 2004529402 A5 JP2004529402 A5 JP 2004529402A5 JP 2002548785 A JP2002548785 A JP 2002548785A JP 2002548785 A JP2002548785 A JP 2002548785A JP 2004529402 A5 JP2004529402 A5 JP 2004529402A5
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JP
Japan
Prior art keywords
net
cost
diagonal
circuit
length
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Pending
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JP2002548785A
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English (en)
Japanese (ja)
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JP2004529402A (ja
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Priority claimed from US09/732,181 external-priority patent/US6826737B2/en
Priority claimed from US09/731,891 external-priority patent/US7024650B2/en
Application filed filed Critical
Priority claimed from PCT/US2001/046406 external-priority patent/WO2002047165A2/en
Publication of JP2004529402A publication Critical patent/JP2004529402A/ja
Publication of JP2004529402A5 publication Critical patent/JP2004529402A5/ja
Pending legal-status Critical Current

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JP2002548785A 2000-12-06 2001-12-05 配置の際に対角線配線を考慮に入れるための方法および装置 Pending JP2004529402A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/732,181 US6826737B2 (en) 2000-12-06 2000-12-06 Recursive partitioning placement method and apparatus
US09/731,891 US7024650B2 (en) 2000-12-06 2000-12-06 Method and apparatus for considering diagonal wiring in placement
PCT/US2001/046406 WO2002047165A2 (en) 2000-12-06 2001-12-05 Method and apparatus for considering diagonal wiring in placement

Publications (2)

Publication Number Publication Date
JP2004529402A JP2004529402A (ja) 2004-09-24
JP2004529402A5 true JP2004529402A5 (US20040098680A1-20040520-M00007.png) 2005-12-22

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Application Number Title Priority Date Filing Date
JP2002548785A Pending JP2004529402A (ja) 2000-12-06 2001-12-05 配置の際に対角線配線を考慮に入れるための方法および装置

Country Status (7)

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US (1) US6904580B2 (US20040098680A1-20040520-M00007.png)
EP (1) EP1362373A2 (US20040098680A1-20040520-M00007.png)
JP (1) JP2004529402A (US20040098680A1-20040520-M00007.png)
CN (1) CN1529864B (US20040098680A1-20040520-M00007.png)
AU (1) AU2002233977A1 (US20040098680A1-20040520-M00007.png)
TW (1) TW564575B (US20040098680A1-20040520-M00007.png)
WO (1) WO2002047165A2 (US20040098680A1-20040520-M00007.png)

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US20070006106A1 (en) * 2005-06-30 2007-01-04 Texas Instruments Incorporated Method and system for desensitization of chip designs from perturbations affecting timing and manufacturability
CN102054068B (zh) * 2009-10-30 2014-06-18 新思科技(上海)有限公司 芯片设计中的线网分配方法与装置
CN116011389B (zh) * 2023-01-28 2023-06-06 上海合见工业软件集团有限公司 基于空间约束的电路原理图路由规划系统
CN116050339B (zh) * 2023-01-28 2023-07-21 上海合见工业软件集团有限公司 电路原理图路由规划系统

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