JP2004526299A - Integrated CMOS capacitive pressure sensor - Google Patents

Abstract

The capacitive pressure sensor (10) uses a diaphragm (38) formed at the same time as forming the gates (56, 57) of active elements on the same semiconductor substrate (11).

Description

[0001]
(Background of the Invention)
The present invention relates generally to semiconductor devices and processes, and more particularly, to monolithic pressure sensors integrated in CMOS circuits.
[0002]
The semiconductor industry has in the past formed capacitive pressure sensors that are compatible with CMOS circuit elements and can be integrated within CMOS circuits. Examples of such pressure sensors are described in U.S. Pat. Nos. 5,321,989 and 5,431,057 issued to Gunther Zimmer et al. And the paper "A Fully" by Dudaiiceevs et al. Integrated Surface Micromachined Pressure Sensor with Low Temperature Dependence "8th Int. Conf, Solid State Sensors and Actors and Eurosensors IX, June 25-29, pages 616-619, all of which are incorporated herein by reference.
[0003]
Generally, a pressure sensor includes a fixed electrode formed in a substrate as a doved portion below a sensor diaphragm. Generally, the electrode region is doped by implantation, which is done simultaneously with the implantation of the source and drain of a CMOS transistor formed in the same substrate. Thereafter, a (poly) silicon diaphragm is formed overlying the diffused electrode area. Subsequently, polysilicon implantation and annealing are performed to dope the polysilicon. This annealing operation affects the implantation of the source and drain of the CMOS device, resulting in a change in the characteristics of the CMOS transistor. As a result, the characteristics of the CMOS transistor differ from the originally desired characteristics.
[0004]
Therefore, there is a need for a method of forming a pressure sensor integrated in a CMOS transistor that does not adversely affect the characteristics of the CMOS transistor.
[0005]
(Detailed description of drawings)
In all of the following description of the drawings, the same reference numbers are used throughout the drawings to represent the same elements.
[0006]
FIG. 1 schematically shows an enlarged cross-section of a pressure sensor built on a monolithic semiconductor substrate 11 and an integrated pressure sensor 10 having CMOS circuits. Substrate 11 is formed of a first conductivity type (corresponding to a later P-type) and includes a sensor portion or region generally indicated at 16 and a CMOS portion or region generally indicated at 17. In a preferred embodiment, substrate 11 is P-type. The substrate 11 has a first well region 12 or a sensor well 12 and a second well region 13 on the surface of the substrate 11, and both the first well region 12 and the second well region 13 have the second conductivity type. It is. Well regions 12, 13 are formed by techniques well known to those skilled in the semiconductor art. In a preferred embodiment, well regions 12 and 13 oxidize the surface of substrate 11 to expose a portion of the surface of substrate 11 using a silicon nitride mask, followed by N 2 in the exposed portion of substrate 11. It is formed by implanting a type of dopant and subsequently oxidizing to form an oxide layer overlying the well regions 12,13. Thereafter, in this preferred embodiment, the nitride mask is removed, and a dopant of the first conductivity type is implanted into the surface of the base 11 and into the region where the third well region 14 is formed. Subsequently, the dopants of the well regions 12, 13, and 14 are implanted into the substrate 11 to form the well regions 12, 13, and 14. In this preferred embodiment, third well region 14 has a P-type doping that is 5 to 100 times that of substrate 11. Further, in the preferred embodiment, well region 13 is often referred to as N-type well 13 and well region 14 is referred to as P-type well 14. As will be appreciated from the description below, well region 12 will function as an RF / EMI shield that minimizes variations in sensor 10 capacitance due to RF / EMI interference.
[0007]
FIG. 2 schematically shows a subsequent step of manufacturing the sensor 10. The sensor insulating portion 18 is formed in the surface of the substrate 11 so as to rest on the well region 12 and to extend into the well region 13. The insulation 18 will later act to isolate the pressure sensor from other CMOS circuits formed in the substrate 11. Insulation 18 may be a variety of insulating regions, such as a field oxide region, an oxide or nitride film deposited on substrate 11, an oxidized poly layer, or other insulators known to those skilled in the art. The insulating part 18 is formed in the sensor area 16 of the sensor 10. In a preferred embodiment, insulation 18 is a first field oxide. A well insulating field oxide film 19 is formed in the surface of the substrate 11 between the well region 13 and the well region 14, and a well insulating field oxide film 21 is formed in the well region 14 on the surface of the substrate 11. The field oxide 19 and the field dopant 20 associated with the field oxide 19 are used to insulate CMOS transistors used in CMOS devices formed in the sensor 10 and include a field oxide 21 and a field oxide. Field dopant 20 associated with film 21 is used to insulate the devices formed in well region 14. Field oxide films 19, 21 and field dopant 20 are formed by techniques well known to those skilled in the semiconductor art. Generally, the thickness of the insulating portion 18 is 0.3 to 1.0 μm, preferably about 0.75 μm.
[0008]
In a preferred embodiment, the insulating portion 18 or the first field oxide film 18, the second field oxide film 19 or the well insulating field oxide film 19, and the third field oxide film 21 or the cell insulating field oxide film 21 are formed simultaneously. . P-type transistors subsequently formed in well region 14 are also isolated from EEPROM cells similarly formed in well 14. Subsequently, a thin blanket tunnel oxide 22 is applied overlying the surface of the overlying insulator 18, the field oxides 19,21 and the well regions 13,14. In this preferred embodiment, layer 22 will then be used to form an EEPROM in well region 14. Such a tunnel oxide is formed by techniques well known to those skilled in the semiconductor arts, including oxidation in a nitrogen oxide (N ₂ O) atmosphere that precisely controls the thickness of layer 22. Layer 22 is generally very thin due to the thickness of insulation 18 and due to the generally limited diffusion in the formation of layer 22. Layer 22 has a thickness in the range of 3 to 15 nm, preferably about 0.5 to 1.0 nm. Thereafter, a floating gate blanket polysilicon layer 23 is deposited overlying layer 22.
[0009]
In an alternative embodiment, the insulation 18 is formed with a trench in the substrate 11 so that it has a sufficient surface area to form the diaphragm of the sensor 10, i.e., the area of the insulation in the generally preferred embodiment. May be formed. Thereafter, thermal oxidation is performed on the insulating layer extending over the trench surface and the substrate surface. In many cases, the surface of the substrate 11 is planarized using chemical mechanical polishing or other techniques after such oxidation.
[0010]
The use of a tunnel oxide, floating gate, gate oxide, or gate poly formation process (described below) to form the fixed electrode of the sensor 10 facilitates integration of the CMOS process flow and manufacturing costs. And the characteristics of the device are improved.
[0011]
FIG. 3 shows the sensor 10 after a subsequent process. The layers 23, 22 (shown in FIG. 2) are patterned and etched to provide a first doped polysilicon of the sensor 10 on the electrode tunnel oxide region or the first tunnel oxide region 24 on the surface of the insulation 18. A region 28 or a fixed electrode 28 is formed. The polysilicon region 29 or the sensor contact 29 of the contact and the tunnel oxide film region 26 of the contact are formed simultaneously with the electrode 28 on the surface of the insulating portion 18. Although not shown in FIG. 3, the electrode 28 and the sensor contact 29 are electrically continuous on the surface of the insulating portion 18. As described in the description of FIG. 2, the layer 22 over the insulation 18 is too thin to be detected or non-existent. The floating gate region or the second doped polysilicon region 31 is formed on the floating gate tunnel oxide film 27 or the second tunnel oxide film region 27 simultaneously with the electrode 28 and the sensor contact 29. By patterning and etching, a second tunnel oxide region 27 is formed on the surface of the substrate 11 adjacent to the field oxide film 21. The patterning and etching steps employed are well known to those skilled in the semiconductor art. It should also be noted that, for example, the conductive materials of electrodes 28 and contacts 29 may be formed in separate steps, such as forming and patterning separate doped poly layers.
[0012]
In a preferred embodiment, a mask is then applied to facilitate implantation of dopants into well 14 adjacent second doped poly region 31 to form doped region 52. Region 52 will be utilized as part of an EEPROM cell formed as part of sensor 10. Generally, a gate oxide is formed over the sensor 10 and removed from the sensor region 16 by methods well known to those skilled in the art. Another mask is applied to facilitate the implantation of dopants in the doped region 53 and to adjust the threshold of the transistor between the field oxides 19, 21 in the well 14.
[0013]
FIG. 4 shows the sensor 10 after forming a protective layer 35 that covers the CMOS region 17 and extends into the sensor region 16 to reach the sensor contact 29 in a subsequent step. The protection layer 35 includes a second polysilicon layer 32 and an etch stop layer 33 covering the layer 32. Layers 32, 33 are formed by blanket deposition of polysilicon followed by blanket deposition of an etch stop material, both of which are patterned and etched to form layers 33, 32 over portions of sensor region 16. Formed by removing a portion of the As a result of this removal operation, protective layer 35 overlies well region 14 and region 31 and extends beyond field oxide film 21 across well region 14 and across well region 13 across field oxide film 19. The protective layer 35, which includes the layers 32, 33, remains above the insulating material 18 adjacent to the edge of the sensor contact 29. Layer 32 will then be used to form the gate of the CMOS transistor. It should be noted that if the material of layer 32 is doped to provide a conductor in the region of electrode 28 and contact 29, layer 32 may also be utilized in forming electrode 28 and contact 29. In a preferred embodiment, etch stop layer 33 is tetraethylorthosilicate (TEOS).
[0014]
FIG. 5 shows the results of a subsequent process performed on the sensor 10. The sensor nitride film 34 is formed on the insulating material 18 and overlaps the edge of the electrode 28, extends to the CMOS region 17, rests on the well regions 13 and 14, and over the field oxide films 19 and 21. It is listed in In a preferred embodiment, the nitride film 34 is a low stress, high silicon-containing silicon nitride layer 34 formed by blanket deposition followed by patterning and etching exposing the electrode 28. Alternatively, layer 34 may be a stoichiometric silicon nitride layer.
[0015]
FIG. 6 shows the sensor 10 after formation of the sacrificial layer, having a sensor region or first sacrificial layer portion 36 and a CMOS region or second sacrificial layer portion 37. A first sacrificial layer portion 36 is formed on the electrode 28 and extends over the layer 34, and a second sacrificial layer portion 37 overlies the sensor contact 29, well regions 13 and 14, and field oxides 19 and 21. Formed on a portion of layer 34. The sacrificial layer portions 36, 37 are formed by methods well known to those skilled in the semiconductor art, such as blanket deposition of PSG and subsequent patterning and etching. In a preferred embodiment, the sacrificial layer portions 36, 37 are PSG films, followed by annealing prior to masking and etching. The thickness of the first sacrificial layer portion 36 is used to determine the capacitor gap of the completed pressure sensor. The second sacrificial layer portion 37 is used to facilitate protection of the CMOS region 17 during subsequent formation of the sensor diaphragm. Multiple sacrificial layers may be used to form sacrificial layer portions 36,37. In a preferred embodiment, sacrificial layer portions 36, 37 have a thickness of 0.2-1.0 μm.
[0016]
Referring to FIG. 7, a subsequent stage of manufacture of the sensor 10 after forming the pressure sensor diaphragm 38 resting on the fixed electrode 28 is shown. In a preferred embodiment, the diaphragm 38 first deposits a blanket deposit of polysilicon on the surface of the sensor 10 and then implants dopants to form a doped polysilicon layer. Thereafter, a mask is applied to protect the diaphragm 38 that is to remain on the sensor 10 while the other portion of the polysilicon layer, ie, the polysilicon layer over the second sacrificial layer portion 37 and over a portion of layer 34 Is removed. The mask has an opening overlying the diaphragm 38, so that while removing the exposed polysilicon layer, an etch release opening 54 is formed through the diaphragm 38 to form the first underlying layer. The surface of the sacrificial layer portion 36 is exposed. Generally, the etch used to remove the exposed polysilicon does not affect the sacrificial layer portions 36, 37 (shown in FIG. 6).
[0017]
Thereafter, peel etching is performed to remove the first sacrificial layer portion 36 under the diaphragm 38 and also remove the second sacrificial layer portion 37 from the other surface of the sensor 10. The other surfaces of the sensor 10, including the surface of the CMOS region 17, are protected because the material used for the strip etch does not affect the underlying layer 34 that functions as an etch stop during the etching operation. Methods of forming the diaphragm 38 and removing the sacrificial layer portions 36, 37 (shown in FIG. 6) are well known to those skilled in the semiconductor art. In the present embodiment, since the stress applied to the diaphragm 38 is reduced by using a low-stress nitride at the lower portion of the diaphragm 38, a large surface area or a long depletion distance is obtained in a peel etching larger than 100 μm. The formation of the diaphragm becomes easy. The use of a layer 34 having a thickness of 0.2-1.0 μm facilitates such a deduction distance. In a preferred embodiment, the diaphragm 38 is formed to a thickness of 1 to 3 μm by compressive stress and may be formed from a plurality of layers.
[0018]
FIG. 8 shows a subsequent manufacturing stage of the sensor 10, wherein a sealing layer 39 is provided to seal the diaphragm 38. The material of the sealing layer 39 may be any material commonly used for sealing a sensor diaphragm. In general, layer 39 is formed by depositing a blanket deposit of TEOS, by non-conformal deposition to prevent lateral erosion of the deposited TEOS, or by line of sight deposition. Is done. After blanket deposition, an undesired portion of the sealant is removed by applying a mask to protect layer 39 while removing the sealant from CMOS region 17 and sensor contacts 29, as shown by dashed line 41. For example, a buffered oxide etch may be used to remove unwanted portions of the sealant. In a preferred embodiment, layer 39 has a thickness of about 1-4 μm. Other materials such as PSG, plasma enhanced nitride, and oxynitride may be used for layer 39.
[0019]
The mask is removed and a portion of layer 34 is removed from CMOS region 17 and sensor contact 29. This operation leaves the diaphragm 38 and the sealing layer 39 in contact with the layer 34. After removing layer 34, etch stop layer 33 is removed using blanket etching. In a preferred embodiment, a buffered oxide etch solution is used to remove the TEOS used in the etch stop layer 33.
[0020]
FIG. 9 shows the sensor 10 after several subsequent processes. In a preferred embodiment, a memory cell or an EEPROM specified by a broken line frame 46 is formed in the well region 14, and N-type and P-type CMOS transistors are formed in the corresponding well regions 13 and 14, respectively. After removal of the protective layer 35 described in the description of FIG. 8, the exposed protective poly layer 32 is patterned and etched to form the transistor gate 56 and the active gate 57 of the EEPROM cell. Gate 56 will be the CMOS transistor gate of transistors 43 and 44 (shown approximately in dashed boxes) formed in well regions 13 and 14. The formation of transistor gate 56 and active gate 57 is well known to those skilled in the art.
[0021]
Thereafter, the sensor 10 is masked to form a source / drain injection region 58 adjacent to the transistor gate 56 in the well regions 13 and 14. As is well known to those skilled in the art, implant region 58 may combine implants to form graded source / drain regions. In a preferred embodiment, a nitride spacer is formed adjacent to the transistor gate 56 to protect the gate 56 during subsequent siliconization of the gate 56. Such spacers and siliconization operations and methods are well known to those skilled in the semiconductor art. Subsequently, activation annealing is performed to activate the dopant in the implantation region 58. In a preferred embodiment, the activation annealing is a rapid thermal process performed at 900-1100C for 20-40 seconds. This activation also activates the dopants in diaphragm 38, releasing the stresses formed in diaphragm 38. By simultaneously activating and annealing the source / drain implant and the polysilicon doped with the diaphragm, the influence of the activation anneal of the diaphragm polysilicon on the characteristics of the CMOS transistor is avoided. In this way, the pressure transducer 42 indicated by the broken line frame is formed on the sensor 10.
[0022]
FIG. 10 shows the sensor 10 after the formation of the multiple layers of metal interconnects and the passivation film 49 protecting the sensor 10. The first interlayer insulating film 47 and associated metal interconnects, as well as the second interlayer insulating film 48 and device electrodes 51 are formed by methods well known to those skilled in the semiconductor field. The method of forming the passivation film 49 overlying the sensor 10 is well known to those skilled in the semiconductor field. Subsequently, a part of the passivation film 49 is removed to expose the device electrode 51 and the diaphragm 38. Generally, the passivation film 49 is a layer of oxynitride, but a known passivation material including silicon dioxide may be used.
[0023]
In one embodiment, the passivation film 49 is patterned by applying a mask to form openings corresponding to locations where the sensor openings 61 and contact openings 62 are to be formed. The exposed portion of the passivation film 49 is removed using wet buffered oxide etching (BOE). Etching is stopped before exposing the metal of the device electrode 51 to avoid corrosion of the metal of the contact 51 by BOE. Thereafter, the contact 51 is exposed by using dry etching, and the dielectric and the sealing layer 39 which are placed on the diaphragm 38 are removed. This dry etching must be stopped as soon as the diaphragm 38 is exposed to avoid etching or damage to the diaphragm 38.
[0024]
As is well known to those skilled in the art, a separate pressure transducer similar to transducer 42 is formed over a portion of sensor 10 at the distal end of transducer 42 to provide a differential capacitor sensor. To form
[0025]
In an alternative embodiment, an opening 61 is formed in interlayer insulating film 47 and a portion of underlying sealing layer 39 that is removed at the same time that an opening for metal contact through interlayer insulating film 47 is formed. May be. In this embodiment, it is important to remove all of the metal formed above the dielectric 38 and above the diaphragm 38 so that the metal does not affect the capacitance of the sensor 10. Thereafter, an opening 61 will be formed in the dielectric 48 while forming an opening for the metal of the contact 51. Any metal on the surface of the dielectric 48 resting on the diaphragm 38 also needs to be removed. Thereafter, the opening 61 will be formed in the passivation film 49 at the same time as the opening 62 is formed.
[0026]
In another alternative embodiment, a mask is applied to expose areas of the passivation film 49 where openings 61, 62 are to be formed. By using the dry etching, the layer 49 is penetrated and further penetrated to the lower part through the dielectrics 48 and 47 to expose the sealing layer 39 to form the openings 61 and 62. During wet etching to remove the material of the sealing layer 39, another mask is applied to protect the opening 62 and expose the opening 61, exposing the diaphragm 38.
[0027]
FIG. 11 shows an alternative embodiment of the sensor 10, wherein the sensor 10 is more recessed by recessing the diaphragm and sealing layers to a more planarized height with respect to the surface provided by the transistors 43, 44. A flat surface is provided. In this embodiment, a dent or moat is formed in well region 12 before forming field oxide film 18. The holes in well region 12 may be formed by a variety of well-known techniques, for example, anisotropic etching to form V-shaped or sloping sides, to facilitate subsequent processing steps.
[0028]
In another alternative embodiment, a mask is applied to expose regions of the passivation film 49 where the openings 62 will be formed. The opening 61 is formed using dry etching. After that, another mask is applied to expose the passivation region where the opening 61 is formed. Thereafter, the materials in the layers 49, 48, 47, and 39 are removed by using wet etching to expose the diaphragm 38.
[0029]
It should be understood that a novel integrated pressure sensor and method of manufacturing an integrated pressure sensor are now provided. Forming the diaphragm and fixed electrode over an insulating layer, such as a field oxide, isolates the diaphragm and fixed electrode from the CMOS and other activating elements of sensor 10. By forming the fixed electrode on the thin oxide film simultaneously with the floating gate electrode of the EEPROM cell, the processing steps required to form the fixed electrode are minimized. By forming a doped polysilicon diaphragm prior to implanting the source and drain regions of the CMOS transistor and annealing the polysilicon diaphragm at the same time as the source and drain implants, the characteristics of the CMOS transistor can be enhanced by annealing the polysilicon diaphragm. The ring ensures that it is not adversely affected.
[Brief description of the drawings]
FIG. 1 is a schematic illustration of an enlarged cross-section of an embodiment of an integrated pressure sensor according to the present invention during an initial manufacturing stage.
FIG. 2 is a schematic view of the pressure sensor of FIG. 1 according to the invention in a subsequent manufacturing stage.
FIG. 3 is a schematic view of the pressure sensor of FIG. 1 according to the invention in a subsequent manufacturing stage.
FIG. 4 is a schematic view of the pressure sensor of FIG. 1 according to the invention in a subsequent manufacturing stage.
FIG. 5 is a schematic view of the pressure sensor of FIG. 1 according to the present invention in a subsequent manufacturing stage.
FIG. 6 is a schematic view of the pressure sensor of FIG. 1 according to the invention in a subsequent manufacturing stage.
FIG. 7 is a schematic diagram of the pressure sensor of FIG. 1 according to the present invention in a subsequent manufacturing stage.
FIG. 8 is a schematic view of the pressure sensor of FIG. 1 according to the present invention in a subsequent manufacturing stage.
FIG. 9 is a schematic view of the pressure sensor of FIG. 1 according to the present invention in a subsequent manufacturing stage.
FIG. 10 is a schematic illustration of an enlarged cross-sectional portion of the integrated pressure sensor of FIGS. 1-9 after formation of a passivation film and a pressure sensor opening according to the present invention.
FIG. 11 is a schematic illustration of an enlarged cross-sectional portion of another embodiment of an integrated pressure sensor according to the present invention.

Claims (14)

A method of forming an integrated CMOS pressure sensor, comprising:
Forming a first conductivity type semiconductor substrate having a sensor region and a CMOS region;
Forming a sensor diaphragm resting on the fixed electrode of the sensor;
Forming a source / drain region of a CMOS transistor in the surface of the semiconductor substrate in the CMOS region of the semiconductor substrate before annealing the sensor diaphragm;
Annealing the sensor diaphragm and source / drain regions;
Method consisting of. The method of claim 1, wherein forming the sensor diaphragm comprises forming a sensor diaphragm that rests on a sensor insulation formed in a sensor region on a surface of a semiconductor substrate. Method. 3. The method of claim 2, wherein forming the sensor diaphragm comprises forming a sensor diaphragm from doped polysilicon overlying a fixed electrode and a sensor insulation. 3. The method of claim 2, wherein forming the sensor diaphragm comprises forming a fixed electrode over the sensor insulation. 3. The method of claim 2, wherein the step of forming the sensor diaphragm has a first portion on a sensor insulator and a second portion in a CMOS region on a surface of a semiconductor substrate. Forming a;
Forming a fixed electrode over a first portion of the tunnel oxide and forming a floating gate electrode over a second portion of the tunnel oxide prior to forming the diaphragm from doped polysilicon. Method. A method of forming a semiconductor pressure sensor, comprising:
Forming a first conductivity type semiconductor substrate having a sensor region and a CMOS region;
Forming a sensor insulating portion in the sensor region, and forming a field oxide region in the CMOS region on the surface of the semiconductor substrate, wherein the sensor insulating portion is separated from the field oxide region;
Forming a first doped polysilicon region as an electrode region resting on the sensor insulation, and forming a second doped polysilicon region as a floating gate region in the CMOS region;
Forming a sensor diaphragm of doped polysilicon overlying the first doped polysilicon region and forming a sealing layer overlying the sensor diaphragm; and Is protected during the formation of the sensor diaphragm and the sealing layer; and
Subsequently, implanting and annealing source / drain regions in the surface of the CMOS region of the semiconductor substrate;
Method consisting of. 7. The method of claim 6, wherein a first tunnel oxide is formed on a portion of the first field oxide region, and a second tunnel oxide is formed on a surface of the semiconductor substrate adjacent the second field oxide region. A method further comprising forming a tunnel oxide film. 7. The method of claim 6, wherein the step of forming the semiconductor substrate comprises: forming a first well region of a second conductivity type; a second well region of a second conductivity type; Forming a semiconductor substrate having a third well region, wherein the first well region, the second well region, and the third well region are formed on a surface of the semiconductor substrate. 9. The method of claim 8, wherein forming the first field oxide region comprises forming a first field oxide region overlying a portion of the first well region and a portion of the second well region. Forming a second field oxide region adjacent to the second well region and the third well region. 10. The method of claim 9, further comprising: forming a doped region in the third well region adjacent the floating gate portion of the tunnel oxide;
A sensor region over a portion of the first field oxide region and over the second well region, over the second field oxide layer, over the third well region, and over the doped polysilicon layer Forming a protection layer having a CMOS region on the floating gate portion of
A sensor region over a portion of the first field oxide region, overlying the doped polysilicon electrode portion, and over the second well region; over the second field oxide; Forming a low stress nitride film having a CMOS region over the well region and over the second floating gate portion of the doped polysilicon layer;
A doped polysilicon layer having a first portion over the electrode portion and over the second well region, over the second field oxide layer, over the third well region, and over the doped polysilicon. Forming a sacrificial layer having a second portion over and over a second floating gate portion of the layer. 11. The method of claim 10, wherein forming the pressure sensor diaphragm comprises: forming a polysilicon layer over the low stress nitride film and covering a first portion of the sacrificial layer;
Removing the sacrificial layer;
Providing a sealing layer on the diaphragm polysilicon layer;
Removing the low stress nitride film in the CMOS region;
Method consisting of. 11. The method of claim 10, wherein the implanting and annealing of the source / drain regions comprises implanting source / drain regions in the third well region to form a third well region and the tunnel oxide. Forming a floating gate of a memory cell overlying a second portion and implanting a source / drain region in the second well region to form a CMOS transistor in the second well region. A method of forming a semiconductor pressure sensor, comprising:
Forming a substrate of a semiconductor material of a first conductivity type, the substrate comprising a first well region of a second conductivity type, a second well region of a second conductivity type, A third well region, wherein the first well region, the second well region, and the third well region are formed on a surface of the substrate;
Forming a first field oxide region overlying a portion of the first and second well regions and forming a second field oxide region adjacent to the second and third well regions; When,
Forming a doped polysilicon layer having an electrode portion and overlying the first field oxide region, and having a floating gate portion overlying the third well region;
Forming a doped region in the third well region adjacent to the floating gate portion of the tunnel oxide film;
A sensor region over a portion of the first field oxide region, and doped over the second well region, over the second field oxide layer, over the step three well region; Forming an etch stop layer having a CMOS region on the floating gate portion of the polysilicon layer;
A sensor region over a portion of the first field oxide region, overlying a doped polysilicon electrode portion, and over a second well region, over a second field oxide layer; Forming a low stress nitride film having a CMOS region over the third well region and over the second floating gate portion of the doped polysilicon layer;
A first portion over the electrode portion of the doped polysilicon layer and over the second well region, over the second field oxide layer, over the third well region, and over the doped polysilicon. Forming a sacrificial layer having a second portion on and above a second floating gate portion of the layer;
Forming a polysilicon layer of the diaphragm by covering the low stress nitride film and the first portion of the sacrificial layer;
Removing the sacrificial layer;
Providing a sealing layer on the polysilicon layer of the diaphragm;
Removing the low stress nitride film in the CMOS region;
Implanting a source / drain region in the third well region to form a floating gate of a memory cell in the third well region and over a second portion of the tunnel oxide; Implanting source / drain regions in the region to form CMOS in the second well region;
Annealing the source / drain regions. 14. The method of claim 13, wherein forming the doped polysilicon layer has a first portion over a portion of the first field oxide region and a portion of the third well region. Forming a tunnel oxide film having a second portion thereon.