JP2008140867A - Semiconductor device mixedly mounted with micro electro mechanical system sensor - Google Patents

Semiconductor device mixedly mounted with micro electro mechanical system sensor Download PDF

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JP2008140867A
JP2008140867A JP2006323865A JP2006323865A JP2008140867A JP 2008140867 A JP2008140867 A JP 2008140867A JP 2006323865 A JP2006323865 A JP 2006323865A JP 2006323865 A JP2006323865 A JP 2006323865A JP 2008140867 A JP2008140867 A JP 2008140867A
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cavity
passivation film
semiconductor device
mems
sensor
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JP5127210B2 (en
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Tsukasa Fujimori
司 藤森
Hiroko Hanaoka
裕子 花岡
Hiroshi Fukuda
宏 福田
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Hitachi Ltd
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0058—Packages or encapsulation for protecting against damages due to external chemical or mechanical influences, e.g. shocks or vibrations
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0228—Inertial sensors
    • B81B2201/0235—Accelerometers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0264—Pressure sensors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/01—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
    • B81B2207/015—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being integrated on the same substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0136—Growing or depositing of a covering layer

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  • Microelectronics & Electronic Packaging (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
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  • Pressure Sensors (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To enhance the reliability of an MEMS sensor formed on a semiconductor integrated circuit. <P>SOLUTION: An MEMS portion including a cavity 12 is formed on a lower passivation film formed on the semiconductor integrated circuit, which consists of silicon nitride, etc. and has high moisture resistance and high chemical resistance. An upper passivation film 11 is formed on the top surface of the MEMS portion. The MEMS portion is hermetically sealed by the passivation films. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、ＭＥＭＳ（Ｍｉｃｒｏ Ｅｌｅｃｔｒｏ Ｍｅｃｈａｎｉｃａｌ Ｓｙｓｔｅｍ）技術を用いたセンサを混載した半導体装置に関する。それは、特に、センサの高信頼性に関して有効な技術である。   The present invention relates to a semiconductor device in which a sensor using a MEMS (Micro Electro Mechanical System) technology is mixedly mounted. It is an effective technique especially regarding the high reliability of the sensor.

ＭＥＭＳ技術を用いたセンサに関しては、例えば、特開２００６-１５６１８２号公報（特許文献１）に、窒化シリコン膜でパッシベーションする技術が開示されている。可動電極と固定電極を対向配置させた静電容量式ＭＥＭＳ圧力センサを半導体回路配線層上に形成し、ＭＥＭＳを含む最上層を窒化シリコン膜でパッシベーションする。最上層を窒化シリコン膜とする理由は、耐環境性能を高めるためである。   Regarding a sensor using the MEMS technology, for example, Japanese Patent Application Laid-Open No. 2006-156182 (Patent Document 1) discloses a technology for passivation with a silicon nitride film. A capacitive MEMS pressure sensor in which the movable electrode and the fixed electrode are arranged to face each other is formed on the semiconductor circuit wiring layer, and the uppermost layer including the MEMS is passivated with a silicon nitride film. The reason why the uppermost layer is a silicon nitride film is to improve environmental resistance.

特開２００６-１５６１８２号公報JP 2006-156182 A

しかしながら、従来の技術は、センサ特性のドリフトを引き起こす恐れがあった。これは、ＭＥＭＳ部に生じる高段差部へのパッシベーション膜にピンホールが発生し、水分がＭＥＭＳセンサ内部に浸透、もしくはＭＥＭＳセンサを構成する膜質の変質による為である。又、こうした事を回避するために、従来の半導体集積回路に用いてきたような厚さ１マイクロメートル程度のパッシベーション膜を適用することも考えられる。しかし、この場合、ＭＥＭＳセンサの動作に大きな影響を与えてしまうため、適用が難しい。又、特に圧力センサは、半導体基板上に形成した感圧部を直接大気暴露しなくてはならず、装置の信頼性の確保は重大な課題であった。   However, the conventional technology may cause a drift in sensor characteristics. This is because a pinhole is generated in the passivation film to the high step portion generated in the MEMS portion, and moisture permeates into the MEMS sensor or the quality of the film constituting the MEMS sensor is changed. In order to avoid such a situation, it is conceivable to apply a passivation film having a thickness of about 1 μm as used in a conventional semiconductor integrated circuit. However, in this case, since the operation of the MEMS sensor is greatly affected, it is difficult to apply. In particular, in the pressure sensor, the pressure-sensitive part formed on the semiconductor substrate has to be directly exposed to the atmosphere, and ensuring the reliability of the apparatus is a serious problem.

本発明では、次のような方策を取る。即ち、半導体集積回路の配線層上にＭＥＭＳ構造体を形成する場合に、まず半導体集積回路を通常の半導体技術により形成し、最上部を平坦化してから下部パッシベーション用膜を成膜する。この下部パッシベーション膜上に、ＭＥＭＳセンサ部を形成した後、ＭＥＭＳ部及び回路部を含めて、上部パッシベーション膜を更に成膜し、全体を覆う。即ち、ＭＥＭＳセンサ部を上下パッシベーション膜で密封する構造とする。これにより、段差部で上部パッシベーション膜にピンホールが発生したとしても、そのピンホール直下は下部パッシベーション膜であり、信頼性を損なう恐れを回避可能となる。   In the present invention, the following measures are taken. That is, when the MEMS structure is formed on the wiring layer of the semiconductor integrated circuit, the semiconductor integrated circuit is first formed by a normal semiconductor technique, and the uppermost portion is flattened, and then the lower passivation film is formed. After the MEMS sensor portion is formed on the lower passivation film, an upper passivation film including the MEMS portion and the circuit portion is further formed to cover the whole. That is, the MEMS sensor unit is sealed with the upper and lower passivation films. As a result, even if a pinhole is generated in the upper passivation film at the stepped portion, the lower passivation film is directly under the pinhole, and the risk of impairing reliability can be avoided.

本願発明の諸形態を整理し列挙すれば、次の通りである。   The various aspects of the present invention are summarized and listed as follows.

本発明の基本形態は、半導体集積回路の上部に、空洞部を有するＭＥＭＳ（Ｍｉｃｒｏ Ｅｌｅｃｔｒｏ Ｍｅｃｈａｎｉｃａｌ Ｓｙｓｔｅｍ）センサが搭載された半導体装置であって、少なくとも、前記半導体集積回路上に第１のパッシベーション膜を有し、前記第１のパッシベーション膜上に前記空洞部を有するＭＥＭＳセンサが搭載され、且つ、前記空洞部を有するＭＥＭＳセンサの少なくとも空洞部を覆って第２のパッシベーション膜を有する半導体装置である。   A basic form of the present invention is a semiconductor device in which a MEMS (Micro Electro Mechanical System) sensor having a hollow portion is mounted on an upper portion of a semiconductor integrated circuit, and at least a first passivation film is provided on the semiconductor integrated circuit. And a semiconductor device having a second passivation film covering at least the cavity of the MEMS sensor having the cavity, wherein the MEMS sensor having the cavity is mounted on the first passivation film.

前記第１と第２のパッシベーション膜の双方が、前記空洞部を有するＭＥＭＳセンサの空洞部の端部で接触し、前記空洞部を有するＭＥＭＳセンサを封止した構造が有用である。こうした構造をとることで、ＭＥＭＳセンサ部をパッシベーション膜で密封した構造となる。又、前記半導体集積回路の表面に対して、前記空洞部の上下に第１及び第２の電極が配置されて、変形可能なコンデンサを構成している。   A structure in which both the first and second passivation films are in contact with each other at the end of the cavity of the MEMS sensor having the cavity and the MEMS sensor having the cavity is sealed is useful. By adopting such a structure, the MEMS sensor portion is sealed with a passivation film. The first and second electrodes are arranged above and below the cavity with respect to the surface of the semiconductor integrated circuit to constitute a deformable capacitor.

更に、本発明の別な形態によれば、前記空洞部の下部に配置される第１のパッシベーション膜の膜厚が、前記空洞部の上部に配置される第２のパッシベーション膜の膜厚より厚い前記半導体装置が滋養的に好ましい。   Furthermore, according to another embodiment of the present invention, the film thickness of the first passivation film disposed below the cavity is thicker than the film thickness of the second passivation film disposed above the cavity. The semiconductor device is nutritionally preferable.

尚、前記第１及び第２のパッシベーション膜が、窒化シリコン膜であることが、実際的である。   It is practical that the first and second passivation films are silicon nitride films.

更に、前記空洞部の、前記半導体回路の基板表面と平行な位置に中間電極を設け、例えば、加速度による小さな力をも検知することが出来るようにすることが出来る。   Furthermore, an intermediate electrode can be provided at a position parallel to the substrate surface of the semiconductor circuit in the hollow portion, and for example, a small force due to acceleration can be detected.

本発明によれば、高い信頼性を持ったセンサを実現することが出来る。これは、本発明の構造が、ＭＥＭＳセンサ部をパッシベーション膜で密封した構造をとることによる。更に、本発明の別な形態によれば、前記密封構造と同時に、ＭＥＭＳセンサ部の動作を阻害しない構造になることにより、より高い信頼性を持ったセンサを実現することが出来る   According to the present invention, a highly reliable sensor can be realized. This is because the structure of the present invention has a structure in which the MEMS sensor portion is sealed with a passivation film. Furthermore, according to another aspect of the present invention, a sensor with higher reliability can be realized by having a structure that does not hinder the operation of the MEMS sensor unit simultaneously with the sealing structure.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。尚、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

＜実施例１＞
実施例１では、半導体集積回路の配線層上に形成した静電容量式ＭＥＭＳ圧力センサについて説明する。図１はその断面図である。図１に示す圧力センサは、半導体基板に形成された集積回路配線層の表面に下部パッシベーション膜層６を設け、その上層に下部電極層７、上部電極層９から成る静電容量を形成した断面図である。下部電極層７と上部電極層２の間の空洞１２は、封止絶縁膜層１０と、上部パッシベーション膜１１によって封止されている。空洞１２を設けることで、外部圧力によって上部電極層９が変形し、上部電極層２と下部電極層７の間に存在する静電容量が変化する。つまり、圧力により静電容量が変化する可変容量コンデンサを形成しており、この容量値の変化を検出することで圧力センサとして使用する。尚、半導体集積回路部は、通例の半導体装置の構成を有し、図では、拡散層２、ゲート電極４、配線３、層間絶縁膜５、及び酸化物層１４などを示した。符号８は犠牲層間絶縁膜で、プラズマＣＶＤ法による、いわゆるＴＥＯＳ膜もしくはＳｉＯ２などが用いられる。尚、半導体集積回路の部分の構成は、通例の半導体集積回路のそれを採用して十分であるので、その詳細説明は省略する。 <Example 1>
In Example 1, a capacitive MEMS pressure sensor formed on a wiring layer of a semiconductor integrated circuit will be described. FIG. 1 is a sectional view thereof. The pressure sensor shown in FIG. 1 is a cross-section in which a lower passivation film layer 6 is provided on the surface of an integrated circuit wiring layer formed on a semiconductor substrate, and a capacitance composed of a lower electrode layer 7 and an upper electrode layer 9 is formed thereon. FIG. A cavity 12 between the lower electrode layer 7 and the upper electrode layer 2 is sealed with a sealing insulating film layer 10 and an upper passivation film 11. By providing the cavity 12, the upper electrode layer 9 is deformed by an external pressure, and the capacitance existing between the upper electrode layer 2 and the lower electrode layer 7 changes. That is, a variable capacitor whose capacitance changes with pressure is formed, and is used as a pressure sensor by detecting this change in capacitance value. The semiconductor integrated circuit section has a configuration of a usual semiconductor device. In the figure, the diffusion layer 2, the gate electrode 4, the wiring 3, the interlayer insulating film 5, the oxide layer 14, and the like are shown. Reference numeral 8 denotes a sacrificial interlayer insulating film, which is a so-called TEOS film or SiO 2 formed by plasma CVD. Note that the configuration of the semiconductor integrated circuit portion is sufficient to adopt that of a conventional semiconductor integrated circuit, and therefore detailed description thereof is omitted.

以下、図１及び図２より図１１を用いて、静電容量式圧力センサを形成するプロセスについて述べる。   Hereinafter, a process for forming a capacitive pressure sensor will be described with reference to FIGS. 1 and 2 to 11.

まず、通常の半導体プロセス技術により、集積回路をＳｉ基板（１）上に形成する。集積回路配線層を形成した後、表面をＣＭＰ（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ）工程により平坦化する。平坦化後、下部パッシベーション膜層６を２００ｎｍ程度成膜する(図２)。このパッシベーション膜としては、通常半導体集積回路でパッシベーション膜として用いられ、耐湿性・耐薬品性に優れる窒化シリコン膜が適当であると考えられる。もちろん、耐湿性・耐薬品性が強い、炭化シリコンや酸化アルミ等の他の絶縁膜でも良い。尚、図での符号を付していない部分は図１のそれと同様である。   First, an integrated circuit is formed on a Si substrate (1) by a normal semiconductor process technique. After the integrated circuit wiring layer is formed, the surface is planarized by a CMP (Chemical Mechanical Polishing) process. After planarization, a lower passivation film layer 6 is formed to a thickness of about 200 nm (FIG. 2). As this passivation film, a silicon nitride film which is usually used as a passivation film in a semiconductor integrated circuit and is excellent in moisture resistance and chemical resistance is considered appropriate. Of course, other insulating films such as silicon carbide and aluminum oxide which have high moisture resistance and chemical resistance may be used. The parts not denoted by the reference numerals in the figure are the same as those in FIG.

次に、配線層へのコンタクトホール２０を加工してから、下部電極層７を５０ｎｍ程度の厚さで成膜・加工する(図３)。下部電極層７は、通常半導体プロセスの配線層で用いることができる金属であれば良く、アルミ、タングステン、珪化タングステン、チタン、窒化チタン、モリブデン等を用いる。   Next, after processing the contact hole 20 to the wiring layer, the lower electrode layer 7 is formed and processed to a thickness of about 50 nm (FIG. 3). The lower electrode layer 7 may be any metal that can be used in a wiring layer of a normal semiconductor process, and aluminum, tungsten, tungsten silicide, titanium, titanium nitride, molybdenum, or the like is used.

この上部に、犠牲層絶縁膜８を５００ｎｍ程度の厚さで成膜・加工する(図４)。犠牲絶縁膜層８は、通常の半導体工程で用いられる層間絶縁膜を用いる。   On top of this, a sacrificial layer insulating film 8 is formed and processed to a thickness of about 500 nm (FIG. 4). As the sacrificial insulating film layer 8, an interlayer insulating film used in a normal semiconductor process is used.

次に、上部電極層９を５００ｎｍ程度の厚さで成膜する(図５)。上部電極層９は、通常半導体プロセスの配線層で用いる事ができる金属で、かつ、耐湿性・耐薬品性が高いタングステン、もしくは珪化タングステン等の金属を用いるのが好ましい。加えて、その内部応力が、大きさ５００ＭＰａ程度の引っ張り応力を持つように成膜するのが良い。それは空洞を有するセンサ部分が十分機能するように為、引っ張り応力である必要がある。   Next, the upper electrode layer 9 is formed with a thickness of about 500 nm (FIG. 5). The upper electrode layer 9 is preferably a metal that can be used in a wiring layer of a normal semiconductor process, and a metal such as tungsten or tungsten silicide having high moisture resistance and chemical resistance. In addition, it is preferable to form a film so that the internal stress has a tensile stress of about 500 MPa. It must be a tensile stress in order for the sensor part with the cavity to function well.

この上部電極層９に対し、直径２００ｎｍ程度の微小穴２１を開口する(図６)。次に、この微小穴２１から等方的なエッチングを行い、空洞１２を形成する(図７)。この等方的なエッチングには、フッ酸等の薬液や蒸気を用いたエッチングを用いる。適当な時間、エッチングすることで、空洞１２を所望の大きさで形成できる。   A minute hole 21 having a diameter of about 200 nm is opened in the upper electrode layer 9 (FIG. 6). Next, isotropic etching is performed from the minute hole 21 to form the cavity 12 (FIG. 7). For this isotropic etching, etching using a chemical solution such as hydrofluoric acid or steam is used. By etching for an appropriate time, the cavity 12 can be formed in a desired size.

次に、層間絶縁膜材料からなる封止絶縁膜１０を３００ｎｍ程度成膜し、空洞１２を完全に封止する(図８)。これには、常圧ＣＶＤ技術などの被膜性の高い成膜技術を用いる。被膜性の良い成膜方法を用いることで、空洞内が埋まる前に微小穴が塞がり、空洞内に空間を残すことができる。   Next, a sealing insulating film 10 made of an interlayer insulating film material is formed to a thickness of about 300 nm, and the cavity 12 is completely sealed (FIG. 8). For this, a film forming technique having a high film property such as an atmospheric pressure CVD technique is used. By using a film forming method with good film properties, the microhole is closed before the cavity is filled, and a space can be left in the cavity.

こうした上部電極層９と封止絶縁膜１０を、所望形状に加工する(図９)。最後に、１５０ｎｍ程度の上部パッシベーション膜１１で全体を覆う（図１）。この上部パッシベーション膜１１も、下部パッシベーション膜６と同様に、窒化シリコン等の耐湿性・耐薬品性が高い膜を用いる。但し、空洞部１２の形状に影響を与えるため、内部応力は０以上から２００ＭＰａ程度の引っ張り応力を持っていることが望ましい。前述したように、空洞を有するセンサ部分が十分機能するように為、封止絶縁膜１０及び上部パッシベーション膜１１のトータルで引っ張り応力の状態になっていることが必要である。又、上部パッシベーション膜１１は、十分な耐湿性を確保し、且つ、上部電極層９の変形を妨げない厚さでなければならないので、１５０ｎｍ〜２００ｎｍ程度の厚さで成膜する(図１)。パッシベーション膜として機能するに、通例１５０ｎｍ程度は必要であり、一方、余り厚くすると、空洞を有するセンサ部分の機能が阻害されるおそれが生ずる。上部パッシベーション膜１１あるいは下部の封止絶縁膜１０、上部電極層９などの材料、構造などにも依存するが、一般的には５００ｎｍ程度が上限であろう。   The upper electrode layer 9 and the sealing insulating film 10 are processed into a desired shape (FIG. 9). Finally, the whole is covered with an upper passivation film 11 of about 150 nm (FIG. 1). Similarly to the lower passivation film 6, the upper passivation film 11 is a film having high moisture resistance and chemical resistance such as silicon nitride. However, in order to affect the shape of the cavity 12, it is desirable that the internal stress has a tensile stress of 0 to 200 MPa. As described above, it is necessary that the sealing insulating film 10 and the upper passivation film 11 are in a state of tensile stress in total so that the sensor portion having the cavity functions sufficiently. Further, since the upper passivation film 11 must have a thickness that ensures sufficient moisture resistance and does not hinder the deformation of the upper electrode layer 9, it is formed with a thickness of about 150 nm to 200 nm (FIG. 1). . In order to function as a passivation film, typically about 150 nm is necessary. On the other hand, if it is too thick, the function of the sensor part having a cavity may be hindered. Although it depends on the material and structure of the upper passivation film 11 or the lower sealing insulating film 10 and the upper electrode layer 9, the upper limit is generally about 500 nm.

しかしながら、このように薄い膜をパッシベーションとして用いた場合、段差部での上部パッシベーション膜（１１）に隙間２２が発生、信頼性を損なう恐れがある。この状態の例を図１０に示す。図は、例えば、図１の左側の円で囲まれた領域を模式的に拡大して示したものである。しかし、本発明によれば、段差部には下部パッシベーション膜６があるため、装置の信頼性を損なう恐れが小さく、且つ、上部パッシベーション膜１１は最低限の厚さで済む。又、空洞１２が存在する領域以外は、上部パッシベーション膜１１と下部パッシベーション膜６が二重に保護する形となり、半導体集積回路装置領域にも十分な信頼性を確保することができる。   However, when such a thin film is used for passivation, a gap 22 is generated in the upper passivation film (11) at the stepped portion, which may impair reliability. An example of this state is shown in FIG. The figure schematically shows, for example, an enlarged area surrounded by a circle on the left side of FIG. However, according to the present invention, since there is the lower passivation film 6 in the step portion, there is little risk of impairing the reliability of the device, and the upper passivation film 11 can be of a minimum thickness. Further, except for the region where the cavity 12 exists, the upper passivation film 11 and the lower passivation film 6 are double-protected, and sufficient reliability can be ensured also in the semiconductor integrated circuit device region.

＜実施例２＞
実施例２では、圧力センサ以外の用途で、空洞を持つ構造への適用例を述べる。
本実施例は、半導体集積回路の配線層上に形成した静電容量式ＭＥＭＳ加速度センサである。図１１はその断面図である。実施例１と同様に、図１１に示す加速度センサは、可動電極層１３を設け、これが小さな力でも変形するように設計しておく。本例では、こうすることで、加速度が印加された時に、可動電極層１３の位置が変動するのを利用する。
本例の構造は次のような工程で製造される。即ち、集積回路配線３まで作製した半導体集積回路基板１の表面を平坦化した後に、下部パッシベーション膜層６を設け、その上層に下部電極層７と上部電極層９を設ける。この下部電極層７と上部電極層９の間に可動電極層１３を設けた構造である。この可動電極層１３は、前記犠牲絶縁膜を設ける際、一旦、可動電極層１３を設ける位置まで、第１の犠牲絶縁膜８−１を形成し、この上部に可動電極層１３を形成する。そして、この上部に第２の犠牲絶縁膜８−２を形成する。その後の製造工程はこれまでの例と同様に行うことが出来る。上部電極層９に微小穴２１を開口し、この微小穴２１から等方的なエッチングによって空洞１２を形成することも、これまでの例と同様である。 <Example 2>
In the second embodiment, an application example to a structure having a cavity for an application other than the pressure sensor will be described.
This embodiment is a capacitive MEMS acceleration sensor formed on a wiring layer of a semiconductor integrated circuit. FIG. 11 is a sectional view thereof. Similar to the first embodiment, the acceleration sensor shown in FIG. 11 is provided with a movable electrode layer 13 which is designed to be deformed even with a small force. In this example, this makes use of the fact that the position of the movable electrode layer 13 varies when acceleration is applied.
The structure of this example is manufactured by the following process. That is, after planarizing the surface of the semiconductor integrated circuit substrate 1 manufactured up to the integrated circuit wiring 3, the lower passivation film layer 6 is provided, and the lower electrode layer 7 and the upper electrode layer 9 are provided thereon. The movable electrode layer 13 is provided between the lower electrode layer 7 and the upper electrode layer 9. When the sacrificial insulating film is provided on the movable electrode layer 13, the first sacrificial insulating film 8-1 is once formed up to the position where the movable electrode layer 13 is provided, and the movable electrode layer 13 is formed thereon. Then, a second sacrificial insulating film 8-2 is formed on the upper portion. Subsequent manufacturing steps can be performed in the same manner as in the previous examples. Opening the minute hole 21 in the upper electrode layer 9 and forming the cavity 12 from the minute hole 21 by isotropic etching are the same as in the previous examples.

可動電極層１３を小さな力でも変形するように設計しておくことで、加速度が印加された時に、可動電極層の位置が変動するようにでき、加速度を印加した際の、下部電極層７もしくは上部電極層９との間に生じている静電容量変化を検出して加速度センサとする。又、下部電極層７と可動電極層１３の間の空洞１２は、実施例１と同様に封止絶縁膜１０と、上部パッシベーション膜１１によって封止されているため、可動部が、外部の粉塵により動作不良を起こす恐れが無い。尚、図１１の稼動部以外の構成は基本的に図１のそれと同様である。   By designing the movable electrode layer 13 so as to be deformed even with a small force, the position of the movable electrode layer can be changed when an acceleration is applied. When the acceleration is applied, the lower electrode layer 7 or A change in capacitance generated between the upper electrode layer 9 is detected to obtain an acceleration sensor. Further, since the cavity 12 between the lower electrode layer 7 and the movable electrode layer 13 is sealed by the sealing insulating film 10 and the upper passivation film 11 as in the first embodiment, the movable portion is made of external dust. There is no risk of malfunction. 11 is basically the same as that of FIG. 1 except for the operating unit.

本実施例においても、実施例１と同様に、段差形状を持つ部位に対する上部パッシベーションはピンホールを発生する恐れがあるが、段差部位の下部には、下部パッシベーション膜があるため、装置の信頼性を損なう恐れが小さい。   Also in the present embodiment, as in the first embodiment, the upper passivation with respect to the portion having the step shape may cause a pinhole. However, since the lower passivation film is present under the step portion, the reliability of the apparatus is increased. There is little risk of damage.

尚、実施例はＭＥＭＳ圧力センサおよびＭＥＭＳ加速度センサを例に記載したが、本発明におけるパッシベーション方法は空洞形状を有する、他のＭＥＭＳ構造体にも利用可能である。   In addition, although the Example described the MEMS pressure sensor and the MEMS acceleration sensor as an example, the passivation method in the present invention can be used for other MEMS structures having a hollow shape.

このように、本発明は、空洞を利用したセンサにおいて、高い信頼性を必要とするセンサに幅広く利用されるものである。   As described above, the present invention is widely used for sensors that require high reliability in sensors that use cavities.

本発明の一実施の形態における圧力センサの模式的な断面図である。It is typical sectional drawing of the pressure sensor in one embodiment of this invention. 本発明の一実施の形態における圧力センサの製造工程順に示した装置の断面図である。It is sectional drawing of the apparatus shown to the manufacturing process order of the pressure sensor in one embodiment of this invention. 本発明の一実施の形態における圧力センサの製造工程順に示した装置の断面図である。It is sectional drawing of the apparatus shown to the manufacturing process order of the pressure sensor in one embodiment of this invention. 本発明の一実施の形態における圧力センサの製造工程順に示した装置の断面図である。It is sectional drawing of the apparatus shown to the manufacturing process order of the pressure sensor in one embodiment of this invention. 本発明の一実施の形態における圧力センサの製造工程順に示した装置の断面図である。It is sectional drawing of the apparatus shown to the manufacturing process order of the pressure sensor in one embodiment of this invention. 本発明の一実施の形態における圧力センサの製造工程順に示した装置の断面図である。It is sectional drawing of the apparatus shown to the manufacturing process order of the pressure sensor in one embodiment of this invention. 本発明の一実施の形態における圧力センサの製造工程順に示した装置の断面図である。It is sectional drawing of the apparatus shown to the manufacturing process order of the pressure sensor in one embodiment of this invention. 本発明の一実施の形態における圧力センサの製造工程順に示した装置の断面図である。It is sectional drawing of the apparatus shown to the manufacturing process order of the pressure sensor in one embodiment of this invention. 本発明の一実施の形態における圧力センサの製造工程順に示した装置の断面図である。It is sectional drawing of the apparatus shown to the manufacturing process order of the pressure sensor in one embodiment of this invention. 本発明の一実施の形態における段差部位に対するパッシベーション膜形状の例である。It is an example of the passivation film shape with respect to the level | step difference site | part in one embodiment of this invention. 本発明の他の実施の形態における加速度センサの模式的な断面図である。It is typical sectional drawing of the acceleration sensor in other embodiment of this invention.

符号の説明Explanation of symbols

１：シリコン基板、２：拡散層、３：配線、４ ：ゲート電極、５：層間絶縁膜、６：下部パッシベーション層、７：下部電極層、８：犠牲層間絶縁膜、９：上部電極層、１０：封止絶縁膜層、１１：上部パッシベーション層、１２：空洞、１３：可動電極層、１４：酸化物層、２０：コンタクトホール、２１：微小穴、２２：間隙。 1: silicon substrate, 2: diffusion layer, 3: wiring, 4: gate electrode, 5: interlayer insulating film, 6: lower passivation layer, 7: lower electrode layer, 8: sacrificial interlayer insulating film, 9: upper electrode layer, 10: sealing insulating film layer, 11: upper passivation layer, 12: cavity, 13: movable electrode layer, 14: oxide layer, 20: contact hole, 21: minute hole, 22: gap.

Claims (8)

半導体集積回路の上部に、空洞部を有するＭＥＭＳ（Ｍｉｃｒｏ Ｅｌｅｃｔｒｏ Ｍｅｃｈａｎｉｃａｌ Ｓｙｓｔｅｍ）センサが搭載された半導体装置であって、少なくとも、前記半導体集積回路上に第１のパッシベーション膜を有し、前記第１のパッシベーション膜上に前記空洞部を有するＭＥＭＳセンサが搭載され、且つ、前記空洞部を有するＭＥＭＳセンサの少なくとも空洞部を覆って第２のパッシベーション膜を有することを特徴とする半導体装置。 A semiconductor device in which a MEMS (Micro Electro Mechanical System) sensor having a hollow portion is mounted on an upper portion of a semiconductor integrated circuit, the semiconductor device including at least a first passivation film on the semiconductor integrated circuit, A semiconductor device comprising: a MEMS sensor having the cavity on the passivation film; and a second passivation film covering at least the cavity of the MEMS sensor having the cavity. 前記第１と第２のパッシベーション膜の双方が、前記空洞部を有するＭＥＭＳセンサの空洞部の端部で接触し、前記空洞部を有するＭＥＭＳセンサを封止した構造であることを特徴とする請求項１に記載の半導体装置。 Both the first and second passivation films are in contact with each other at the end of the cavity of the MEMS sensor having the cavity, and the MEMS sensor having the cavity is sealed. Item 14. The semiconductor device according to Item 1. 前記半導体集積回路の表面に対して、前記空洞部の上下に第１及び第２の電極が配置されて、変形可能なコンデンサを構成してなることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein a deformable capacitor is configured by arranging first and second electrodes above and below the cavity with respect to a surface of the semiconductor integrated circuit. . 前記空洞部の下部に配置される第１のパッシベーション膜の膜厚が、前記空洞部の上部に配置される第２のパッシベーション膜の膜厚より厚いことを特徴とする請求項１に記載の半導体装置。 2. The semiconductor according to claim 1, wherein the thickness of the first passivation film disposed below the cavity is greater than the thickness of the second passivation film disposed above the cavity. apparatus. 前記空洞部の下部に配置される第１のパッシベーション膜の膜厚が、前記空洞部の上部に配置される第２のパッシベーション膜の膜厚より厚いことを特徴とする請求項２に記載の半導体装置。 3. The semiconductor according to claim 2, wherein the thickness of the first passivation film disposed below the cavity is greater than the thickness of the second passivation film disposed above the cavity. apparatus. 前記第１及び第２のパッシベーション膜が、窒化シリコン膜であることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first and second passivation films are silicon nitride films. 前記第１及び第２のパッシベーション膜が、窒化シリコン膜であることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first and second passivation films are silicon nitride films. 前記空洞部の、前記半導体回路の基板表面と平行な位置に中間電極を、更に有することを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, further comprising an intermediate electrode at a position parallel to the substrate surface of the semiconductor circuit in the cavity.
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