JPH1065167A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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Publication number
JPH1065167A
JPH1065167A JP2939597A JP2939597A JPH1065167A JP H1065167 A JPH1065167 A JP H1065167A JP 2939597 A JP2939597 A JP 2939597A JP 2939597 A JP2939597 A JP 2939597A JP H1065167 A JPH1065167 A JP H1065167A
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JP
Japan
Prior art keywords
insulating film
layer
semiconductor device
formed
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2939597A
Other languages
Japanese (ja)
Inventor
Masatoshi Arai
Kouji Eriguchi
Bunji Mizuno
Michihiko Takase
文二 水野
浩二 江利口
雅利 荒井
道彦 高瀬
Original Assignee
Matsushita Electric Ind Co Ltd
松下電器産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2497996 priority Critical
Priority to JP8-24979 priority
Priority to JP8-149004 priority
Priority to JP14900496 priority
Application filed by Matsushita Electric Ind Co Ltd, 松下電器産業株式会社 filed Critical Matsushita Electric Ind Co Ltd
Priority to JP2939597A priority patent/JPH1065167A/en
Publication of JPH1065167A publication Critical patent/JPH1065167A/en
Withdrawn legal-status Critical Current

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Abstract

(57) [Problem] To improve the reliability of an insulating layer by preventing formation of a damaged layer in the insulating layer when doping impurities. SOLUTION: After performing a doping step, portions of the insulating layers 6, 23, 32, 43, 53 doped with impurities and / or the insulating layers 6, 23, 32, 4 passed through the impurities.
Before removing at least a part of the portions 3 and 53 or performing the doping process, the portions of the insulating layers 6, 23, 32, 43 and 53, which are expected to be doped with impurities, and / or the impurities pass therethrough. The insulating layer 6, which is predicted to
By removing at least a part of the portions 23, 32, 43, and 53 in advance, physical damage is prevented from being generated, and the reliability of the insulating layers 6, 23, 32, 43, and 53 is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a step of forming a conductive layer or a layer to be a conductive layer on a semiconductor substrate through an insulating layer, and a step of doping the semiconductor substrate with impurities after the step. The present invention relates to a semiconductor device manufacturing method including the same, and a semiconductor device.

[0002]

2. Description of the Related Art Generally, in the production of semiconductor devices such as MOS transistors and MOS capacitors,
After a conductive layer or a layer to be a conductive layer is formed over a semiconductor substrate with an insulating layer interposed therebetween, an impurity is doped into a surface of the semiconductor substrate. Doping impurities on the semiconductor substrate surface
On a semiconductor substrate, a source / drain region or an LDD (Light
This is for shaping the region (in the case of a MOS transistor) or imparting conductivity to the layer to be the conductive layer (in the case of a MOS capacitor).

A conventional example of such a semiconductor device manufacturing method will be described with reference to the drawings. 20 are cross-sectional views each showing a manufacturing process of a conventional MOS transistor. Here, a P-well region 71, an LDD
P having region 72 and source / drain region 73
A gate insulating film 74, a gate electrode 75, and sidewalls 76 are formed on the surface of
Description will be made using an OS transistor as an example.

First, as shown in FIG. 20A, a gate electrode 75 made of polysilicon or the like is patterned on a P-type silicon substrate 70 on which a P-well region 71 and a gate insulating film 74 are formed. Next, as shown in FIG. 20B, the first ion implantation of As ions is performed under the conditions of an acceleration energy of 3 KeV and a dose of 3 × 10 13 atoms / Cm 2 to form an LDD region 72. And FIG.
As shown in (c), HTO (High Temperature Oxida
The sidewalls 76 are formed by depositing a 100 nm layer and etching back. Further, FIG.
As shown in (d), As ions are accelerated with an acceleration energy of 30.
2 under the conditions of keV and a dose of 3 × 10 15 atoms / Cm 2.
A second ion implantation is performed to form source / drain regions 73. At this time, since the LDD region 72 is covered with the sidewall 76, the impurity concentration does not increase and the LDD region 72 is not assimilated to the source / drain region 73.

[0005] Through these steps, the LDD
A semiconductor device (MOS transistor) including the region 72 is manufactured. Note that the LDD region 72 prevents hot carriers from being generated due to relaxation of the drain electric field, and further prevents the source / drain region 73 from diffusing and extending below the gate electrode 75 due to a heat diffusion step to be performed later. It is provided in.

[0006]

In the conventional method of manufacturing a semiconductor device, as the miniaturization and the improvement of the characteristics of the semiconductor device further progress in the future, the gate insulating film 74 in the ion implantation step will be increased.
However, there is a problem that the device characteristics are deteriorated due to the formation of a damaged layer.

Hereinafter, the reason will be described.

When the implanted ions directly enter or pass through in the ion implantation process, the gate insulating film 74 is not only damaged physically but also deteriorates in characteristics, and eventually causes dielectric breakdown. Such characteristic deterioration
Bonds between silicon and oxygen may be broken by implanted ions that have entered the gate insulating film 74, or the gate insulating film 7
It is considered that this occurs because a level is formed in 4 and holes and electrons are trapped at the formed level.

Such a decrease in insulation and reliability also occurs when a capacitor (MOS capacitor) is formed on a semiconductor substrate. That is, generally, a conductive layer such as a well region formed on a semiconductor substrate is used as a lower capacitor electrode, an insulating film selectively formed on the lower capacitor electrode is used as a capacitor insulating film, and an upper layer is formed on the capacitor insulating film. 2. Description of the Related Art A capacitor is formed on a semiconductor substrate by forming a capacitor electrode. In a capacitor having such a structure, the upper capacitor electrode is made of polysilicon into which high-concentration impurities are implanted.

However, in order to use polysilicon as an upper capacitor electrode, an impurity must be added
It is necessary to implant impurities larger than 14 atoms / Cm 2 . Therefore, it has been pointed out that when such a large amount of impurities are implanted, a damage layer is formed in the capacitor insulating film due to the same reason as described above.

It is pointed out that the formation of such a damaged layer on the gate insulating film or the capacitor insulating film is closely related not only to the increase in the amount of ion implantation but also to the thickness of these insulating films. . That is, the thickness of the gate insulating film and the capacitance insulating film has been reduced in response to a demand for higher integration of the semiconductor device, and recently, an insulating film having a thickness of 5 nm or less is being manufactured. Naturally, such an insulating film having a great influence on the ion implantation has a large effect.
Even if impurity ions are implanted with a relatively small ion implantation amount of 14 atoms / cm 2 or less, a damaged layer may be formed in the insulating film.

In view of the above problems, the present invention prevents the formation of a damaged layer by ion implantation in an insulating film formed on a semiconductor substrate, and prevents the generation of hot carriers, thereby improving the reliability of a semiconductor device. The purpose is to increase.

[0013]

In order to solve the above-mentioned problems, a semiconductor device and a method of manufacturing the same according to the present invention have the following features.

A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the following steps.

Forming an insulating layer on the semiconductor substrate forming a conductive layer on the insulating layer patterning the conductive layer doping impurities into at least one of the semiconductor substrate and the conductive layer under the conductive layer This configuration removes at least a part of the portion of the insulating layer that is doped or passed with the impurity. With this configuration, the insulating layer that has been physically damaged can be removed, and the reliability of the insulating layer can be reduced. Will increase.

A method of manufacturing a semiconductor device according to another embodiment of the present invention includes the following steps.

Forming an insulating layer on the semiconductor substrate, forming a conductive layer on the insulating layer, patterning the conductive layer, wherein the insulating layer is located below the conductive layer, and is doped with impurities in a later step. Removing at least a part of the portion which is passed or passed through the semiconductor substrate or the conductor layer is doped with an impurity. With this configuration, the insulating layer at a portion where physical damage is expected to occur due to the impurity doping is removed. By removing in advance, physical damage does not remain on the insulating layer, and the reliability of the insulating layer is increased.

A method of manufacturing a semiconductor device according to still another embodiment of the present invention includes the following steps. Forming a second conductor layer in or on a semiconductor substrate, forming an insulation layer on the first conductor layer, forming a second conductor layer on the insulation layer, patterning the second conductor layer, Wherein the semiconductor layer or at least one of the-and the second conductor layer is doped with impurities, the exclusionary layer located under the-first conductor layer,
A method of manufacturing a semiconductor device according to another embodiment of the present invention includes the following steps.

Forming a second conductive layer in or on the semiconductor substrate forming an insulating layer on the first conductive layer forming a second conductive layer on the insulating layer; The insulating layer located below the-conductor layer to be patterned,
Removing at least a part of a portion where impurities are doped or pass through in a later step; doping impurities into at least one of the semiconductor substrate and the first and second conductor layers; a semiconductor device according to an embodiment of the present invention. Includes the following configuration.

A semiconductor substrate, a first insulating film thermally formed on the semiconductor substrate, a gate electrode formed on the first insulating film, and a gate electrode formed on the semiconductor substrate; A source / drain region, and a side end of the second insulating film is located inside a side end of the gate electrode facing the source / drain region.

A semiconductor device according to another embodiment of the present invention further includes the following configuration.

A second insulating film formed in contact with a side surface of the gate electrode and a side end of the first insulating film. The semiconductor device according to still another embodiment of the present invention has the following features.

The second insulating film is made of a material having a higher dielectric constant than the first insulating film.

A semiconductor device according to still another embodiment of the present invention further includes the following configuration.

A third insulating film formed on the second insulating film The semiconductor device according to still another embodiment of the present invention has the following features.

The dielectric constant of the third insulating film is substantially the same as that of the first insulating film.

A semiconductor device according to still another embodiment of the present invention further includes the following configuration.

A second insulating film formed below the vicinity of the side edge of the gate electrode The semiconductor device according to still another embodiment of the present invention has the following features.

The second insulating film is made of a material having a higher dielectric constant than the first insulating film.

A semiconductor device according to still another embodiment of the present invention has the following features.

The first insulating film is thermally grown, and the second insulating film is chemically grown.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a process sectional view of a method of manufacturing a semiconductor device according to a first embodiment of the present invention. Here, a MOS transistor having a source / drain / extension structure is used. An example will be described. This MOS transistor is formed by forming a gate insulating film 6, a gate electrode 7, and a side wall 8 on a P-type silicon substrate 2 on which a P-well region 3, an extension region 4, and a source / drain region 5 are formed. .

Next, the manufacturing process of this MOS transistor will be described.

First, as shown in FIG. 1A, a gate electrode is formed on a P-type silicon substrate 2 on which a P well region 3 and a gate insulating film (a thermally grown silicon oxide film or the like) 6 are formed. (Polysilicon, etc.) 7 is patterned. The thickness of the gate insulating film is 2 to 8 nm, and the thickness of the gate electrode 7 is 200 to 400 nm. The gate length of the transistor in the figure is 500 nm or less. Next, FIG.
As shown in FIG. 2 , the first ion implantation is performed on the P-type silicon substrate 2 under the conditions of, for example, As ions as acceleration ions at an acceleration energy of 10 keV and a dose of 1 × 10 14 atoms / cm 2. An extension region 4 is formed on the mold silicon substrate 2. The extension region 4 is formed in a relatively shallow region of the P-type silicon substrate 2 because it is formed by the first ion implantation step performed with a relatively small acceleration energy of 10 kev.

When such ion implantation is performed, the ion beam is not all perpendicular to the surface of the P-type silicon substrate 2, and some beam components are implanted obliquely. Furthermore, there is no structure for protecting the side edges of the gate insulating film 6 and the gate electrode 7 at the time of the first ion implantation. Under these conditions,
In addition, when the ion implantation is performed at a high dose of 1 × 10 14 atoms / cm 2 , the obliquely implanted ion beam is applied to the gate insulating film 6 located below the side end of the gate electrode 7.
The ion beam directly penetrates into the portion of the gate electrode 7 or enters the gate electrode 7 obliquely and penetrates through the gate electrode 7 to reach the gate insulating film 6. Therefore, as shown in FIG. 2, the gate insulating film 6 located below the side end of the gate electrode 7 is physically damaged by the rushed or passed impurity (As) ions, and the damaged layer 9 is formed there. Is done. In FIG. 2, for the sake of illustration, a clear boundary is drawn between the damage layer 9 and the gate insulating film 6, but in actuality, the vicinity of the exposed surface of the gate insulating film 6 is most physically damaged. And the physical damage gradually decreases toward the inside, so that the damage layer 9 is formed, and there is no clear boundary between the damage layer 9 and the gate insulating film 6. The damage layer 9 thus formed is
This not only deteriorates the characteristics of the OS transistor but also causes dielectric breakdown.

Then, as shown in FIG. 1C, the P-type silicon substrate 2 is immersed in a wet etching solution, for example, a 3% aqueous solution of hydrogen fluoride for 1 minute to perform wet etching, thereby forming the gate insulating film 6. Is selectively removed. The removal of the damaged layer 9 can be sufficiently prevented by removing the damaged layer 9 near the portion that is most physically damaged, that is, in the vicinity of the portion exposed below the side end of the gate electrode 7. Also,
Even if the damaged layer 9 is removed into a curved shape 10 (see FIG. 2) by wet etching, the characteristic deterioration can be sufficiently prevented, but the anisotropic etching may be performed to remove the damaged layer 9 in a rectangular shape. .

When the thickness of the gate insulating film is 2 to 8 nm,
From the side edge of the gate electrode 7 to the inside of about 5 to 20 nm,
It is desirable to remove the gate insulating film.

Thus, by wet etching,
If the damaged layer 9 formed on the gate insulating film 6 is removed, the gate insulating film 6 can be selectively etched without damaging the gate electrode 7 made of polysilicon or the like. Since the damaged portion of the gate insulating film 6 has a higher etch rate than the other portions, when the damaged portion is removed, the etch rate is lowered, so that the etching is performed in a so-called "self-stop" manner.

After removing the damaged layer 9 by wet etching, the P-type silicon substrate 2 is washed with water and dried.

After removing the damaged layer 9 in this manner, as shown in FIG. 1D, a silicon oxide film is deposited on the P-type silicon substrate 2 to a thickness of about 120 nm by a chemical vapor deposition method. Further, the side wall 8 is formed by etching back the silicon oxide film.

After forming the sidewalls 8, As ions are applied to the P-type silicon substrate 2 with an acceleration energy of 30.
A second ion implantation was performed under the conditions of keV and a dose of 3 × 10 15 atoms / cm 2 , and a source
The drain region 5 is formed. At this time, since the source / drain region 5 is formed by ion implantation with a relatively large acceleration energy of 30 keV, the source / drain region 5 is formed to a position deeper than the extension region 4.

At this time, the extension region 4 located at the side end of the gate electrode 7 and below the side end of the gate electrode 7 is protected by the sidewall 8, and is physically formed on the gate insulating film 6 by the second ion implantation. There is no damage. Furthermore, at the time of the second ion implantation, the extension region 4 in the vicinity of the gate insulating film 6 is protected by the sidewalls 8, so that the impurity concentration thereof does not increase excessively.

Through the above steps, a MOS transistor having a source / drain / extension structure is manufactured. In this MOS transistor, a damaged layer 9 formed on the gate insulating film 6 in a first ion implantation process performed to form the extension region 4 is performed.
Is removed by performing wet etching on the P-type silicon substrate 2, so that the gate insulating film 6 does not deteriorate in characteristics due to physical damage or dielectric breakdown.

Next, an experiment conducted to confirm the effect of the present invention will be described. Samples were made based on the above process.

<Experimental Conditions> Injection device: large current injection device: PI-9500 (manufactured by AMJ) Gate oxide film damage evaluation method: constant voltage TDDB test.

Injection conditions: BF 2 + , 40 (kev), 10 15 atoms / cm 2 Gate insulating film thickness: 8 nm Gate electrode film pressure: 330 nm Applied voltage: 10 V Capacitor area (size): 0.8 square microns < Experimental Results> FIG. 3 shows the results of a constant voltage TDDB test without ion implantation. The horizontal axis indicates time, and the vertical axis indicates the value of current flowing between the gate and the semiconductor substrate. Next, ion implantation is performed, and wet etching is performed for 0 second, 30 seconds.
FIGS. 4, 5, 6, and 7 show the results of the constant voltage TDDB test performed for 90 seconds and 120 seconds, respectively.

When the wet etching is not performed, the leakage current increases with the passage of time, and the dielectric breakdown occurs around 500 seconds. On the other hand, when the wet etching is performed for 30 seconds, almost no effect is seen. However, when the wet etching time is increased to 90 seconds or 120 seconds, the leak current is reduced, and the ion implantation is not performed. It's getting closer. When the etching time is 30 seconds, the gate insulating film is removed from the side edge of the gate electrode to the inside of about 5 nm. When the etching time is 90 seconds, the gate insulating film is removed from the side edge of the gate electrode to the inside of about 8 nm. When the etching time is 120 seconds, the gate insulating film is removed from the side edge of the gate electrode to the inside of about 10 nm.

When wet etching is not performed after the ion implantation, when the impurity is doped or passes through the gate insulating film 6 located below the end on the side of the gate electrode 7, a damage layer 9 is generated there. Increase, causing early dielectric breakdown. However, if the wet etching is performed for a predetermined time or more, the damaged layer 9 is removed, and the state of the gate insulating film 6 before the ion implantation is returned.
Therefore, according to the manufacturing process of the semiconductor device according to the present invention, it is possible to prevent the characteristic deterioration of the MOS transistor and prevent the dielectric breakdown of the gate insulating film 6.

Second Embodiment FIG. 8 is a process sectional view of a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Here, similarly to the first embodiment, the source / drain An explanation will be given by taking a MOS transistor having an extension structure as an example. This MO
The basic structure of the S transistor is the same as that of the first embodiment shown in FIG.
Are given. Unless otherwise specified, dimensions are the same.

Next, the manufacturing process of the MOS transistor will be described. First, as shown in FIG. 8A, a gate electrode 7 is pattern-formed on the P-type silicon substrate 2 on which the P-well region 3 and the gate insulating film 6 have been formed. Next, as shown in FIG. 8B, wet etching is performed by immersing the P-type silicon substrate 1 in a wet etching solution, for example, a 3% aqueous hydrogen fluoride solution for one minute. As a result, the impurity (A
The portion of the gate insulating film 7 which is predicted to suffer physical damage due to the entry or passage of s), specifically, the gate insulating film 6 located below the side end of the gate electrode 7 is removed. Removal of the parts that are predicted to receive physical damage will include the parts that are predicted to receive the most physical damage,
That is, if the gate insulating film 6 near the portion exposed below the side end of the gate electrode 7 is removed, the deterioration of the characteristics can be sufficiently prevented. When the thickness of the gate insulating film is 2 to 8 nm,
From the side edge of the gate electrode 7 to the inside of about 5 to 20 nm,
It is desirable to remove the gate insulating film 6. Further, even if the gate insulating film 6 is removed from the curved shape 10 as shown in FIG. 2 by wet etching, the characteristics can be sufficiently prevented from being deteriorated. However, the gate insulating film 6 is anisotropically etched to have a rectangular shape. May be removed. After performing the wet etching, the P-type silicon substrate 2 is washed with water and dried.

After the completion of the wet etching, FIG.
As shown in (c), the P-type silicon substrate 2
Acceleration energy of 10 kev and dose of 1 × 10 for s ions
The first ion implantation is performed under the condition of 14 atoms / cm 2 ,
An extension region 4 is formed. At this time, since the portion of the gate insulating film 6 which is expected to receive physical damage by the first ion implantation step has been removed in advance by wet etching, a damaged layer is formed on the gate insulating film 6. It will not be done.

After forming the extension region 4,
A 120 nm silicon oxide film is deposited on the P-type silicon substrate 2. Then, the sidewall 8 is formed by etching back the deposited silicon oxide film.

[0054] After forming the sidewalls 8, As ions acceleration energy 3Okev, performs second ion implantation at a dose of 3 × 10 15 atoms / cm 2, the source-drain in a P-type silicon substrate 2 Region 5 is formed. At this time, the side end of the gate electrode 7 and the gate electrode 7
The extension region 4 located below the side end is protected by the sidewall 8, and the second ion implantation does not cause physical damage to the gate insulating film 6.

Through the above steps, a MOS transistor having an extension structure is manufactured.
In this MOS transistor, a portion of the gate insulating film 6 which is expected to be physically damaged in the first ion implantation step performed to form the extension region 4 is set in advance before performing the first ion implantation. Since the P-type silicon substrate 2 is removed by performing wet etching, the gate insulating film 6 does not deteriorate in characteristics due to physical damage or breakdown.

Third Embodiment FIG. 9 is a process sectional view of a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Here, a MOS transistor having a single source / drain structure is taken as an example. This will be explained. This MOS transistor has a P-well region 21,
A gate insulating film 23 and a gate electrode 24 are formed in a P-type silicon substrate 20 on which a single source / drain 22 is formed. The dimensions are the same as in the previous embodiment, unless otherwise specified.

Next, the manufacturing process of this MOS transistor will be described. First, as shown in FIG. 9A, a P well region 21, a gate insulating film (such as a silicon oxide film) 2
A gate electrode (polysilicon, etc.) 24 is pattern-formed on the P-type silicon substrate 20 on which 3 is formed.

Next, as shown in FIG. 9B, As ions are implanted into the P-type silicon substrate 20 under the conditions of an acceleration energy of 10 kev and a dose of 3 × 10 15 atoms / cm 2. An injection is made, which results in P
A single source / drain region 22 is formed in the silicon substrate 20. Single source / drain region 22
Is formed in a relatively shallow region of the P-type silicon substrate 2 because it is formed by an ion implantation step performed with a relatively small acceleration energy of 10 keV.

In this step, due to the mechanism described above, physical damage occurs in the gate insulating film 23 located below the side end of the gate electrode 24, and a damaged layer 25 is formed.

Therefore, as shown in FIG. 9C, the P-type silicon substrate 20 is immersed in a wet etching solution, for example, a 3% aqueous solution of hydrogen fluoride for 1 minute to perform wet etching, and the gate insulating film 23 is formed. After selectively removing the formed damaged layer 25, the P-type silicon substrate 2
0 is washed with water and dried.

Through the above steps, a MOS transistor having a single source / drain structure 22 is manufactured. In this MOS transistor, the damage layer 25 formed on the gate insulating film 23 in the ion implantation step for forming the single source / drain region 22 is wet-etched on the P-type silicon substrate 20. Since the gate insulating film 23 is removed, the characteristics are not deteriorated by the physical damage and the dielectric breakdown is not caused.

Fourth Embodiment FIG. 10 is a sectional view showing the steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. MO with source / drain structure
Description will be made by taking an S transistor as an example. The basic structure of this MOS transistor is the same as that of the third embodiment shown in FIG. 9, and the same or similar parts are denoted by the same reference numerals.

Next, the manufacturing process of this MOS transistor will be described. First, as shown in FIG. 10A, a gate electrode 24 is patterned on a P-type silicon substrate 20 on which a P-well region 21 and a gate insulating film 23 have been formed. The dimensions are the same as in the previous embodiment, unless otherwise specified.

Next, as shown in FIG. 10B, wet etching is performed by immersing the P-type silicon substrate 20 in a wet etching solution, for example, a 3% aqueous solution of hydrogen fluoride for one minute. As a result, the portion of the gate insulating film 23 which is predicted to be physically damaged due to the intrusion or passage of the impurity (As) by the next ion implantation, specifically, below the side end of the gate electrode 24 The located gate insulating film 23 is removed. The removal of the portion expected to receive the physical damage is performed by removing the portion expected to receive the most physical damage, that is, the gate insulating film 6 near the portion exposed below the side end of the gate electrode 24. If this is the case, the characteristic deterioration can be sufficiently prevented. Gate insulating film 23
When the thickness is 2 to 8 nm, it is desirable to remove the gate insulating film 23 from the side edge of the gate electrode 24 to the inside of about 5 to 20 nm. After performing wet etching,
The P-type silicon substrate 20 is washed with water and dried.

After the wet etching is completed, FIG.
As shown in FIG. 1C, As ions are implanted into the P-type silicon substrate 20 at an acceleration energy of 10 keV and a dose of 3
Ion implantation is performed under the condition of × 10 15 atoms / cm 2 to form a single source / drain region 22. The single source / drain region 22 is formed in a relatively shallow region of the P-type silicon substrate 2 because it is formed by an ion implantation process performed with a relatively small acceleration energy of 10 kev. At this time, since the portion of the gate insulating film 23 which is predicted to be physically damaged by the ion implantation step is removed in advance by wet etching, no damage layer is formed on the gate insulating film 23.

By going through the above steps, a single
A MOS transistor having a source / drain structure is manufactured. In this MOS transistor, a portion of the gate insulating film 23, which is predicted to be physically damaged in the ion implantation process performed to form the single source / drain region 22, is subjected to P ion implantation before the ion implantation. The silicon substrate 20 is removed by performing wet etching, so that the characteristics of the gate insulating film 23 do not deteriorate due to physical damage and dielectric breakdown does not occur.

Fifth Embodiment FIG. 11 is a process sectional view of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention. Here, a MOS capacitor will be described as an example. This MOS capacitor
A capacitor insulating film 32 and a capacitor electrode 33 are sequentially formed on a P-type silicon substrate 30 having a P-well region 31 formed thereon. In this MOS capacitor, the other capacitor electrode facing the capacitor electrode 33 is a P-well region 31.
It is composed of The thickness of the capacitance insulating film 32 is about 6 n
m, the thickness of the capacitor electrode 33 is about 200 nm. The electrode area is determined based on the desired capacitance.

Next, the manufacturing process of this MOS capacitor will be described. First, as shown in FIG. 11A, a polysilicon pattern 330 is formed on a P-type silicon substrate 30 on which a P-well region 31 and a capacitance insulating film 32 have been formed. Next, as shown in FIG. 11B, in order to make the polysilicon pattern 330 conductive, As ions are applied to the surface of the P-type silicon substrate 30 at an acceleration energy of 1.
Ion implantation is performed under the conditions of 0 kev and a dose of 3 × 10 15 atoms / cm 2 . As a result, the polysilicon pattern 330
Has conductivity and functions as a capacitor electrode 33.

At this time, for the same reason as described in the previous embodiment, the capacitance insulating film 32 located below the side end of the capacitance electrode 33 is formed.
In this case, a damage layer 34 is formed due to physical damage.

Therefore, as shown in FIG. 11C, the P-type silicon substrate 30 is immersed in a wet etching solution, for example, a 3% aqueous solution of hydrogen fluoride for 1 minute to perform wet etching, and the capacitance insulating film 32 is formed. After selectively removing the formed damage layer 34, the P-type silicon substrate 3
0 is washed with water and dried.

Through the above steps, a MOS capacitor is manufactured. In this MOS capacitor, the damaged layer 34 formed in the capacitance insulating film 32 in the ion implantation step for imparting conductivity to the polysilicon pattern 330 is subjected to wet etching on the P-type silicon substrate 30. Since the capacitor insulating film 32 is removed, the characteristics of the capacitor insulating film 32 are not degraded due to physical damage or dielectric breakdown does not occur. When the thickness of the capacitor insulating film 32 is 2 to 8 nm, it is desirable to remove the capacitor insulating film 32 from the side end of the capacitor electrode 33 to the inside of about 5 to 20 nm.

Sixth Embodiment FIG. 12 is a sectional view showing a process of a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention. Here, the same MOS capacitor as that of the fifth embodiment is used. Will be described as an example.
The basic structure of this MOS capacitor is the same as that of the fifth embodiment shown in FIG. 11, and the same or similar parts are denoted by the same reference numerals.

Next, the manufacturing process of this MOS capacitor will be described. First, as shown in FIG. 12A, a polysilicon pattern 330 is formed on the P-type silicon substrate 30 on which the P-well region 31 and the capacitance insulating film 32 are formed. The dimensions are the same as in the previous embodiment, unless otherwise specified.

Next, as shown in FIG. 12B, wet etching is performed by immersing the P-type silicon substrate 30 in a wet etching solution, for example, a 3% aqueous solution of hydrogen fluoride for 1 minute. As a result, a portion of the capacitive insulating film 32, which is predicted to be physically damaged by the intrusion or passage of the impurity (As) by the next ion implantation, specifically, below the side end of the polysilicon pattern 330 Is removed. The removal of the portion expected to receive the physical damage is performed by removing the portion expected to receive the most physical damage, that is, the capacitance insulating film 32 near the portion exposed below the side end of the polysilicon pattern 330. By doing so, the deterioration of characteristics can be sufficiently prevented. After performing the wet etching, the P-type silicon substrate 30 is washed with water and dried.

After the wet etching is completed, FIG.
As shown in FIG. 2C, As ions are implanted into the P-type silicon substrate 30 at an acceleration energy of 10 keV and a dose of 3
Ions are implanted under the condition of × 10 15 atoms / cm 2 , and impurities (As) are implanted into the polysilicon pattern 330 so as to have conductivity and function as the capacitor electrode 33. At this time, there is no structure for protecting the side edges of the capacitor insulating film 32 and the capacitor electrode 33. Under such conditions, and 3 × 1
When ions are implanted at a high dose of 0 15 atoms / cm 2 , it is predicted that the implanted ion beam enters or passes through the capacitive insulating film 32 and is physically damaged. However, since the portion of the capacitor insulating film 32 which is predicted to be physically damaged has been removed in advance by wet etching, no gomage layer is formed on the capacitor insulating film 32.

Through the above steps, a MOS capacitor is manufactured. In this MOS capacitor, a portion of the capacitor insulating film 32, which is expected to be physically damaged by the ion implantation process performed to impart conductivity to the polysilicon pattern 330, is set in advance by P
Since the capacitive insulating film 32 is removed by wet etching performed on the mold silicon substrate 30, the characteristics are not degraded due to physical damage and dielectric breakdown does not occur. When the thickness of the capacitor insulating film 32 is 2 to 8 nm, it is desirable to remove the capacitor insulating film 32 from the side end of the capacitor electrode 33 to the inside of about 5 to 20 nm.

Seventh Embodiment FIG. 13 is a sectional view showing a method of manufacturing a semiconductor device according to a seventh embodiment of the present invention.
Similar to the embodiment, description will be made by taking a MOS capacitor as an example. This MOS capacitor is formed by sequentially forming a lower capacitor electrode 42, a capacitor insulating film 43, and an upper capacitor electrode 44 on a P-type silicon substrate 40 having a P-well region 41 formed thereon. The thickness of the lower capacitor electrode 42 is about 200 nm,
The thickness of the capacitor insulating film 43 is about 6 nm, and the thickness of the upper capacitor electrode 44 is about 200 nm. The electrode area is determined based on the desired capacitance.

Next, the manufacturing process of this MOS capacitor will be described. First, as shown in FIG. 13A, a lower capacitor electrode 42 made of polysilicon or the like is pattern-formed on a P-type silicon substrate 40 having a P-well region 41 formed thereon. Then, a capacitor insulating film 43 is patterned on the lower capacitor electrode 42. Further, a polysilicon pattern 440 is formed on the capacitor insulating film 43 by patterning. Next, FIG.
As shown in (b), in order to make the polysilicon pattern 440 conductive, As ions are accelerated on the surface of the P-type silicon substrate 40 at an acceleration energy of 10 keV and a dose of 3 × 1.
Ions are implanted under the condition of 0 15 atoms / cm 2 . As a result, the polysilicon pattern 440 becomes conductive and functions as the upper capacitance electrode 44.

At this time, a damage layer 45 is formed on the capacitive insulating film 43 located below the side end of the polysilicon pattern 440 due to physical damage.

Therefore, as shown in FIG. 13C, the P-type silicon substrate 40 is immersed in a wet etching solution, for example, a 3% aqueous solution of hydrogen fluoride for one minute to perform wet etching, and the capacitance insulating film 43 is formed. After selectively removing the formed damaged layer 45, the P-type silicon substrate 4
0 is washed with water and dried.

Through the above steps, a MOS capacitor is manufactured. In this MOS capacitor, the damage layer 45 formed on the capacitance insulating film 43 in the ion implantation step for imparting conductivity to the polysilicon pattern 440 is subjected to wet etching on the P-type silicon substrate 40. Since the capacitor insulating film 43 is removed, the characteristics are not deteriorated by the physical damage and the dielectric breakdown is not caused. When the thickness of the capacitor insulating film 43 is 2 to 8 nm, it is desirable to remove the capacitor insulating film 43 from the side edge of the capacitor electrode to the inside of about 5 to 20 nm.

Eighth Embodiment FIG. 14 is a sectional view showing a process of a method of manufacturing a semiconductor device according to an eighth embodiment of the present invention. Here, the same MOS capacitor as in the seventh embodiment is used. Will be described as an example.
The basic structure of this MOS capacitor is the same as that of the seventh embodiment shown in FIG. 13, and the same or similar parts are denoted by the same reference numerals. The dimensions are the same as in the previous embodiment, unless otherwise specified.

Next, the manufacturing process of this MOS capacitor will be described. First, as shown in FIG. 14A, a lower capacitor electrode 42 made of polysilicon or the like is pattern-formed on a P-type silicon substrate 40 having a P-well region 41 formed thereon. Then, a capacitor insulating film 43 is patterned on the lower capacitor electrode 42. Further, a polysilicon pattern 440 is formed on the capacitor insulating film 43 by patterning.

Next, as shown in FIG. 14B, wet etching is performed by immersing the P-type silicon substrate 40 in a wet etching solution, for example, a 3% aqueous solution of hydrogen fluoride for one minute. As a result, the portion of the capacitive insulating film 48 which is predicted to be physically damaged by the intrusion or passage of the impurity (As) by the next ion implantation, specifically, below the side end of the polysilicon pattern 440 Is removed. The removal of the portion expected to receive the physical damage is performed by removing the portion expected to receive the most physical damage, that is, the capacitance insulating film 43 near the portion exposed below the side end of the polysilicon pattern 440. By doing so, the deterioration of characteristics can be sufficiently prevented. The capacitance insulating film 43 is 5 to 20 nm from the side end of the capacitance electrode.
It is desirable to remove to the inside. After performing the wet etching, the P-type silicon substrate 40 is washed with water and dried.

Thereafter, as shown in FIG. 14 (c), As ions are implanted into the P-type silicon substrate 40 under the conditions of an acceleration energy locev and a dose of 3 × 10 15 atoms / cm 2 . Impurities (As) are implanted into the polysilicon pattern 440 to make it conductive, and function as the upper capacitance electrode 44. At this time, there is no structure for protecting the side edges of the capacitive insulating pus 43 and the upper capacitive electrode 44. Under such conditions, when ions are implanted at a high dose of 3 × 10 15 atoms / cm 2 , the implanted ion beam enters or passes through the capacitive insulating film 43 and causes physical damage. It is expected to receive. However, since the portion of the capacitor insulating film 43 which is expected to receive physical damage has been removed in advance by wet etching, no damage layer is formed on the capacitor insulating film 43.

Through the above steps, a MOS capacitor is manufactured. In this MOS capacitor, a portion of the capacitive insulating film 43, which is expected to be physically damaged in an ion implantation step performed for imparting conductivity to the polysilicon pattern 440, is previously set on the P-type silicon substrate 4
Since the capacitor insulating film 43 is removed by wet etching performed for 0, the characteristics of the capacitor insulating film 43 do not deteriorate due to physical damage or dielectric breakdown.

Ninth Embodiment FIG. 15 is a process sectional view of a method of manufacturing a semiconductor device according to a ninth embodiment of the present invention. Here, as in the fifth to eighth embodiments, A description will be given using a MOS capacitor as an example. In this MOS capacitor, a lower capacitance electrode 52, a capacitance recording film 53, and an upper capacitance electrode 54 are sequentially formed on an element isolation silicon oxide film 51 formed on a P-type silicon substrate 50 on which a P well region 51 is formed. It is configured. The dimensions are the same as in the previous embodiment, unless otherwise specified.

Next, the manufacturing process of this MOS capacitor will be described. First, as shown in FIG.
A lower capacitor electrode 52 made of polysilicon or the like is formed on the element isolation silicon oxide film 51 of the P-type silicon substrate 40 on which the element isolation silicon oxide film 51 having the S-divided structure is formed.
Is patterned. Then, a capacitor insulating film 53 is patterned on the lower capacitor electrode 52. Further, a polysilicon pattern 540 is formed on the capacitor insulating film 53 by a pattern.

Next, as shown in FIG. 15B, in order to make the polysilicon pattern 540 conductive, As ions are applied to the surface of the P-type silicon substrate 50 at an acceleration energy of 10 keV and a dose of 3 × 10 15. Ions are implanted under the condition of the number of atoms / cm 2 . As a result, the polysilicon pattern 54
0 has conductivity and functions as the upper capacitance electrode 54.

At this time, all the ion beams are not perpendicular to the surface of the P-type silicon substrate 50, and some beam components are implanted in an oblique direction. Furthermore, there is no structure for protecting the side edges of the capacitive insulating film 53 and the polysilicon pattern 540 during ion implantation. Under these conditions, and 3 × 10 15 atoms / cm
If ions are implanted at a high dose of 2 , the implanted ion beam may enter or pass through the capacitive insulating film 53. Therefore, a damage layer 55 is formed on the capacitive insulating film 53 located below the side end of the polysilicon pattern 540 due to physical damage.

Therefore, as shown in FIG. 15C, the P-type silicon substrate 50 is immersed in a wet etching solution, for example, a 3% aqueous solution of hydrogen fluoride for 1 minute to perform wet etching, so that the capacitance insulating film 53 is formed. After selectively removing the formed damage layer 55, the P-type silicon substrate 5
0 is washed with water and dried.

Through the above steps, a MOS capacitor is manufactured. In this MOS capacitor, the damage layer 55 formed on the capacitance insulating film 53 in the ion implantation step for imparting conductivity to the polysilicon pattern 540 is performed by wet-etching the P-type silicon substrate 50. Since the capacitor insulating film 53 is removed, the characteristics do not deteriorate or dielectric breakdown occurs due to physical damage. When the thickness of the capacitor insulating film 53 is 2 to 8 nm, the capacitor insulating film 5 extends from the side end of the capacitor electrode to the inside of about 5 to 20 nm.
3 is desirably removed.

Tenth Embodiment FIG. 16 is a sectional view showing a process of a method of manufacturing a semiconductor device according to a tenth embodiment of the present invention. Here, a MOS capacitor similar to that of the ninth embodiment is shown. Will be described as an example. The basic structure of this MOS capacitor is the same as that of the ninth embodiment shown in FIG. 15, and the same or similar parts are denoted by the same reference characters. The dimensions are the same as in the previous embodiment, unless otherwise specified.

Next, the manufacturing process of this MOS capacitor will be described. First, as shown in FIG.
A lower capacitor electrode 52 made of polysilicon or the like is patterned on the element isolation silicon oxide film 51 of the P-type silicon substrate 50 on which the element isolation silicon oxide film 51 having a structure difficult for S is formed. Then, a capacitor insulating film 53 is patterned on the lower capacitor electrode 52. Further, the capacitance insulating film 5
Then, a polysilicon pattern 540 is formed on the pattern 3.

Next, as shown in FIG. 16B, wet etching is performed by immersing the P-type silicon substrate 50 in a wet etchant, for example, a 3% aqueous solution of hydrogen fluoride for one minute. As a result, by removing the portion expected to be most likely to be physically damaged by the next ion implantation, that is, the capacitively disconnected film 53 near the portion exposed below the side end of the polysilicon pattern 540, The deterioration of characteristics can be sufficiently prevented. When the thickness of the capacitance insulating film 53 is 2
In the case of 88 nm, it is desirable to remove the capacitor insulating film 53 from the side end of the capacitor electrode to the inside of about 5 to 20 nm.
After performing wet etching, the P-type silicon substrate 5
0 is washed with water and dried.

After the wet etching is completed, FIG.
As shown in FIG. 6C, As ions are implanted into the P-type silicon substrate 50 at an acceleration energy of 10 keV and a dose of 3
Ions are implanted under the condition of × 10 15 atoms / cm 2 , and impurities (As) are implanted into the polysilicon pattern 540 so as to have conductivity and function as the upper capacitor electrode 54. At this time, there is no structure for protecting the side edges of the capacitive insulating film 53 and the upper capacitive electrode 54. When ions are implanted under such conditions and at a high dose of 3 × 10 15 atoms / cm 2 , the implanted ion beam enters or passes through the capacitive insulating film 53, causing physical damage. It is expected to receive. However, since the portion of the capacitor insulating film 53 that is expected to receive physical damage has been removed in advance by wet etching, no damage layer is formed on the capacitor insulating film 53.

Through the above steps, a MOS capacitor is manufactured. In this MOS capacitor, a portion of the capacitive insulating film 53, which is expected to be physically damaged in an ion implantation process for imparting conductivity to the polysilicon pattern 540, is previously set to a P-type silicon substrate 5
0 is removed by wet etching, and the capacitance-free green film 53 is not deteriorated by physical damage and dielectric breakdown does not occur.

In the fifth to tenth embodiments, the capacitance insulating film 32 is formed by ion implantation for imparting conductivity to the polysilicon patterns 330, 440, and 540 to be the upper capacitance electrodes 33, 44, and 54. , 43, and 53 have been described assuming that physical damage occurs. However, such physical damage, besides this,
It also occurs when manufacturing another semiconductor device formed on a semiconductor substrate together with a MOS capacitor. That is, the capacitance insulating film 3 of the MOS capacitor is affected by the influence of a doping process such as ion implantation performed when manufacturing another semiconductor device.
2, 43 and 53 are physically damaged. Even in such a case, if the method of the present invention removes physical damage or a portion where physical damage is expected to be formed, the same operation and effect as the fifth to tenth embodiments can be obtained. Obtainable.

Eleventh Embodiment FIG. 17 is a process sectional view of a method of manufacturing a semiconductor device according to an eleventh embodiment of the present invention. A description will be given of a MOS transistor having a drain extension structure as an example. This M
The feature of the structure of the OS transistor is that a sidewall 55 made of silicon nitride is provided instead of the sidewall 8 made of a silicon oxide film as shown in FIG. The first shown in FIG.
The embodiment is basically the same as that of the embodiment, and the same or similar parts are denoted by the same reference numerals. The dimensions are the same as in the previous embodiment, unless otherwise specified.

Next, the manufacturing process of this MOS transistor will be described. First, as shown in FIG. 17A, on a P-type silicon substrate 2 on which a P-well region 3 and a gate insulating film (a thermally grown silicon oxide film or the like) 6 are formed.
A gate electrode (polysilicon or the like) 7 is patterned.
Next, as shown in FIG.
For example, As ions are implanted as impurities, for example, under the conditions of an acceleration energy of 10 kev and a dose of 1 × 10 14 atoms / cm 2 , thereby forming an extension region 4 in the P-type silicon substrate 2. I do. The extension region 4 is formed in a relatively shallow region of the P-type silicon substrate 2 because it is formed by the first ion implantation step performed with a relatively small acceleration energy of 10 kev.

The damage layer 9 formed during such ion implantation not only deteriorates the characteristics of the MOS transistor but also causes dielectric breakdown.

Therefore, as shown in FIG. 17C, the P-type silicon substrate 2 is immersed in a wet etching solution, for example, a 3% aqueous solution of hydrogen fluoride for one minute to perform wet etching, thereby forming the gate insulating film 6. Is selectively removed. When the thickness of the gate insulating film 6 is 2 to 8 nm, 5 to 20 n from the side end of the gate electrode 7
It is desirable to remove the gate insulating film 6 to the inside of about m.

If the damaged layer 9 formed on the gate insulating film 6 is removed by wet etching, the gate insulating film 6 is selectively etched without damaging the gate electrode 7 made of polysilicon or the like. can do.

After removing the damaged layer 9 by wet etching, the P-type silicon substrate 2 is washed with water and dried.

After removing the damaged layer 9 in this manner, as shown in FIG. 17D, a silicon nitride having a higher dielectric constant than the gate insulating film 6 made of silicon oxide is formed on the P-type silicon substrate 2. A ride film 550 is deposited to a thickness of about 120 nm by a chemical vapor deposition method. At this time, the hole formed by etching the gate insulating film 6 is filled with the silicon nitride film 550. The interface between the silicon oxide film of the gate insulating film 6 and the silicon nitride film 550 is located inside the side end of the gate electrode 7.

Next, the silicon nitride film 550 is etched back to form side walls 55 as shown in FIG.

After the formation of the sidewall 55, FIG.
As shown in FIG. 7 (f), the P-type silicon substrate 2
Acceleration energy of 30 keV for s ions, dose 3 × 10
Second ion implantation is performed under the condition of 15 atoms / cm 2 to form source / drain regions 5 on the P-type silicon substrate 2. At this time, since the source / drain region 5 is formed by ion implantation performed with a relatively large acceleration energy of 30 keV, the source / drain region 5 is formed to a position deeper than the extension region 4.

At this time, the extension region 4 located below the side end of the gate electrode 7 and the side end of the gate electrode 7 is protected by the side wall 55,
There is no physical damage to the gate insulating film 6 due to the second ion implantation. Furthermore, at the time of the second ion implantation, the extension region 4 in the vicinity of the gate insulating film 6 is protected by the sidewall 55, so that the impurity concentration does not excessively increase.

Through the above steps, a MOS transistor having a source / drain / extension structure is manufactured. In this MOS transistor, the damage layer 9 formed on the gate insulating film 6 in the first ion implantation process performed to form the extension region 4
Is removed by performing wet etching on the P-type silicon substrate 2, so that the gate insulating film 6 does not deteriorate in characteristics due to physical damage or dielectric breakdown.

Further, since the side end portions of the gate insulating film 6 where hot carriers are most likely to be generated are replaced by silicon nitride, which is a substance having a higher dielectric constant than the gate insulating film 6, the generation of hot carriers is suppressed. Will be.

Further, the side wall 55 is made of a material having a higher dielectric constant than the gate insulating film 6 (silicon nitride).
Therefore, the fringe electric field of the gate increases, and the peak of the drain electric field decreases. Therefore, the generation of hot carriers is further suppressed due to the decrease in the drain electric field peak.

Twelfth Embodiment FIG. 18 is a process sectional view of a method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention. This MOS transistor is a modification of the eleventh embodiment. Its structural feature is, as shown in FIG. 18C, a side wall 55 made of a single silicon nitride layer, A sidewall 58 having a two-layer structure of silicon nitride and silicon oxide is provided. The other structure is basically the same as that of the eleventh embodiment shown in FIG.
And the same or similar parts are denoted by the same reference numerals. The dimensions other than the sidewall portion are the same as those of the previous embodiment unless otherwise specified.

Next, the manufacturing process of this MOS transistor will be described. First, a P-well region 3, a gate insulating film (silicon oxide film) 6, a gate electrode 7, and an extension region 4 are formed on a P-type silicon substrate 2, and a gate insulating film formed by the formation of the extension region 4 is formed. 6 is removed. When the thickness of the gate insulating film is 2 to 8 nm, 5 to 20 n from the side end of the gate electrode
It is desirable to remove the gate insulating film to the inside of about m. These steps are the same as the steps described with reference to FIGS.

After removing the damaged layer 9 in this manner, a silicon nitride film 560 having a higher dielectric constant than the gate insulating film 6 is deposited on the P-type silicon substrate 2 as shown in FIG. I do. Silicon nitride film 5
No. 60 is extremely deposited as 10 to 20 nm. At this time, the holes formed by removing the damaged layer of the gate insulating film 6 are filled with the deposited silicon nitride film 560. Further, the silicon nitride film 56
0 to 100 n-th silicon oxide film 570
m.

Next, the silicon nitride film 560 and the silicon oxide film 570 are etched back to form side walls 58 on the side walls of the gate insulating film 6 and the gate electrode 7 as shown in FIG. The sidewall 58 thus formed has a two-layer structure of the remaining film 56 of silicon nitride and the remaining film 57 of silicon oxide film.

After the formation of the sidewall 58, FIG.
As shown in FIG. 8C, the P-type silicon substrate 2
Acceleration energy of 30 keV and dose of 3 × 1 for s ions
Second ion implantation is performed under the condition of 0 15 atoms / Cm 2 to form source / drain regions 5 on the P-type silicon substrate 2.

Through the above steps, a MOS transistor having a source / drain / extension structure is manufactured. Also in this MOS transistor, the side end portion of the gate insulating film 6 where hot carriers are most likely to occur is formed of silicon nitride.
Since the material is replaced with a material having a higher dielectric constant, the generation of hot carriers is suppressed. Further, the inner film constituting the sidewall 58 is the gate insulating film 6.
Since the remaining film 56 is made of silicon nitride having a higher dielectric constant, the fringe electric field of the gate increases and the drain electric field peak decreases. Therefore, the generation of hot carriers is further suppressed due to the decrease in the drain electric field peak.

Further, the side wall 58 is formed by the remaining film 56 of silicon nitride and the remaining film 5 of silicon oxide film.
7 has a two-layer structure.
Nitride film 56 formed to constitute
The film thickness of 0 can be made as extremely thin as 10 to 20 nm. Silicon nitride is a substance that has a large difference in thermal expansion coefficient with respect to the silicon substrate 2 and increases thermal stress when adhered to each other. Therefore, in this structure in which the thickness of the silicon nitride film 560 is extremely small, silicon nitride is used. The thermal stress generated in the silicon substrate 2 by forming the ride film 560 can be made relatively small,
Inconvenience such as damage to the silicon substrate 2 due to thermal stress is less likely to occur.

Thirteenth Embodiment FIG. 19 is a process sectional view of a method of manufacturing a semiconductor device according to a thirteenth embodiment of the present invention. This MOS transistor is a modification of the eleventh embodiment, and its structural feature is, as shown in FIG. 19E, a sidewall 55 made of a single silicon nitride layer, That is, a sidewall 61 having a two-layer structure of silicon nitride and silicon oxide is provided. Just two
The structure of the side wall 61 having a layer structure is slightly different from that of the twelfth embodiment. The specific differences in the structure are as follows. That is, in the sidewall 58 of the eighteenth embodiment, the remaining film 56 of silicon nitride is interposed between the remaining film 57 of the silicon oxide film and the P-type silicon substrate 2, and the remaining film of the silicon oxide film is formed. 57 is P
It is not in direct contact with the mold silicon substrate 2. On the other hand, in the side wall 61 of the thirteenth embodiment, an inner side wall 59 is provided between the outer side wall 60 made of a silicon oxide film (corresponding to the remaining film 57 of the silicon oxide film) and the P-type silicon substrate 2. (Corresponding to the remaining film 56 of silicon nitride) is not interposed, and the outer side wall 60 is in direct contact with the P-type silicon substrate 2.

The other structure is the same as that of the first structure shown in FIG.
It is basically the same as that of the first embodiment, and the same or similar parts are denoted by the same reference numerals. The dimensions other than the sidewall portion are the same as those of the previous embodiment unless otherwise specified.

First, a P-well region 3, a gate insulating film 6, a gate electrode 7, and an extension region 4 are formed on a P-type silicon substrate 2, and a gate insulating film 6 formed by the formation of the extension region 4 is formed. Remove the damaged layer. When the thickness of the gate insulating film is 2 to 8 nm,
It is desirable to remove the gate insulating film from the side edge of the gate electrode to the inside of about 5 to 20 nm. These steps are
The steps are the same as those described with reference to FIGS.

After removing the damaged layer 9 in this manner, a silicon nitride film 590 having a higher dielectric constant than the gate insulating film 6 is formed on the P-type silicon substrate 2 as shown in FIG. accumulate. The silicon nitride film 590 is extremely deposited with a thickness of 10 to 20 nm. At this time,
The holes formed by removing the damaged layer of the gate insulating film 6 are filled with the deposited silicon nitride film 590.

After the silicon nitride film 590 is formed, the silicon nitride film 590 is etched back, so that the side wall 59 of the gate insulating film 6 and the gate electrode 7 as shown in FIG.
To form

After forming the inner side wall 59,
Further, as shown in FIG. 19C, a silicon oxide film 600 is deposited on the P-type silicon substrate 2 from the inner side wall 59 to a thickness of 100 to 110 nm.

Next, by etching back the silicon oxide film 600, the outer side wall 60 as shown in FIG. 19D is formed.

The inner side wall 59 and the outer side wall 60 thus formed constitute a side wall 61.

After forming the side wall 61, FIG.
As shown in FIG. 8E, the P-type silicon substrate 2
Acceleration energy of 30 keV and dose of 3 × 1 for s ions
A second ion implantation is performed under the condition of 0 15 atoms / Cm 2 to form source / drain regions 5 on the P-type silicon substrate 2.

Through the above steps, a MOS transistor having a source / drain / extension structure is manufactured. Also in this MOS transistor, the side end portion of the gate insulating film 6 where hot carriers are most likely to occur is formed of silicon nitride.
Since the material is replaced with a material having a higher dielectric constant, the generation of hot carriers is suppressed. Further, since the inner side wall 59 constituting the side wall 61 is made of silicon nitride having a higher dielectric constant than the gate insulating film 6, the fringe electric field of the gate increases and the peak of the drain electric field decreases. Therefore, the generation of hot carriers is further suppressed due to the decrease in the drain electric field peak.

In addition, since the side wall 61 has a two-layer structure of the inner side wall 59 and the outer side wall 61, the silicon nitride film 590 formed to form the side wall 58 has a thickness of 10
It was possible to achieve a very thick thickness of about 20 nm. Since silicon nitride is a substance having a large thermal stress and a different coefficient of thermal expansion for the silicon substrate 2, in this structure in which the thickness of the silicon nitride film 590 is extremely small, the silicon nitride film 590 is formed by forming the silicon nitride film 590. 2, the thermal stress generated in the silicon substrate 2 is relatively small, and the disadvantage that the silicon substrate 2 is damaged by the thermal stress is less likely to occur.

Further, the structure of the MOS transistor is suitable for a method of manufacturing a semiconductor device having a CMOS structure. That is, in the structure of the CMOS transistor, it is necessary to diffuse an N-type impurity (such as arsenic (As)) and a P-type impurity (such as boron (B)) as active regions on the same silicon substrate. However, a P-type impurity such as boron (B) has a characteristic that it is more easily diffused than an N-type impurity. When an active region is formed by such diffusion of the P-type impurity, P-type impurities sandwiching a gate are formed.
There is a disadvantage that a short channel effect is easily generated between the channel active regions.

Therefore, first, a mask having an opening corresponding to the N-type impurity diffusion region is formed on the silicon substrate on which the gate is formed, and then the N-type impurity is diffused into the silicon substrate to form an N-channel active region. Form. further,
Inner sidewall 59 made of silicon nitride
Is formed, and in this state, a mask having an opening corresponding to the P-type impurity diffusion region is formed in the silicon substrate. And
P-type impurities are diffused into the silicon substrate. At this time, P
The shape impurity diffuses along the plane direction and tries to enter under the gate. However, due to the formation of the inner side wall 59, the P-type impurity implanted region is located at a position separated from the gate to some extent in advance.
Even if the shaped impurities diffuse to some extent in the plane direction, they do not enter the lower side of the gate, and the short channel effect is less likely to occur between the P channel active regions opposed to each other across the gate. In this case, the inner side wall 5
The thickness of the silicon nitride film 590 of 9 needs to be set in consideration of the length of the diffusion of the P-type impurity in the planar direction.

In the first to thirteenth embodiments, silicon nitride is used as the substance having a higher dielectric constant than the gate insulating film 6 made of silicon oxide. Materials with a high rate include Si 3 N 4 , Ta 2 O 5 , SrTiO 3 (= ST
O), (Ba X SR 1 -X) TiO 3 (= BST), PbZ
rO 3 —PbTiO 3 (= PZT), SrBi 2 Ta 2 O 9
(= Y1), TiO 3 , ZrO 2 , Y 2 O 3 , BaTi
O 3 , Sr x Ba 1 -x Nb 2 O 6 or the like can be used.

In the fifth to tenth embodiments, the capacitance insulating film 32 is formed by ion implantation for imparting conductivity to the polysilicon patterns 330, 440, and 540 to be the upper capacitance electrodes 33, 44, and 54. , 43, and 53 have been described assuming that physical damage occurs. However, such physical damage, besides this,
It also occurs when manufacturing another semiconductor device formed on a semiconductor substrate together with a MOS capacitor. That is, the capacitance insulating film 3 of the MOS capacitor is affected by the influence of a doping process such as ion implantation performed when manufacturing another semiconductor device.
2, 43 and 53 are physically damaged. Even in such a case, if the method of the present invention removes physical damage or a portion where physical damage is expected to be formed, the same operation and effect as the fifth to tenth embodiments can be obtained. Obtainable.

The ligating insulating film 6 is formed by ion implantation.
Damage to the 23 to the capacitance insulating films 32, 43, and 53 includes charging damage in addition to the physical damage described above. This damage is caused by the electric charge charged to the ligating electrodes 7 and 24 and the capacitance electrodes 33, 44 and 54 by the ion implantation through the gate insulating films 6 and 23 and the capacitance insulating films 32 and 43. , 3
Occurs when flowing to 0, 40, 50.

For such charging damage, the l, third, fifth, seventh, ninth, eleventh, twelfth,
As in the thirteenth embodiment, after physical damage is formed by ion implantation, the damaged layer can be effectively prevented by removing the damaged layer. That is, the charges charged in the gate electrodes 7 and 24 and the capacitance electrodes 33, 44 and 54 are accumulated to some extent, and then flow toward the P-type silicon substrates 2, 20, 30, 40 and 50. The charge starts to flow for some time after the ion implantation, so that the gate insulating films 6 and 23 and the capacitor insulating film 3
In 2 and 43, a damaged layer having increased conductivity due to intrusion of impurities by ion implantation has already been formed. Therefore, charges flowing from the gate electrodes 7 and 24 and the capacitor electrodes 33, 44 and 54 selectively flow through these damaged layers, and the gate insulating films 6 and 23 and the capacitor insulating film 3 other than the damaged layers.
The flow hardly flows to the portions 2 and 43. Therefore, charging damage does not occur in the portions of the gate insulating films 6 and 23 and the capacitor insulating films 32 and 43 where no charge flows. Further, the portion where the charge has been damaged due to the flow of the electric charge (= the portion where the physical damage has occurred) is removed by the next wet etching. For such a reason, the charging damage does not remain in the gate insulating films 6 and 23 and the capacitive insulating films 32 and 43.

Further, in each of the above-described embodiments, the present invention is implemented in a method of manufacturing a semiconductor device employing ion implantation as a doping step. ,
The present invention can also be implemented in a method of manufacturing a semiconductor device employing a plasma implant such as a plasma immersion ion implant or a plasma doping. Further, in each of the above-described embodiments, the embodiment of the present invention has been described in the case where the semiconductor device is formed on a P-type silicon substrate. However, the semiconductor device is mounted on an N-type semiconductor substrate such as an N-type silicon substrate. Needless to say, the same can be implemented in the case of forming.

[0137]

According to the manufacturing method of the present invention, the following effects can be obtained.

The damage layer can be easily formed by removing physical damage caused in the insulating layer by doping with impurities or removing in advance the insulating layer which is predicted to cause physical damage by doping with impurities. Can be prevented. In addition, the method of removing the insulating layer by wet etching does not cause another stress or metal contamination problem in the insulating layer. Therefore, in the present invention,
By improving the reliability of the insulating film, it can greatly contribute to the manufacture of an ultrafine semiconductor device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing each step of a method for manufacturing a semiconductor device (MOS transistor) according to a first embodiment of the present invention.

FIG. 2 shows a semiconductor device (M) manufactured by the manufacturing method of the present invention.
FIG. 4 is an enlarged cross-sectional view showing a state during the manufacture of an OS transistor.

FIG. 3 shows the results of a constant voltage TDDB test in the MOS structure without ion implantation.

FIG. 4 shows a constant voltage TDDB test result when wet etching is not performed after ion implantation in a MOS structure.

FIG. 5 shows a constant voltage TDDB test result in a case where wet etching is performed for 30 seconds after ion implantation in a MOS structure.

FIG. 6 shows a constant voltage TDDB test result when wet etching is performed for 90 seconds after ion implantation in a MOS structure.

FIG. 7 shows a constant voltage TDDB test result in a case where wet etching is performed for 120 seconds after ion implantation in a MOS structure.

FIG. 8 is a sectional view showing each step of a method for manufacturing a semiconductor device (MOS transistor) according to the second embodiment of the present invention.

FIG. 9 is a sectional view showing each step of a method for manufacturing a semiconductor device (MOS transistor) according to a third embodiment of the present invention.

FIG. 10 is a sectional view showing each step of a method for manufacturing a semiconductor device (MOS transistor) according to a fourth embodiment of the present invention.

FIG. 11 is a sectional view showing each step of a method for manufacturing a semiconductor device (MOS capacitor) according to a fifth embodiment of the present invention.

FIG. 12 is a sectional view showing each step of a method for manufacturing a semiconductor device (MOS capacitor) according to a sixth embodiment of the present invention.

FIG. 13 is a sectional view showing each step of a method for manufacturing a semiconductor device (MOS capacitor) according to a seventh embodiment of the present invention.

FIG. 14 is a sectional view showing each step of a method for manufacturing a semiconductor device (MOS capacitor) according to an eighth embodiment of the present invention.

FIG. 15 is a sectional view showing each step of a method for manufacturing a semiconductor device (MOS capacitor) according to a ninth embodiment of the present invention.

FIG. 16 is a sectional view showing each step of a method for manufacturing a semiconductor device (MOS capacitor) according to the tenth embodiment of the present invention.

FIG. 17 is a cross-sectional view showing each step of the method for manufacturing a semiconductor device (MOS transistor) according to the 11th embodiment of the present invention;

FIG. 18 is a sectional view showing each step of a method for manufacturing a semiconductor device (MOS transistor) according to a twelfth embodiment of the present invention.

FIG. 19 is a sectional view showing each step of a method for manufacturing a semiconductor device (MOS transistor) according to the thirteenth embodiment of the present invention.

FIG. 20 is a cross-sectional view showing each step of a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

 2, 20, 30, 40, 50 P-type silicon substrate 6, 23 Gate insulating film 7, 24 Gate electrode 32, 43, 53 Capacity insulating film 33 Capacity electrode 44, 54 Upper capacity electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification code Agency reference number FI Technical indication H01L 21/822 (72) Inventor Koji Eguchi Inside

Claims (18)

[Claims]
1. A method for manufacturing a semiconductor device comprising the following steps.
Forming an insulating layer on a semiconductor substrate, forming a conductive layer on the insulating layer, patterning the conductive layer, doping impurities in at least one of the semiconductor substrate and the conductive layer, and positioning the conductive layer under the conductive layer. An insulating layer for removing at least a part of a portion where the impurity is doped or passed
2. A method for manufacturing a semiconductor device including the following steps.
Forming an insulating layer on the semiconductor substrate, forming a conductive layer on the insulating layer, patterning the conductive layer, wherein the insulating layer is located below the conductive layer, and is doped or passed with impurities in a later step. Removing at least a part of a portion to be doped with an impurity into at least one of the semiconductor substrate and the conductor layer
3. A method for manufacturing a semiconductor device comprising the following steps.
Forming a second conductive layer in or on a semiconductor substrate forming an insulating layer on the first conductive layer forming a second conductive layer on the insulating layer patterning the second conductive layer A semiconductor substrate or the insulating layer located under the first conductive layer to dope at least one of the first and second conductive layers with an impurity,
Removing at least a portion of the portion doped or passed by the impurity
4. A method for manufacturing a semiconductor device, comprising the following steps.
Forming a second conductive layer in or on a semiconductor substrate forming an insulating layer on the first conductive layer forming a second conductive layer on the insulating layer patterning the second conductive layer The insulating layer located under the -th conductor layer,
Removing at least a part of a portion where the impurity is doped or passes through in a later step;
5. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer below a side end of the conductor layer is removed.
6. The method of manufacturing a semiconductor device according to claim 2, wherein the insulating layer below a side end of the conductor layer is removed.
7. The method for manufacturing a semiconductor device according to claim 3, wherein the insulating layer below a side end of the second conductor layer is removed.
8. The method for manufacturing a semiconductor device according to claim 4, wherein the insulating layer below a side end of the second conductor layer is removed.
9. The method of manufacturing a semiconductor device according to claim 1, further comprising the following steps. In a portion where the second insulating layer is located below the conductor layer,
Forming a second insulating layer having a higher dielectric constant than the first insulating layer;
10. The method of manufacturing a semiconductor device according to claim 2, further comprising the following steps. In a portion where the second insulating layer is located below the conductor layer,
Forming a second insulating layer having a higher dielectric constant than the first insulating layer;
11. A semiconductor device having the following configuration. A semiconductor substrate, a first insulating film thermally formed on the semiconductor substrate, a gate electrode formed on the first insulating film, and a gate electrode formed on the semiconductor substrate so as to be separated from each other. A source / drain region, wherein a side end of the negative insulating film is located inside a side end of the gate electrode facing the source / drain region.
12. The semiconductor device according to claim 11, further comprising: A second insulating film formed in contact with a side surface of the gate electrode and a side end of the first insulating film
13. The semiconductor device according to claim 12, wherein the second insulating film is made of a material having a higher dielectric constant than the first insulating film.
14. The semiconductor device according to claim 13, further comprising: Third insulating film formed on the second insulating film
15. The semiconductor device according to claim 14, wherein the dielectric constant of the third insulating film is substantially the same as that of the first insulating film.
16. The semiconductor device according to claim 11, further comprising: A second insulating film formed below the vicinity of the side end of the gate electrode
17. The semiconductor device according to claim 16, wherein the second insulating film is made of a material having a higher dielectric constant than the first insulating film.
18. The semiconductor device according to claim 16, wherein said first insulating film is thermally grown, and said second insulating film is chemically grown. A semiconductor device characterized by the above-mentioned.
JP2939597A 1996-02-13 1997-02-13 Semiconductor device and manufacturing method thereof Withdrawn JPH1065167A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2497996 1996-02-13
JP8-24979 1996-06-11
JP8-149004 1996-06-11
JP14900496 1996-06-11
JP2939597A JPH1065167A (en) 1996-02-13 1997-02-13 Semiconductor device and manufacturing method thereof

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Application Number Priority Date Filing Date Title
JP2939597A JPH1065167A (en) 1996-02-13 1997-02-13 Semiconductor device and manufacturing method thereof

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007096976A1 (en) * 2006-02-24 2007-08-30 Fujitsu Limited Semiconductor device and method for manufacturing same
US7288470B2 (en) 2001-03-29 2007-10-30 Kabushiki Kaisha Toshiba Semiconductor device comprising buried channel region and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7288470B2 (en) 2001-03-29 2007-10-30 Kabushiki Kaisha Toshiba Semiconductor device comprising buried channel region and method for manufacturing the same
WO2007096976A1 (en) * 2006-02-24 2007-08-30 Fujitsu Limited Semiconductor device and method for manufacturing same
US7898036B2 (en) 2006-02-24 2011-03-01 Fujitsu Semiconductor Limited Semiconductor device and process for manufacturing the same
JP5062166B2 (en) * 2006-02-24 2012-10-31 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof

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