JP2004503089A - 銅のメタライゼーションに関するビアファーストのデュアルダマシン法 - Google Patents
銅のメタライゼーションに関するビアファーストのデュアルダマシン法 Download PDFInfo
- Publication number
- JP2004503089A JP2004503089A JP2002507438A JP2002507438A JP2004503089A JP 2004503089 A JP2004503089 A JP 2004503089A JP 2002507438 A JP2002507438 A JP 2002507438A JP 2002507438 A JP2002507438 A JP 2002507438A JP 2004503089 A JP2004503089 A JP 2004503089A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- layer
- forming
- vias
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US60854000A | 2000-06-30 | 2000-06-30 | |
| US09/608,541 | 2000-06-30 | ||
| PCT/US2001/021161 WO2002003457A2 (en) | 2000-06-30 | 2001-07-02 | Via first dual damascene process for copper metallization |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2004503089A true JP2004503089A (ja) | 2004-01-29 |
| JP2004503089A6 JP2004503089A6 (ja) | 2004-08-05 |
| JP2004503089A5 JP2004503089A5 (enExample) | 2005-02-03 |
Family
ID=24436949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002507438A Pending JP2004503089A (ja) | 2000-06-30 | 2001-07-02 | 銅のメタライゼーションに関するビアファーストのデュアルダマシン法 |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2004503089A (enExample) |
| KR (1) | KR100474605B1 (enExample) |
| TW (1) | TW519725B (enExample) |
| WO (1) | WO2002003457A2 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102454363B1 (ko) | 2020-08-24 | 2022-10-14 | 주식회사 세움피엔에프 | 운동기구의 수평 이동 장치 |
| KR102491980B1 (ko) | 2021-01-05 | 2023-01-27 | 최순복 | 필라테스용 레더바렐 |
| CN113394184B (zh) * | 2021-06-09 | 2022-06-17 | 武汉新芯集成电路制造有限公司 | 半导体器件及其制造方法 |
| US11876047B2 (en) | 2021-09-14 | 2024-01-16 | International Business Machines Corporation | Decoupled interconnect structures |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5904565A (en) * | 1997-07-17 | 1999-05-18 | Sharp Microelectronics Technology, Inc. | Low resistance contact between integrated circuit metal levels and method for same |
| US6057239A (en) * | 1997-12-17 | 2000-05-02 | Advanced Micro Devices, Inc. | Dual damascene process using sacrificial spin-on materials |
| US6127258A (en) * | 1998-06-25 | 2000-10-03 | Motorola Inc. | Method for forming a semiconductor device |
| US6380096B2 (en) * | 1998-07-09 | 2002-04-30 | Applied Materials, Inc. | In-situ integrated oxide etch process particularly useful for copper dual damascene |
| US6245662B1 (en) * | 1998-07-23 | 2001-06-12 | Applied Materials, Inc. | Method of producing an interconnect structure for an integrated circuit |
| JP2000150644A (ja) * | 1998-11-10 | 2000-05-30 | Mitsubishi Electric Corp | 半導体デバイスの製造方法 |
| EP1192656A1 (en) * | 1999-06-30 | 2002-04-03 | Intel Corporation | Method of protecting an underlying wiring layer during dual damascene processing |
-
2001
- 2001-07-02 WO PCT/US2001/021161 patent/WO2002003457A2/en not_active Ceased
- 2001-07-02 KR KR10-2002-7018006A patent/KR100474605B1/ko not_active Expired - Lifetime
- 2001-07-02 TW TW090116395A patent/TW519725B/zh not_active IP Right Cessation
- 2001-07-02 JP JP2002507438A patent/JP2004503089A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| WO2002003457A3 (en) | 2002-06-06 |
| WO2002003457A2 (en) | 2002-01-10 |
| TW519725B (en) | 2003-02-01 |
| KR100474605B1 (ko) | 2005-03-10 |
| KR20030020324A (ko) | 2003-03-08 |
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