JP2004361518A - Pixel circuit, display device, and drive method of pixel circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pixel circuit for displaying images with high dignity as a result by stably and accurately supplying current of a prescribed value to a light-emitting element of each pixel, independently of the unevenness of the threshold of the active element of a pixel inside and the degree of movement, and to provide a display device and a drive method of the pixel circuit. <P>SOLUTION: In a voltage detection mode, when TFT113 and TFT115 are conducted, the voltage value of the gate of a drive transistor 111 is stored, when reference current Iref is made to flow to a first node ND111. In a normal mode, when TFT113 and TFT115 become conductive, the voltage of the stored value is supplied to the first node ND111, and a threshold Vth and the degree of movement μ of TFT111 are corrected. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a pixel circuit having an electro-optical element whose brightness is controlled by a current value, such as an organic EL (Electroluminescence) display, and an image display device in which the pixel circuits are arranged in a matrix, and in particular, each pixel circuit. The present invention relates to a so-called active matrix type image display device in which the value of a current flowing through an electro-optical element is controlled by an insulated gate type field effect transistor provided therein, and a method of driving a pixel circuit.
[0002]
[Prior art]
2. Description of the Related Art In an image display device, for example, a liquid crystal display, an image is displayed by arranging a large number of pixels in a matrix and controlling light intensity for each pixel according to image information to be displayed.
The same applies to an organic EL display and the like, but an organic EL display is a so-called self-luminous display having a light emitting element in each pixel circuit, and has higher image visibility than a liquid crystal display, and a backlight. It has advantages such as unnecessary and quick response speed.
Further, the luminance of each light emitting element is controlled by a current value flowing through the light emitting element to obtain a color gradation, that is, it is greatly different from a liquid crystal display or the like in that the light emitting element is of a current control type.
[0003]
The organic EL display can be driven by a simple matrix method or an active matrix method as in the liquid crystal display. However, the former has a simple structure, but it is difficult to realize a large and high-definition display. There's a problem.
For this reason, active matrix systems, in which the current flowing through the light emitting element inside each pixel circuit is controlled by an active element provided inside the pixel circuit, generally a TFT (Thin Film Transistor), are being actively developed.
[0004]
FIG. 8 is a block diagram showing a configuration of a general organic EL display device.
As shown in FIG. 8, the display device 1 has a pixel array section 2 in which pixel circuits (PXLC) 2a are arranged in an m × n matrix, a horizontal selector (HSEL) 3, a light scanner (WSCN) 4, and a horizontal It has data lines DTL1 to DTLn selected by the selector 3 and supplied with a data signal corresponding to luminance information, and scanning lines WSL1 to WSLm selectively driven by the write scanner 4.
[0005]
FIG. 9 is a circuit diagram showing a configuration example of the pixel circuit 2a of FIG. 8 (see, for example, Patent Documents 1 and 2).
The pixel circuit in FIG. 9 has the simplest circuit configuration among many proposed circuits, and is a so-called two-transistor driving circuit.
[0006]
The pixel circuit 2a in FIG. 9 includes a p-channel thin film field effect transistor (hereinafter, referred to as TFT) 11 and TFT 12, a capacitor C11, and an organic EL element (OLED) 13 which is a light emitting element. In FIG. 9, DTL indicates a data line, and WSL indicates a scanning line.
Since an organic EL element has rectification in many cases, it is sometimes called an OLED (Organic Light Emitting Diode). In FIG. 9 and the like, a diode symbol is used as a light emitting element. It does not require rectification.
In FIG. 9, the source of the TFT 11 is connected to the power supply potential VCC, and the cathode of the light emitting element 13 is connected to the ground potential GND. The operation of the pixel circuit 2a in FIG. 9 is as follows.
[0007]
Step ST1 :
When the write potential Vdata is applied to the data line DTL while the scanning line WSL is in the selected state (here, low level), the TFT 12 is turned on to charge or discharge the capacitor C11, and the gate potential of the TFT 11 becomes Vdata.
[0008]
Step ST2 :
When the scanning line WSL is in a non-selected state (here, high level), the data line DTL is electrically disconnected from the TFT 11, but the gate potential of the TFT 11 is stably held by the capacitor C11.
[0009]
Step ST3 :
The current flowing through the TFT 11 and the light emitting element 13 has a value corresponding to the gate-source voltage Vgs of the TFT 11, and the light emitting element 13 continues to emit light at a luminance corresponding to the current value.
The operation of selecting the scanning line WSL and transmitting the luminance information given to the data line to the inside of the pixel as in step ST1 is hereinafter referred to as “writing”.
As described above, in the pixel circuit 2a of FIG. 9, once Vdata is written, the light emitting element 13 continues to emit light at a constant luminance until the next rewriting.
[0010]
As described above, in the pixel circuit 2a, the value of the current flowing through the EL light emitting element 13 is controlled by changing the gate applied voltage of the FET 11, which is a drive transistor.
At this time, the source of the p-channel drive transistor is connected to the power supply potential VCC, and the TFT 11 always operates in the saturation region. Therefore, it is a constant current source having the value shown in Expression 1 below.
[0011]
(Equation 1)
Ids = 1/2 · μ (W / L) Cox (Vgs− | Vth |) ² … (1)
[0012]
Here, μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the gate width, L is the gate length, Vgs is the gate-source voltage of the TFT 11, and Vth is the threshold of the TFT 11. Each value Vth is shown.
[0013]
In the simple matrix type image display device, each light emitting element emits light only at the selected moment, whereas in the active matrix, as described above, the light emitting element continues to emit light even after the writing is completed. In comparison with a large-size and high-definition display, it is advantageous in that the peak luminance and the peak current of the light-emitting element can be reduced.
[0014]
However, TFTs generally have large variations in Vth and mobility μ. Therefore, even if the same input voltage is applied to the gates of different drive transistors, the on-currents vary, and as a result, the uniformity of image quality deteriorates.
[0015]
Many pixel circuits have been proposed to solve this problem. A typical example is shown in FIG. 10 (for example, see Patent Document 3 or Patent Document 4).
[0016]
The pixel circuit 2b in FIG. 10 includes p-channel TFTs 21 to 24, capacitors C21 and C22, and an organic EL light emitting element (OLED) 25 as a light emitting element. In FIG. 10, DTL indicates a data line, WSL indicates a scanning line, AZL indicates an auto-zero line, and DSL indicates a driving line.
[0017]
The operation of the pixel circuit 2b will be described below with reference to timing charts shown in FIGS.
FIG. 11A shows the scanning signal ws [1] applied to the scanning line WSL1 in the first row of the pixel array, and FIG. 11B shows the scanning signal ws2 applied to the scanning line WSL2 in the second row of the pixel array. FIG. 11C shows the scanning signal ws [2], FIG. 11C shows the auto-zero signal az [1] applied to the auto-zero line AZL1 of the first row of the pixel array, and FIG. 11D shows the second row of the pixel array. 11E shows an auto-zero signal az [2] applied to the auto-zero line AZL2, and FIG. 11F shows a drive signal ds [1] applied to the first-row drive line DSL1 of the pixel array. 11 shows a drive signal ds [2] applied to the drive line DSL2 in the second row of the pixel array, and FIG. 11G shows a gate potential Vg of the TFT 21.
Note that the operation of the pixel circuits in the first row will be described below.
[0018]
As shown in FIGS. 11C and 11E, the drive signal ds [1] to the drive line DSL1 and the auto-zero signal az [1] to the auto-zero line AZL1 are set to low level, and the TFTs 22 and 23 are turned on. . At this time, since the TFT 21 is connected to the light emitting element (OLED) 25 in a diode-connected state, a current flows through the TFT 21. At this time, the gate potential Vg of the TFT 21 drops as shown in FIG.
[0019]
As shown in FIG. 11E, the driving signal ds [1] to the driving line DSL1 is set to a high level, and the TFT 22 is turned off. At this time, as shown in FIG. 11A, the scanning signal ws [1] to the scanning line WSL1 is at a high level and the TFT 24 is kept in a non-conductive state.
Since the current flowing through the light emitting element 25 is cut off as the TFT 22 becomes non-conductive, the gate potential Vg of the TFT 21 rises as shown in FIG. When the voltage rises to Vth |, the TFT 21 becomes non-conductive and the potential is stabilized. This operation is called "auto-zero operation".
[0020]
As shown in FIG. 11C, the auto-zero signal az [1] to the auto-zero line AZL1 is set to a high level to turn off the TFT 23 to terminate the auto-zero operation (Vth correction operation), and then drive the driving line DSL1. The signal ds [1] is set to a low level, and the TFT 22 is turned on.
[0021]
Then, the scanning signal ws [1] to the scanning line WSL1 is set to a low level as shown in FIG. 11A, the TFT 24 is turned on, and the data signal of a predetermined potential transmitted to the data line DTL1 is applied to the capacitor C21. Apply. Thereby, as shown in FIG. 11 (G), the gate potential of the TFT 21 is reduced by ΔVg via the capacitor C21.
As shown in FIG. 11A, the scanning line WSL1 is set at a high level, and the TFT 24 is turned off.
As a result, a current flows through the TFT 21 and the EL light emitting element (OLED) 25, and the EL light emitting element 25 starts emitting light.
[0022]
[Patent Document 1]
USP 5,684,365
[Patent Document 2]
JP-A-8-234683
[Patent Document 3]
USP 6,229,506
[Patent Document 4]
The Japanese Patent Application Publication No. 2002-514320 discloses FIG. 3
[0023]
[Problems to be solved by the invention]
As described above, in the pixel circuit of FIG. 10, during the period when the EL light emitting element 25 does not emit light, the drive transistor TFT 21 is cut off by turning on the TFT 23 which is an auto-zero switch. In the cut-off state, no current flows through the transistor TFT21, so that its gate-source voltage Vgs is equal to the threshold value Vth of each transistor, and Vth variation for each pixel is cancelled.
Next, by turning off the TFT 23 and then turning on the TFT 24, the voltage ΔV is coupled to the gate of the drive transistor TFT 21 through the capacitor C21 in the pixel. Assuming that this coupling amount is V0, the drive transistor TFT 21 flows an on-current corresponding to Vgs-Vth = V0 regardless of Vth, and an image quality uniform in uniformity due to Vth variation is obtained.
[0024]
However, in the pixel circuit of FIG. 10, even if the Vth variation can be corrected, the variation in the mobility μ cannot be corrected.
Hereinafter, this problem will be described in more detail with reference to the drawings.
[0025]
FIG. 12 is a diagram illustrating a characteristic curve of ΔV (= Vgs−Vth) and a drain-source current Ids of drive transistors having different mobilities in the pixel circuit of FIG. 10.
In FIG. 12, the horizontal axis represents the voltage ΔV, and the vertical axis represents the current Ids. In FIG. 12, a curve indicated by a solid line indicates the characteristic of the pixel A, and a curve indicated by a broken line indicates the characteristic of the pixel B.
[0026]
As shown in FIG. 12, the mobility of the characteristic of the pixel A indicated by the solid line and the characteristic of the pixel B indicated by the broken line are different.
In the pixel circuit system of FIG. 10, at the auto-zero point (ΔV = V0), current values are equal even in pixel transistors having different mobilities.
However, as the voltage subsequently increases, variations in the mobility μ appear in the current value.
For example, even when the same voltage ΔV = V0 is applied to the pixels A and B having different mobilities, the current Ids varies according to the above equation 1, and the brightness of the pixels differs.
In other words, a large current value flows, and as the brightness increases, the current value varies in mobility, the uniformity varies, and the image quality deteriorates.
[0027]
FIG. 13 is a diagram illustrating a change in the gate voltage of the drive transistor during the auto-zero operation in the pixels C and D having different threshold values Vth of the drive transistor.
In FIG. 13, the horizontal axis represents time t, and the vertical axis represents gate voltage vg. In FIG. 13, the curve shown by the solid line shows the characteristic of the pixel C, and the curve shown by the broken line shows the characteristic of the pixel D.
[0028]
Auto zero is performed by connecting the gate and the source of the drive transistor. As the cut-off region is approached, the on-current of the drive transistor rapidly decreases.
Therefore, it takes a long time to completely cut off and cancel the variation in the threshold value. As shown in FIG. 13, if the auto-zero time is insufficient, the variation in the threshold value Vth of the pixel C is not completely canceled.
As described above, it is inferred that the writing state of the gate voltage also varies due to the variation of the threshold value Vth, and the uniformity is thereby degraded.
[0029]
Further, even if a sufficient auto-zero time is taken to cancel the variation of the threshold value Vth, a small amount of off-state current flows through the drive transistor after cutoff.
Therefore, as shown in FIG. 14, the gate voltage gradually increases toward power supply voltage Vcc. As a result, even though the variation of the threshold value Vth is once canceled by auto-zero, the gate potential of the pixel having the variation of the threshold value Vth finally approaches the power supply voltage, so that the threshold is increased again. The variation of the value Vth appears.
[0030]
As described above, in the actual device, in order to effectively cancel the variation of the threshold value Vth, it is necessary to optimally adjust the auto-zero period for each panel.
However, the adjustment of the optimum auto-zero period for each panel takes a huge amount of adjustment time, and increases the cost of the panel.
[0031]
The present invention has been made in view of the above circumstances, and an object thereof is to stably and accurately emit light of each pixel irrespective of the variation of the mobility as well as the variation of the threshold value of the active element inside the pixel. It is an object of the present invention to provide a pixel circuit, a display device, and a method for driving a pixel circuit, which can supply a current of a desired value to a pixel circuit and, as a result, display a high-quality image.
[0032]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of the present invention is a pixel circuit for driving an electro-optical element whose luminance changes according to a flowing current, wherein a data line to which a data signal according to luminance information is supplied; First, second, and third nodes, first and second reference potentials, supply means for selectively supplying a predetermined reference current and a predetermined voltage, and a connection to the first node A driving transistor for forming a current supply line between the first terminal and the second terminal, and controlling a current flowing through the current supply line in accordance with a potential of a control terminal connected to the second node; A first switch connected to the first node, a second switch connected between the first node and the second node, and a connection between the data line and the third node. The third switch, and the first switch A fourth switch connected between a node and the supply means, and a coupling capacitor connected between the second node and the third node, wherein the first reference potential A current supply line of the driving transistor, the first node, the first switch, and the electro-optical element are connected in series between the second reference potential and the second reference potential; When the second and fourth switches are on, the voltage value of the gate of the drive transistor when the reference current flows to the first node is stored in the normal mode. At times, when the second and fourth switches are conductive, the voltage of the stored value is supplied to the first node.
[0033]
According to a second aspect of the present invention, there are provided a plurality of pixel circuits arranged in a matrix, a data line wired for each column in the matrix arrangement of the pixel circuits, and a data signal supplied in accordance with luminance information. First and second reference potentials, and a plurality of supply means provided for each column with respect to the matrix arrangement of the pixel circuits and capable of supplying a predetermined reference current and a predetermined voltage to the pixel circuits of each column; The pixel circuit forms a current supply line between a first terminal and a second terminal connected to the first node, and the current supply line depends on a potential of a control terminal connected to the second node. A driving transistor for controlling a current flowing through the first node, a first switch connected to the first node, a second switch connected between the first node and the second node, The data line and the third node And a fourth switch connected between the first node and the supply means, and a third switch connected between the second node and the third node. A coupling capacitor connected between the first reference potential and the second reference potential, a current supply line of the driving transistor, the first node, the first switch, and the An electro-optical element is connected in series, and each of the supply means supplies the reference current to the first node when the second and fourth switches are in a conductive state in a voltage detection mode. The voltage value of the gate of the drive transistor at the time is stored, and the voltage of the stored value is supplied to the first node when the second and fourth switches are on in the normal mode. I do.
[0034]
Preferably, the supply means includes a reference current source, a current / voltage supply line to which a reference current or voltage is supplied, and a first node when the second and fourth switches are in a conductive state. A storage circuit capable of writing a gate voltage value of the drive transistor when the reference current flows, a voltage output circuit for outputting a voltage of a value stored in the storage circuit to the current voltage supply line, and a voltage detection circuit. In the mode, when the reference current source and the current voltage supply line are connected to each other and the reference current flows to the first node when the second and fourth switches are in a conductive state. The gate voltage value of the drive transistor is transmitted to and stored in the storage circuit through the current / voltage supply line, and in a normal mode, the voltage output circuit and the current / voltage supply line are connected to each other, The voltage value stored 憶回 path including a switch circuit for outputting to the current-voltage supply line.
[0035]
Preferably, in the normal mode, as the first stage, the second switch and the fourth switch are turned on for a predetermined time to electrically connect the first node and the second node, A voltage corresponding to the value stored in the first node is supplied, the second switch and the fourth switch are held in a non-conducting state as a second stage, and the third stage is charged as a third stage. After the switch is turned on and the first switch is turned on and data propagated through the data line is written to the third node, the third switch is held in a non-conductive state; A current corresponding to the data signal is supplied to the electro-optical element.
[0036]
Preferably, the operating frequency in the voltage detection mode is set lower than the operating frequency in the normal mode.
[0037]
Preferably, the value of the reference current is set to a value corresponding to an intermediate color of light emission of the electro-optical element.
[0038]
According to a third aspect of the present invention, there is provided an electro-optical element whose luminance changes according to a flowing current, a data line to which a data signal according to luminance information is supplied, first, second, and third nodes; A current supply line is formed between a first terminal and a second terminal connected to the first node, and a current flowing through the current supply line is controlled according to a potential of a control terminal connected to the second node. A driving transistor, a first switch connected to the first node, a second switch connected between the first node and the second node, the data line and the third switch. And a coupling capacitor connected between the second node and the third node, the third switch being connected between the first reference potential and the second reference node. Between the drive transistor and the reference potential of A method for driving a pixel circuit in which a supply line, the first node, the first switch, and the electro-optical element are connected in series, wherein the second switch is turned on for a predetermined time in a voltage detection mode. Then, the first node and the second node are electrically connected, a predetermined reference current is supplied to the first node, and the reference current flows to the first node. The voltage value of the gate of the drive transistor at that time is stored, and in the normal mode, the second switch is turned on for a predetermined time to electrically connect the first node and the second node; and Supplying a voltage corresponding to the value stored in the first node, holding the second switch in a non-conductive state after a lapse of a predetermined time, stopping the supply of the voltage, causing the third switch to be conductive, The first sui After the switch is turned on and the data transmitted through the data line is written to the third node, the third switch is kept in a non-conductive state, and the electro-optical element responds to the data signal. Supply current.
[0039]
According to the present invention, for example, in the voltage detection mode, the reference current flows through the current / voltage supply line by the current source.
Then, the second switch and the fourth switch are kept conductive. At this time, the second switch and the fourth switch are turned on, and the first node and the second node are connected to the reference current source through the current / voltage supply line and draw the reference current. The gate voltage value of the drive transistor is set so that the ON current matches the reference current.
As a result, the correction (auto-zero operation) is performed on all the pixels in which the threshold value and the mobility μ vary.
As described above, when the reference current is input to the pixel circuit and the threshold value Vt is corrected before normal image formation and use, the time of the Vth correction is set to about 100,000 times the normal time. By performing the operation for about 10 seconds, the reference current can be written without being affected by the variation of the threshold value Vth, even if the wiring capacity of the data line is large (heavy) on the large screen panel.
The gate voltage value of the drive transistor without this variation is written to the storage circuit.
This voltage value is stored in the storage circuit for each pixel circuit. This operation is performed on one screen, and the gate voltage values of all the pixels with respect to the reference voltages are extracted and stored.
[0040]
Next, in the normal mode in which normal image generation is performed, the voltage of the value stored in the storage circuit is supplied to the current / voltage supply line.
Then, the second switch and the fourth switch are kept conductive. At this time, the second switch and the fourth switch are turned on, the voltage of the stored value is supplied to the first node and the second node, and the gate voltage value of the drive transistor is set.
As a result, the correction (auto-zero operation) is performed on all the pixels in which the threshold value and the mobility μ vary.
Next, after the second and fourth switches are turned off and the auto-zero operation (Vth correction operation) is completed, for example, the first switch is turned on.
Further, the third switch is turned on by the first control line, and a data signal of a predetermined potential transmitted to the data line is applied to the coupling capacitor. As a result, the input data signal is coupled to the gate voltage of the drive transistor via the coupling capacitor, and a current having a value corresponding to the coupling voltage ΔV flows through the electro-optical element to emit light.
Then, the third switch is turned off.
[0041]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0042]
FIG. 1 is a block diagram showing a configuration of an organic EL display device employing a pixel circuit according to the present embodiment.
FIG. 2 is a circuit diagram showing a specific configuration of the pixel circuit according to the present embodiment in the organic EL display device of FIG.
[0043]
As shown in FIGS. 1 and 2, the display device 100 includes a pixel array unit 102 in which pixel circuits (PXLC) 101 are arranged in an m × n matrix, a horizontal selector (HSEL) 103, and a light scanner (WSCN). 104, a drive scanner (DSCN) 105, an auto-zero circuit (AZRD) 106, a reference current / voltage supply circuit (RIS / VOC) 107-1 to 107-n, and a data signal selected by the horizontal selector 103 and supplied according to luminance information is supplied. Data lines DTL101 to DTL10n, scanning lines WSL101 to WS10m selectively driven by the write scanner 104, drive lines DSL101 to DSL10m selectively driven by the drive scanner 105, auto-zero lines AZL101 to AZL10m selectively driven by the auto-zero circuit 106, You Reference current and the predetermined voltage by the fine reference current-voltage supply circuit 107-1 to 107-n has a current-voltage supply line IVSL101~IVSL10n selectively supplied.
[0044]
Note that, in the pixel array unit 102, the pixel circuits 101 are arranged in an m × n matrix, but in FIG. 1, for simplification of the drawing, the pixel circuits 101 are arranged in a 2 (= m) × 3 (= n) matrix. An example of arrangement is shown.
FIG. 2 also shows a specific configuration of one pixel circuit 101 and a reference current / voltage supply circuit 107-1 for simplification of the drawing.
[0045]
As shown in FIG. 2, the pixel circuit 101 according to the present embodiment includes p-channel TFTs 111 to 115, capacitors C111 and C112, a light emitting element 116 including an organic EL element (OLED: electro-optical element), a first node ND111, It has a second node ND112 and a third node ND113.
In FIG. 2, DTL 101 indicates a data line, WSL 101 indicates a scanning line, DSL 101 indicates a driving line, and AZL 101 indicates an auto-zero line.
Among these components, the TFT 111 constitutes a drive transistor according to the present invention, the TFT 112 constitutes a first switch, the TFT 113 constitutes a second switch, and the TFT 114 constitutes a third switch. The TFT 115 constitutes a fourth switch, and the capacitor C111 constitutes a coupling capacitor according to the present invention.
[0046]
The supply means is constituted by the reference current / voltage supply circuits 107-1 to 107-n.
For example, a reference current Iref (for example, 2 μA) is supplied to the current / voltage supply line IVSL101 before normal image extraction and use. The reference current Iref is set to a current value corresponding to an intermediate color of light emission of the light emitting element 116 so that the variation in mobility can be corrected.
When the reference current Iref is caused to flow through the current voltage supply line IVSL101 to correct the variation in the threshold Vth and the mobility, the gate voltage (the potential of the first and second nodes) of the TFT 111 as the drive transistor is changed to the current voltage It is detected as a terminal voltage of the supply line IVSL101 and written in the memory.
Then, when performing normal image output, the voltage of the value written in the memory is output to the current / voltage supply line IVSL101.
[0047]
Further, a supply line (power supply potential) of the power supply voltage VCC corresponds to a first reference potential, and the ground potential GND corresponds to a second reference potential.
[0048]
In the pixel circuit 101, a TFT 111, a first node ND111, a TFT 112, and a light emitting element 116 are connected in series between a power supply potential VCC and a ground potential GND.
Specifically, the source of the TFT 111 serving as a drive transistor is connected to the supply line of the power supply voltage VCC, and the drain is connected to the first node ND111. The source of the TFT 112 serving as a first switch is connected to the first node ND111, the drain is connected to the anode of the light emitting element 116, and the cathode of the light emitting element 116 is connected to the ground potential GND. The gate of the TFT 111 is connected to the second node ND112, and the gate of the TFT 112 is connected to the drive line DSL101.
The source / drain of the TFT 113 as a second switch is connected to the first node ND111 and the second node ND112, and the gate of the TFT 113 is connected to the auto-zero line AZL101.
The first electrode of the capacitor C111 is connected to the second node ND112, and the second electrode is connected to the third node ND113. The first electrode of the capacitor C112 is connected to the third node ND113, and the second electrode is connected to the power supply potential VCC.
The source / drain of the TFT 114 as a third switch is connected to the data line DTL101 and the third node ND113, and the gate of the TFT 114 is connected to the scanning line WSL101.
Further, the source / drain of the TFT 115 as a fourth switch is connected between the first node ND111 and the current / voltage supply line IVSL101, and the gate of the TFT 115 is connected to the auto-zero line AZL101.
[0049]
As shown in FIG. 2, the reference current / voltage supply circuit 107-1 (to 107-n) according to the present embodiment includes a reference current source I107, n-channel TFTs 1071 and 1072, a p-channel TFT 1073, and a storage circuit (MEM) 1074. , And a voltage follower circuit 1075 as a voltage output circuit.
The switch circuit according to the present invention is configured by the n-channel TFTs 1071 and 1072 and the p-channel TFT 1073.
[0050]
The TFT 1071 and the TFT 1072 are connected in series between one end T107 of the current / voltage supply line IVSL101 and the reference current source I107, and the TFT 1073 is connected between one end T107 of the current / voltage supply line IVSL101 and the output of the voltage follower circuit 1075. Have been.
Gates of the TFTs 1071 to 1073 are connected to a supply line of a selector pulse PSEL by a control system (not shown).
Further, a connection point ND107 between the TFT 1071 and the TFT 1072 (a connection point between the source and the drain) is connected to the voltage input / output line of the storage circuit.
[0051]
When storage circuit 1074 receives write command WR from a control system (not shown) and applies reference current Iref to current / voltage supply line IVSL101 in synchronization with clock signal CLK to correct variations in threshold value Vth and mobility. The gate voltage of the TFT 111 (the potential of the first and second nodes) as the drive transistor is detected as the terminal voltage of the current voltage supply line IVSL101, and the value is written.
The storage circuit 1074 receives a read command WR from a control system (not shown) and outputs a voltage signal corresponding to the stored voltage value to a non-inverting input (+) of the voltage follower circuit 1075.
[0052]
The voltage follower circuit 1075 is a circuit whose output is fed back to the inverting input (-), and outputs a voltage having a value corresponding to the voltage signal from the storage circuit 1074 to the current / voltage supply line IVSL101 via the TFT 1073.
[0053]
The selector pulse PSEL supplied by a control system (not shown) is set to a high level when the control system is issuing a write command WR, and is set to a low level when the control system is issuing a read command RD.
Further, the master clock signal of the panel is output when the control system (not shown) issues a write command WR, in other words, in the gate voltage detection mode before normal image formation and use. Is set to a frequency sufficiently lower than the field frequency of 60 Hz in the case where the image is output.
On the other hand, the master clock signal of the panel has a frequency corresponding to that when the control system (not shown) is issuing the read command WR, in other words, at the time of the normal node that performs the normal image display. The field frequency is set to 60 Hz.
[0054]
Next, the operation of the above configuration will be described focusing on the operation of the reference current / voltage supply circuit and the pixel circuit with reference to FIGS. 3, 4, and 5A to 5G.
FIG. 5A shows the scanning signal ws [1] applied to the scanning line WSL101 in the first row of the pixel array, and FIG. 5B shows the scanning signal ws [1] applied to the scanning line WSL102 in the second row of the pixel array. FIG. 5C shows the scanning signal ws [2], FIG. 5C shows the auto-zero signal az [1] applied to the auto-zero line AZL101 in the first row of the pixel array, and FIG. 5D shows the second row of the pixel array. 5E shows the auto-zero signal az [2] applied to the auto-zero line AZL102 of FIG. 5, and FIG. 5E shows the drive signal ds [1] applied to the first-line drive line DSL101 of the pixel array. 5D shows a drive signal ds [2] applied to the drive line DSL102 in the second row of the pixel array, and FIG. 5G shows the gate potential Vg of the TFT 111. Vo indicates a gate voltage value of the drive transistor TFT111 through which the reference current Iref flows.
Note that the operation of the pixel circuits in the first row will be described below.
[0055]
First, in a gate voltage detection mode before normal image formation and use, the selector pulse PSEL is set to a high level by a control system (not shown) and supplied to the reference current / voltage supply circuits 107-1 (to -n). Supplied. In parallel with this, a control system (not shown) issues a write command WR to the storage circuit 1074 of the reference current / voltage supply circuit 107-1 (-n).
At this time, in the reference current / voltage supply circuits 107-1 (to -n), the TFTs 1071 and 1072 are turned on and the TFT 1073 is turned off. Therefore, as shown in the equivalent circuit of FIG. 3, the reference current / voltage supply circuit 107-1 (to -n) has the reference current source I107 connected to the current / voltage supply line IVSL101 and the node ND107 connected to the storage circuit. It is configured to be connected to the voltage input / output line 1074.
At this time, the panel unit including the pixel array unit 102 takes about several tens of seconds, which is about 100,000 times that of correcting the threshold value Vth as will be described later, when performing normal image output. The frequency of the master clock signal is set as follows.
[0056]
In this state, constant current source 107 allows reference current Iref (for example, 2 μA) to flow through current voltage supply line IVSL101.
When the drive signal ds [1] to the drive line DSL101 is at a high level (the TFT 112 is non-conductive), the auto-zero signal az [1] to the auto-zero line AZL101 is at a low level, and the TFT 113 and the TFT 115 are made conductive.
[0057]
At this time, the TFT 115 is turned on, and the first node ND111 and the second node ND112 are connected to the reference current source I107 through the current / voltage supply line IVSL101 and draw the reference current Iref. The gate voltage Vo of the drive transistor TFT111 is set so as to match the reference current Iref.
As a result, the correction (auto-zero operation) is performed on all the pixels in which the threshold value and the mobility μ vary.
[0058]
The auto-zero signal az [1] to the auto-zero line AZL101 is set to a high level, and the TFT 113 and the TFT 115 are turned off to terminate the auto-zero operation (Vth correction operation).
[0059]
As described above, when the reference current Iref is input to the pixel array unit 102 before the normal image formation and use, and the threshold value Vt is corrected, as described above, the time of the Vth correction is normally set. The reference current Iref is not affected by the variation of the threshold value Vth, even if the wiring capacity of the data line is large (heavy) in a large screen panel, by performing the operation for about several tens of seconds which is about 100,000 times the Can write.
The gate potential of the TFT 111 having no variation is transmitted to the node ND107 via the TFTs 113 and 114 and the current / voltage supply line IVSL101, and the voltage value is written to the storage circuit 1074.
This voltage value is stored in the storage circuit 1074 for each pixel circuit. This operation is performed on one screen, and the gate voltage values for all the pixels with respect to the reference voltage Iref are extracted and stored.
[0060]
Next, in the normal mode in which normal image generation is performed, the selector pulse PSEL is set to a low level by a control system (not shown) and supplied to the reference current / voltage supply circuits 107-1 (to -n). . In parallel with this, a read command RD is issued from the control system (not shown) to the storage circuit 1074 of the reference current / voltage supply circuits 107-1 (-n).
At this time, in the reference current / voltage supply circuits 107-1 (to -n), the TFTs 1071 and 1072 are turned off, and the TFT 1073 is turned on. Therefore, in the reference current / voltage supply circuit 107-1 (-n), the output of the voltage follower circuit 1075 is connected to the current / voltage supply line IVSL101 as shown in the equivalent circuit of FIG. Are connected to the non-inverting input (+) of the voltage follower circuit 1075.
At this time, the frequency of the master clock signal in the panel section including the pixel array section 102 is set so that the threshold value Vth is corrected based on, for example, a field frequency of 60 Hz for normal image output.
[0061]
In this case, instead of the reference current Iref (for example, 2 μA) from the constant current source 107, a voltage corresponding to the voltage value stored in the storage circuit 1074 is supplied to the current / voltage supply line IVSL101 by the voltage follower circuit 1075. Output to the supply line IVSL101. This voltage value reflects a variation in the threshold value Vth of the TFT 111 for each pixel circuit.
[0062]
As shown in FIGS. 5C and 5E, when the drive signal ds [1] to the drive line DSL101 is at a high level (TFT 112 is in a non-conductive state), the auto-zero signal az [1] to the auto-zero line AZL101 is obtained. Is set to a low level, and the TFT 113 and the TFT 115 are made conductive.
[0063]
At this time, the TFT 115 is turned on, and the first node ND111 and the second node ND112 are supplied with a voltage reflecting a variation in the threshold value Vth of the TFT 111 for each pixel through the current voltage supply line IVSL101. .
As a result, the gate voltage Vo of the drive transistor TFT111 is set as shown in FIG. Writing of this voltage to each pixel circuit 101 is performed, for example, during a horizontal blanking period.
As a result, the correction (auto-zero operation) is performed on all the pixels in which the threshold value and the mobility μ vary.
[0064]
In this case, since the voltage is input, even if the wiring capacity of the data line is large in the large-screen panel, it is sufficiently charged in a short time of about the horizontal blanking period. This is equivalent to correcting the threshold value Vth based on the reference current Iref. Further, since the correction of the threshold value Vth is not affected at all by the variation of the threshold value Vth of the TFT 111 of each pixel circuit 101, the variation of the threshold value Vth and the variation of the mobility μ are completely canceled. Uniformity image quality can be obtained.
[0065]
As shown in FIG. 5C, the auto-zero signal az [1] to the auto-zero line AZL1 is set to a high level to turn off the TFT 113 and the TFT 115 to complete the auto-zero operation (Vth correction operation). ), The drive signal ds [1] to the drive line DSL1 is set to a low level, and the TFT 112 is turned on.
[0066]
Then, as shown in FIG. 5A, the scanning signal ws [1] to the scanning line WSL1 is set to a low level to make the TFT 114 conductive, and the data signal of a predetermined potential transmitted to the data line DTL101 is applied to the capacitor C111. Apply. Thereby, as shown in FIG. 5G, the input data signal is coupled to the gate voltage of the TFT 111 via the capacitor C111, and a current Ids having a value corresponding to the coupling voltage ΔV flows to the EL light emitting element 116, It emits light.
Then, as shown in FIG. 5A, the scanning line WSL101 is set at a high level, and the TFT 114 is turned off.
[0067]
FIG. 6 is a diagram illustrating a characteristic curve of ΔV (= Vgs−Vth) and a drain-source current Ids of drive transistors having different mobilities in the pixel circuit of FIG. 2.
In FIG. 6, the horizontal axis represents voltage ΔV, and the vertical axis represents current Ids. In FIG. 6, the curve shown by the solid line shows the characteristic of the pixel A, and the curve shown by the broken line shows the characteristic of the pixel B.
[0068]
As shown in FIG. 6, in the present pixel circuit, at the time of the variation correction (ΔV = 0) as described above, the drive transistor TFT 111 supplies the reference current Iref to the drive transistor TFT 111 even in pixels having different thresholds Vth and mobility μ. A corresponding current flows. Thereafter, an on-current corresponding to the coupling voltage ΔV flows.
This pixel circuit is equivalent to a conventional method in which a graph (FIG. 12) having a different mobility in the conventional method is translated and crossed with a current value Iref.
That is, the mobility μ varies around the reference current Iref, so that the variation in the ON current due to the mobility variation during white display is suppressed as shown in FIG. As a result, an organic EL panel having better uniformity can be obtained.
[0069]
FIG. 7 is a diagram illustrating a change in the gate voltage of the drive transistor during the auto-zero operation in the pixels C and D having different threshold values Vth of the drive transistor.
In FIG. 7, the horizontal axis represents time t, and the vertical axis represents the gate voltage Vg. In FIG. 7, the curve shown by the solid line shows the characteristic of the pixel C, and the curve shown by the broken line shows the characteristic of the pixel D.
[0070]
As described above, in the present pixel circuit, the gate potential Vg of the TFT 111 is determined so that a current corresponding to the reference current Iref flows, and the variation of the threshold value Vth is canceled.
As described above, the variation of the threshold value Vth is canceled while the current corresponding to the reference current Iref is flowing, so that the time until the cancellation of the Vth variation can be shorter than that of the conventional method, and the variation of the threshold value Vth can be reduced. Cancellation will not be incomplete, and no uniformity variation will occur.
Further, even after the variation of the threshold value Vth is canceled, as long as the TFT 115 is kept conductive, the voltage of the stored value is supplied and the reference current Iref continues to flow, and as shown in FIG. The voltage continues to be held.
That is, in the present pixel circuit, the gate voltage is kept being held, so that the gate voltage is kept being corrected with the variation in the threshold value Vth.
As a result, the threshold value Vth is corrected irrespective of the auto-zero setting time even for panels having different threshold values Vth. As a result, uniformity is improved.
[0071]
As described above, according to the present embodiment, the reference current line is connected to the drive transistor of the pixel through the switch, and the variation of the threshold value Vth is corrected. Variations in current can be suppressed, and uniformity with respect to mobility variations can be significantly improved as compared with the conventional method.
Further, since a voltage having a value reflecting the variation in the threshold value of the driving transistor of each pixel circuit is input to cancel the variation in the threshold value Vth, the variation in the threshold value Vth can be reduced as compared with the related art. This time is shortened, and deterioration of the uniformity due to the variation of the threshold value Vth can be prevented.
Further, once the variation in the threshold value is canceled, the gate potential does not change thereafter. Therefore, the auto-zero time does not depend on the absolute value of the threshold value Vth, and the man-hour increase due to the setting of the auto-zero time is suppressed. Can be.
Further, in the present embodiment, since the voltage is input, even if the wiring capacitance of the data line is large in the large-screen panel, it is possible to sufficiently charge the battery in a short time of about the horizontal blanking period. This is equivalent to correcting the threshold value Vth with reference to the reference current Iref. This correction of the threshold value Vth completely eliminates the influence of the variation in the threshold value Vth of the TFT 111 of each pixel circuit 101. As a result, the variation in the threshold value Vth and the variation in the mobility μ can be completely canceled in a short time, and a high uniformity image quality can be obtained.
Further, since only one current / voltage supply line is required for each pixel column, there is an advantage that the pixel layout becomes easy.
[0072]
In the present embodiment, the configuration has been described in which the reference current source is generated in a so-called display panel. However, the configuration may be such that the reference current Iref is supplied from outside the panel. In this case, for example, the reference current Iref is generated by an external MOSIC or the like and is input to the panel, so that the current value of each current voltage supply line has little variation.
[0073]
In this embodiment, the gate of the TFT 113 as the second switch and the gate of the TFT 115 as the fourth switch are connected to the auto-zero line AZL101 as the third control line. The gate of the TFT 113 as the fourth switch may be connected to the first auto-zero line AZL101-1, and the gate of the TFT 115 as the fourth switch may be connected to the second auto-zero line AZL101-2.
As described above, when the TFT 113 and the TFT 115 are turned on by different control lines, the turning-on timing does not affect the auto-zero operation, whichever comes first (after).
However, since the drive pulse can be reduced, it is preferable to turn on at the same timing by the common control line as in the present embodiment.
[0074]
Further, in the present embodiment, the drive control is performed so that the drive scan and the auto-zero do not overlap. However, the drive scan and the auto-zero may be overlapped. The overlap makes it possible to prevent the cutoff of the drive transistor TFT111.
In the present embodiment, the drive control is performed so that the drive scan is turned on before the light scan. However, the drive control is performed at the same time, and the drive scan may be performed after.
When drive scan is turned on before write scan, drive transistor TFT 111 is in saturation drive at the time of writing a signal voltage and the gate capacitance is reduced. Therefore, drive scan is turned on before write scan. Is preferred.
[0075]
In the above-described embodiment, as a layout of the auto-zero circuit (AZRD) 106, the write scanner (WSCN) 104, and the drive scanner (DSCN) 105, the auto-zero circuit (AZRD) 106 is disposed on the left side in the drawing of the pixel array unit 102. Although the case where the right scanner (WSCN) 104 and the drive scanner (DSCN) 105 are arranged on the right side has been described as an example, all are arranged on the left side or the right side, or the auto-zero circuit (AZRD) 106 is arranged on the right side. A light scanner (WSCN) 104 and a drive scanner (DSCN) 105 are arranged on the left side, or an auto-zero circuit (AZRD) 106 and a light scanner (WSCN) 104 or a drive scanner (DSCN) 105 are combined to the left. Rui is on can be made, various aspects of placing on the right side.
[0076]
【The invention's effect】
As described above, according to the present invention, it is possible to suppress the variation of the on-current due to the mobility at the time of white display, and to significantly improve the uniformity with respect to the variation of the mobility as compared with the conventional method. it can.
In addition, since the variation of the threshold value is canceled by inputting a voltage having a value reflecting the variation of the threshold value of the driving transistor for each pixel circuit, the time required for canceling the variation of the threshold value is reduced, Deterioration of uniformity due to threshold variation can be prevented.
Furthermore, once the variation of the threshold value is canceled, the gate potential of the driving transistor does not fluctuate thereafter, so the so-called auto-zero time does not depend on the absolute value of the threshold value, and the man-hour increase due to the setting of the auto-zero time is suppressed. can do.
[0077]
As described above, according to the present invention, it is possible to stably and accurately supply a current of a desired value to the light emitting element of each pixel irrespective of the variation of the mobility of the active element inside the pixel, in addition to the variation of the threshold value of the active element inside the pixel. As a result, a high-quality image can be displayed.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an organic EL display device employing a pixel circuit according to an embodiment.
FIG. 2 is a circuit diagram showing a specific configuration of a pixel circuit according to the embodiment in the organic EL display device of FIG.
FIG. 3 is a circuit diagram for explaining an operation in a gate voltage detection mode.
FIG. 4 is a circuit diagram for explaining an operation in a normal mode.
FIG. 5 is a timing chart for explaining the operation of the present embodiment.
6 is a diagram illustrating characteristic curves of ΔV (= Vgs−Vth) and a drain-source current Ids of drive transistors having different mobilities in the pixel circuit of FIG. 2;
7 is a diagram illustrating a change in a gate voltage of a drive transistor in an auto-zero operation in pixels having different threshold values Vth of the drive transistor in the pixel circuit of FIG. 2;
FIG. 8 is a block diagram illustrating a configuration of a general organic EL display device.
FIG. 9 is a circuit diagram illustrating a configuration example of a pixel circuit in FIG. 8;
FIG. 10 is a circuit diagram illustrating a configuration example of a pixel circuit having an auto-zero function.
FIG. 11 is a timing chart for explaining the operation of the circuit of FIG. 10;
12 is a diagram showing characteristic curves of ΔV (= Vgs−Vth) and drain-source current Ids of drive transistors having different mobilities in the pixel circuit of FIG. 10;
FIG. 13 is a diagram illustrating a change in the gate voltage of the drive transistor during an auto-zero operation in pixels having different threshold values Vth of the drive transistor.
FIG. 14 is a diagram for explaining a problem of the circuit in FIG. 10;
[Explanation of symbols]
100: display device, 101: pixel circuit (PXLC), 102: pixel array unit, 103: horizontal selector (HSEL), 104: light scanner (WSCN), 105: drive scanner (DSCN), 106: auto-zero circuit (AZRD) 107, a reference current / voltage supply circuit (RIS / VOC), 1071 to 1073, a TFT, 1074, a storage circuit, 1075, a voltage follower circuit, 111, a TFT as a driving transistor, 112, a TFT as a first switch, 113: TFT as a second switch, 114: TFT as a third switch, 115: TFT as a fourth switch, DTL101 to DTL10n: data lines, WSL101 to WSL10m: scanning lines, DSL101 to DSL10m: driving lines, AZL101 to AZL 0m ... auto-zero line, IVSL101~IVSL10n ... current voltage supply line.

Claims (12)

A pixel circuit for driving an electro-optical element whose luminance changes according to a flowing current,
A data line to which a data signal according to the luminance information is supplied,
First, second, and third nodes;
First and second reference potentials;
Supply means for selectively supplying a predetermined reference current and a predetermined voltage,
A current supply line is formed between a first terminal and a second terminal connected to the first node, and a current flowing through the current supply line is controlled according to a potential of a control terminal connected to the second node. A driving transistor,
A first switch connected to the first node;
A second switch connected between the first node and the second node;
A third switch connected between the data line and the third node;
A fourth switch connected between the first node and the supply means;
A coupling capacitor connected between the second node and the third node;
Has,
A current supply line of the driving transistor, the first node, the first switch, and the electro-optical element are connected in series between the first reference potential and the second reference potential;
In the voltage detection mode, when the second and fourth switches are in a conductive state, the supply means supplies a voltage value of a gate of the drive transistor when the reference current flows to the first node. A pixel circuit that supplies the voltage of the stored value to the first node when the second and fourth switches are in a conductive state in a normal mode. The supply means includes: a reference current source;
A current / voltage supply line to which the reference current or voltage is supplied;
A memory circuit capable of writing a gate voltage value of the drive transistor when the reference current flows to the first node when the second and fourth switches are in a conductive state;
A voltage output circuit that outputs a voltage having a value stored in the storage circuit to the current / voltage supply line;
In the voltage detection mode, the reference current source is connected to the current / voltage supply line, and the reference current flows to the first node when the second and fourth switches are in a conductive state. The gate voltage value of the driving transistor at the time is transmitted to the memory circuit through the current voltage supply line and stored, and in the normal mode, the voltage output circuit and the current voltage supply line are connected, and the memory circuit is connected to the memory circuit. 2. The pixel circuit according to claim 1, further comprising: a switch circuit that outputs a voltage having a stored value to the current / voltage supply line. In normal mode,
As a first stage, the second switch and the fourth switch are turned on for a predetermined time to electrically connect the first node and the second node, and to store the data in the first node. Supply the voltage corresponding to the value,
As a second stage, the second switch and the fourth switch are kept in a non-conductive state,
In the third stage, after the third switch is turned on, the first switch is turned on, and data transmitted through the data line is written to the third node, the third switch is turned on. The pixel circuit according to claim 1, wherein a switch is kept in a non-conductive state, and supplies a current corresponding to the data signal to the electro-optical element. 2. The pixel circuit according to claim 1, wherein an operation frequency in the voltage detection mode is set lower than an operation frequency in the normal mode. 2. The pixel circuit according to claim 1, wherein the value of the reference current is set to a value corresponding to an intermediate color of light emission of the electro-optical element. A plurality of pixel circuits arranged in a matrix,
A data line wired for each column with respect to the matrix arrangement of the pixel circuits and supplied with a data signal corresponding to luminance information;
First and second reference potentials;
A plurality of supply means provided for each column with respect to the matrix arrangement of the pixel circuits, and capable of supplying a predetermined reference current and a predetermined voltage to the pixel circuits of each column;
The pixel circuit,
A current supply line is formed between a first terminal and a second terminal connected to the first node, and a current flowing through the current supply line is controlled according to a potential of a control terminal connected to the second node. A driving transistor,
A first switch connected to the first node;
A second switch connected between the first node and the second node;
A third switch connected between the data line and the third node;
A fourth switch connected between the first node and the supply means;
A coupling capacitor connected between the second node and the third node;
A current supply line of the driving transistor, the first node, the first switch, and the electro-optical element are connected in series between the first reference potential and the second reference potential;
In the voltage detection mode, when the second and fourth switches are in a conductive state, each of the supply means is configured to supply a voltage of a gate of the drive transistor when the reference current flows to the first node. A display device which stores a value and supplies the voltage of the stored value to the first node when the second and fourth switches are on in a normal mode. The supply means includes: a reference current source;
A current-voltage supply line provided for each column with respect to the matrix arrangement of the pixel circuits and supplied with a reference current or voltage;
A memory circuit capable of writing a gate voltage value of the drive transistor when the reference current flows to the first node when the second and fourth switches are in a conductive state;
A voltage output circuit that outputs a voltage having a value stored in the storage circuit to the current / voltage supply line;
In the voltage detection mode, the reference current source is connected to the current / voltage supply line, and the reference current flows to the first node when the second and fourth switches are in a conductive state. The gate voltage value of the driving transistor at the time is transmitted to the memory circuit through the current voltage supply line and stored, and in the normal mode, the voltage output circuit and the current voltage supply line are connected, and the memory circuit is connected to the memory circuit. 7. The display device according to claim 6, further comprising: a switch circuit that outputs a voltage having a stored value to the current / voltage supply line. In normal mode,
As a first stage, the second switch and the fourth switch are turned on for a predetermined time to electrically connect the first node and the second node, and to store the data in the first node. Supply the voltage corresponding to the value,
As a second stage, the second switch and the fourth switch are kept in a non-conductive state,
In the third stage, after the third switch is turned on, the first switch is turned on, and data transmitted through the data line is written to the third node, the third switch is turned on. 7. The display device according to claim 6, wherein a switch is kept in a non-conductive state, and supplies a current corresponding to the data signal to the electro-optical element. 7. The display device according to claim 6, wherein an operation frequency in the voltage detection mode is set lower than an operation frequency in the normal mode. 7. The display device according to claim 6, wherein the value of the reference current is set to a value corresponding to an intermediate color of light emission of the electro-optical element. An electro-optical element whose luminance changes according to a flowing current;
A data line to which a data signal according to the luminance information is supplied,
First, second, and third nodes;
A current supply line is formed between a first terminal and a second terminal connected to the first node, and a current flowing through the current supply line is controlled according to a potential of a control terminal connected to the second node. A driving transistor,
A first switch connected to the first node;
A second switch connected between the first node and the second node;
A third switch connected between the data line and the third node;
A coupling capacitor connected between the second node and the third node;
Has,
A pixel in which the current supply line of the driving transistor, the first node, the first switch, and the electro-optical element are connected in series between the first reference potential and the second reference potential A method of driving a circuit,
In voltage detection mode,
Turning on the second switch for a predetermined time to electrically connect the first node and the second node, and supplying a predetermined reference current to the first node; The voltage value of the gate of the drive transistor when the reference current is passed is stored,
In normal mode,
Turning on the second switch for a predetermined time to electrically connect the first node and the second node, and supplying a voltage corresponding to a value stored in the first node;
After the lapse of a predetermined time, the second switch is kept in a non-conductive state, the supply of the voltage is stopped,
After the third switch is turned on and the first switch is turned on to write data propagated through the data line to the third node, the third switch is held in a non-conductive state. A method for driving a pixel circuit for supplying a current corresponding to the data signal to the electro-optical element. 12. The method according to claim 11, wherein an operating frequency in the voltage detection mode is set lower than an operating frequency in the normal mode.

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