JP2004356213A - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device Download PDF

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Publication number
JP2004356213A
JP2004356213A JP2003149446A JP2003149446A JP2004356213A JP 2004356213 A JP2004356213 A JP 2004356213A JP 2003149446 A JP2003149446 A JP 2003149446A JP 2003149446 A JP2003149446 A JP 2003149446A JP 2004356213 A JP2004356213 A JP 2004356213A
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light emitting
semiconductor light
layer
emitting device
emitting element
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JP4277583B2 (en
Inventor
Masaharu Yasuda
正治 安田
Nobuyuki Takakura
信之 高倉
Kazunari Kuzuhara
一功 葛原
Takanori Akeda
孝典 明田
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light emitting device which is capable of restraining a semiconductor light emitting element from deteriorating due to heat released from it when it emits light using light emitted from the element more effectively, manufactured at a low cost, and reduced in size. <P>SOLUTION: The semiconductor light emitting device is equipped with a semiconductor light emitting element which contains a GaN semiconductor as a component element and is positioned on the bottom of a cone-shaped hollow provided to a support substrate. A silicon substrate is used as the above support substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、半導体発光装置に関し、詳しくは、特に青色または紫外発光素子を内蔵した半導体発光装置に関するものである。
【0002】
【従来の技術】
従来から、半導体発光装置としては、例えば特許文献1や特許文献2に開示の構成を有するものが知られている。これらの特許文献に開示の装置は、青色半導体発光装置の一例であり、絶縁性の回路基板上に、半導体発光素子が設置された構造を有している。
【0003】
従来の半導体発光装置に使用されている絶縁性基板としては、アルミナなどのセラミックス基板が一般的であるが、これらのセラミックス基板は熱伝導率が低い。従って、発光の際に発生した熱を排出させる作用が小さく、この熱によって半導体発光素子の劣化が問題となる場合があった。
【0004】
上記特許文献2の半導体発光装置では、半導体発光素子を封止するための樹脂封止体と配線基板の間に間隙を設け、該間隙から放熱することとしている。このように発光の際の発熱の問題を回避するには、上記の如き特殊な構造を採用する必要があった。
【0005】
また、半導体発光装置では、通常、半導体発光素子から発生する光の一部は、素子側面から漏れるなどし、該装置の構成部材に吸収される。このため、半導体発光素子から放射される光のうち、半導体発光装置の外部へ取り出して有効に活用し得る割合が低くなるといった問題もあった。
【0006】
【特許文献1】
特開平11−340517号公報
【特許文献2】
特開2002−208737号公報
【0007】
【発明が解決しようとする課題】
本発明は、上記事情に鑑みてなされたものであり、その目的は、発光の際に発生する熱による半導体発光素子の劣化を抑制でき、また、該素子から放射された光をより有効に活用し得ると共に、低コスト化と小型化を達成し得る半導体発光装置を提供することにある。
【0008】
【課題を解決するための手段】
本発明の半導体発光装置は、内面が擂鉢状の凹部を有する支持基板の該凹部の底面上に、GaN系半導体を構成要素に含む半導体発光素子を有する半導体発光装置であって、前記支持基板はシリコン基板であるところに特徴を有するものである。
【0009】
本発明の半導体発光装置では、支持基板が熱伝導に優れるシリコン基板であるため、該シリコン基板を通じて発光時に発生する熱を効果的に排出することができ、半導体発光素子の熱劣化を抑制し得る。また、上記支持基板であるシリコン基板は、従来のセラミックス基板に比べて安価であるため、低コスト化を達成できる。
【0010】
さらに、上記支持基板上には、半導体発光素子を駆動するための駆動回路などを設けることも可能であるため、半導体発光装置を小型化することができる。
【0011】
加えて、上記支持基板の有する凹部の傾斜面で、半導体発光素子の側面から漏れる光を反射して、装置外部に取り出すことができる。よって、半導体発光素子から放射された光のうち、装置外部に取り出して有効に活用し得る光の割合(以下、「光の取り出し効率」という場合がある)を高めることができる。
【0012】
【発明の実施の形態】
<第1実施形態>
図1は、本発明の半導体発光装置の第1実施形態を示す平面模式図であり、図2は図1のA−A線断面をより詳細に示した模式図である。この第1実施形態に係る半導体発光装置10aでは、内面が擂鉢状の凹部を有するシリコン基板である支持基板101の該凹部底面に半導体発光素子102が固着されており、支持基板101の一部と半導体発光素子102は、封止樹脂109で封止されている。
【0013】
半導体発光素子102は、透光性基板103上に、n層104、発光層105、p層106が順次積層されてなるGaN系半導体を構成要素に備え、さらにp層106表面にp型電極108を有すると共に、p層106側からn層104の一部が露出するように露出面が形成されており、該露出面にn型電極107を有している。
【0014】
この半導体発光素子102は、n層104と支持基板101との間に透光性基板103が介在するように該支持基板101に固着されており、さらにワイヤボンド110によって支持基板101と電気的に接続されている。支持基板101には、電源(安定電源114)が接続されている。ワイヤボンドによる支持基板への接続は、図2に示すように支持基板の上記凹部以外の箇所であってもよく、該凹部の傾斜面であっても構わない。
【0015】
安定電源114によってn型電極107とp型電極108の間に順方向バイアスを印加する(すなわち、p型電極に正電圧を印加する)ことにより、発光層105内で電子とホールが結合して、青色若しくは紫外(波長:500〜250nm)の光が発生し、この光が、封止樹脂109を通して装置外部に取り出される。このとき、半導体発光素子102の側面側に向かう光が、支持基板101の傾斜面111によって装置上部側(装置外部側)へ反射される(図2中、a1)ため、かかる光も取り出される。よって、素子内部で発生した光の取り出し効率を高めることができる。
【0016】
支持基板101、すなわちシリコン基板の上記凹部は、公知の異方性エッチングによって形成できる。異方性エッチングとは、結晶面の方向によってエッチング速度が異なるというシリコンの特性を利用して、該結晶面を基準とする微細構造を形成する技術である。上記凹部は、例えばKOH水溶液を用いて、単結晶シリコンの(100)面をエッチングし、(111)面を出すことで形成できる。上記凹部の形状(例えば開口面積や深さ)は、エッチングマスクの形状や、エッチングの時間の調節によりエッチング深さを制御することで調整できる。
【0017】
次に、半導体発光素子102について説明する。透光性基板103の素材としてはサファイアが一般的である。透光性基板の厚みは、通常、30〜500μmである。
【0018】
n層104は、n型GaN系化合物半導体からなる層であり、具体的には、AlInGa1−a−bN(0≦a,0≦b,a+b≦1)で表される化合物から構成される。例えば、aが0.5以下であるAlGa1−aNや、bが0.5以下であるInGa1−bNが好ましい。
【0019】
なお、図2では、n層104は単一の層として示したが、該n層が、支持基板側から、n型コンタクト層、n型クラッド層の順に積層された積層構造を有していてもよい。この場合、n型電極107を形成するための露出面は、n型コンタクト層が露出するように形成する。n型コンタクト層としては、n層を構成する上記化合物の中でもGaNが一般的である。また、n型クラッド層としては、n層を構成する上記化合物のうち、Al0.3Ga0.7NやAlN、GaNなどが一般的である。
【0020】
また、上記単層構造のn層、およびn型コンタクト層並びにn型クラッド層には、Si、Ge,Sなどのn型不純物をドープすることが、キャリア濃度を高め得ることなどから望ましい。
【0021】
n層の厚みとしては、n層が単層構造の場合には、0.5〜10μmが一般的である。また、n層がn型コンタクト層とn型クラッド層の積層構造である場合には、n型コンタクト層の厚みは0.2〜10μmが一般的であり、n型クラッド層の厚みは特に限定されないが、通常は、0.01〜3μmである。
【0022】
発光層105は、GaN系化合物半導体からなる層であり、具体的には、AlInGa1−c−dN(0≦c,0≦d,c+d≦1)で表される化合物から構成される。この発光層において、例えば、上記化合物のInとAlの組成比を調節することにより、また、該発光層にSi、Ge、Sなどのn型不純物や、Mg、Znなどのp型不純物をドープすることにより、発生する光の波長を青色から紫外の範囲で調整することができる。
【0023】
なお、図2では、発光層105は単一の層で示したが、例えば、発光層を複数層からなる積層構造とし、各層を構成する化合物の組成を変えた所謂多重量子井戸構造とすることも好ましい。発光層の厚みは全厚みで、0.001〜0.5μmとすることが一般的である。
【0024】
p層106は、p型GaN系化合物半導体からなる層である。図2ではp層106は単一の層として示したが、発光層側から、p型クラッド層、p型コンタクト層の順に積層された積層構造を有するものが一般的である。
【0025】
p型クラッド層は、例えば、AlGa1−eN(0<e≦1)で表される化合物により構成され、さらにp型不純物がドープされている。eは0.05以上であることが好ましい。p型コンタクト層は、例えば、p型不純物がドープされたp型GaNにより構成される。これらp型クラッド層およびp型コンタクト層にドープされるp型不純物は、Mg、Znなどが挙げられる。p型クラッド層の厚みは、通常、0.001〜1.5μmであり、p型コンタクト層の厚みは0.01〜2μmが一般的である。
【0026】
半導体発光装置102のn型電極107およびp型電極108の素材は、夫々n層、p層と電気的に接続可能なものであれば特に限定されないが、n型電極としては、例えばV層とAu層の積層構造(Au層が最表層)のものなどが一般的である。この場合、各層の厚みは、通常、V層:0.1〜0.5μm、Au層:1〜3μmである。また、p型電極としては、例えばNi層とAu層の積層構造(Auが最表層)のものなどが一般的である。この場合、各層の厚みは、通常、Ni層:0.1〜0.5μm、Au層:1〜3μmである。
【0027】
n層102、発光層103およびp層104を形成するに当たっては、気相成長法[有機金属気相成長法(MOCVD法)など]などの公知の製膜法を採用することができる。n層への上記n型不純物のドーピング、およびp層への上記p型不純物のドーピングは、これらの層の形成(気相成長)の際に行う。
【0028】
なお、図2には示さないが、支持基板がサファイア基板の場合、n層を直接形成することは困難であるため、n層と支持基板の間にバッファ層を設けることが好ましい。かかるバッファ層は、支持基板とn層との格子不整合を緩和する作用を有するものであり、このバッファ層の存在により、n層の形成(n型GaN系化合物半導体結晶の成長)を良好に進めることが可能となる。バッファ層としては、例えば、GaN、AlN、GaAlN、ZnOなどが挙げられる。ちなみに、GaNを用いてn層を気相成長法により形成する際に、まず低温条件で製膜を行ってバッファ層を形成し、その後温度を高めてn層を形成する二段階成長法を採用することで、バッファ層とn層を、より簡便に形成できる。バッファ層の厚みは、通常、0.001〜1μmである。
【0029】
n型電極を形成するためのn層の露出面は、フォトレジストを利用したエッチング法などにより形成することができる。また、p型電極およびn型電極は、公知の蒸着法などにより形成すればよい。
【0030】
半導体発光素子102を支持基板101に固着する方法は特に限定されないが、 、図1および図2に示すように、ワイヤボンドで半導体発光素子を支持基板と電気的に接続する場合では、公知のダイボンディング法などが採用可能である。また、所謂フリップチップ接合によって、半導体発光素子を支持基板に固着すると共に電気的に接続してもよい。
【0031】
なお、図1および図2にあるように、傾斜面111の一部または全部に反射膜として作用し得る金属膜112を設けておくことで、装置上部側への光の反射効率をより高めることができる。
【0032】
金属膜112を構成する素材としては、半導体発光素子から発生する光の反射率が60%以上のものが好ましく、例えば、Al、Ag、Rhなどが挙げられる。金属膜112は、公知の蒸着法などにより形成できる。
【0033】
さらに、上記凹部の底面における半導体発光素子102の形成部周囲には、粗面構造113が形成されていることが好ましい。この粗面構造113により、半導体発光素子102から発生し支持基板101側に向かう光を、乱反射させ、装置上部側に向けたり(図2中、a2)、傾斜面111(金属膜112)側へ向け、該傾斜面111(金属膜112)で更に装置上部側へ反射させたりすることができるため、光の取り出し効率をより高めることが可能となる。
【0034】
粗面構造113は、支持基板101側へ向かう光を乱反射できればよいため、その形状・構成は特に限定されない。例えば図1および図2に示すような形状の突起が複数存在する構成であっても良く、連続した壁のような形状であって、半導体発光素子の形成部の周囲を取り囲むように形成された構成であっても構わない。ただし、支持基板側へ向かう光を、より効果的に乱反射させるためには、図1および図2に示すような形状の突起が複数存在する構成であることが望ましい。
【0035】
粗面構造113は、支持基板101に上述の異方性エッチングを施して上記凹部を形成する際に、エッチング条件を調節することで形成させることができる。
【0036】
また、図1および図2には示さないが、上記凹部の底面に上述の金属膜(反射膜)を設けることも好ましく、この場合には、支持基板側に向かう光を、より有効に装置上部側に反射することができる。かかる金属膜も公知の蒸着法などで形成できる。
【0037】
<第2実施形態>
図3は、本発明の半導体発光装置の第2実施形態を示す平面模式図であり、図4は図1のB−B線断面をより詳細に示した模式図である。第1実施形態と同じ機能を有する部分については、同一符号を付して、重複説明を避ける。第2実施形態は、以下の点に特徴を有している。
【0038】
第2実施形態の半導体発光装置10bでは、半導体発光素子102を駆動するための駆動回路を、支持基板101の駆動回路形成部116に有している。これにより、半導体発光装置内に上記駆動回路を設ける場合には、支持基板101の外部に該駆動回路を設ける必要がなく、半導体発光装置の小型化を図ることが可能となる。
【0039】
なお、支持基板101の上記凹部の傾斜面111に、駆動回路を形成するためのパターンを設けている場合には、該傾斜面に金属膜(反射層)を直接形成すると、電流がリークして半導体発光素子の発光が阻害されることがあるため、図4に示すように、傾斜面111と金属膜112の間には、SiO膜などの絶縁膜115を設けることが好ましい。
【0040】
また、支持基板101に設ける駆動回路は特に限定されないが、例えば、必要に応じて電流値を下げるための抵抗などを有する回路などが挙げられる。また、交流電源を採用する場合には、上記回路にAC/DC変換回路を組み合わせた回路などが適用できる。
【0041】
図5に、半導体発光素子102と駆動回路117を含む本発明の半導体発光装置の等価回路の例を示す。本発明の半導体発光装置では、第1実施形態、第2実施形態、さらには後述の第3実施形態のいずれにおいても、図5に示すように、半導体発光素子102は、ダイオード(ツェナーダイオード)118と並列に接続されていることが好ましい。このような構成を採用することで、過電圧が加わった際の半導体発光素子102の破損を防止することができる。
【0042】
<第3実施形態>
図6は、本発明の半導体発光素子の第3実施形態を示す断面模式図である。第3実施形態の半導体発光装置10cでは、上述の異方性エッチングにより上記凹部を形成した支持基板101の該凹部の底面に、SiCまたはAlInGa1−X−YN(0≦X≦1,0≦Y≦1,0≦1−X−Y≦1)薄膜119を介して、n層104、発光層105、p層106、p型電極108が順次形成されてなる半導体発光素子102が設けられている。
【0043】
n型電極107は、支持基板101上に設けられており、拡散層120およびSiCまたはAlInGa1−X−YN(0≦X≦1,0≦Y≦1,0≦1−X−Y≦1)薄膜119を介してn層106と電気的に接続されている。支持基板101の拡散層120は、不純物を拡散させてあり、これにより他の部分よりも電気抵抗が小さいため、電流が流れ得る。拡散層120は、ボロンなどの不純物をイオン注入などし、その後熱処理を施す方法などにより形成できる。拡散層の深さは、通常、0.5μm以下程度である。
【0044】
図6では図示しないが、支持基板101の一部および半導体発光素子102は、第1実施形態や第2実施形態と同様に封止樹脂で封止する。
【0045】
半導体発光素子102に係るn層104、発光層105、p層106、n型電極107およびp型電極108の構成、素材、厚みおよび形成方法は、第1実施形態と同様であるが、この第3実施形態の半導体発光装置10cでは、これら半導体発光素子102の構成要素を、支持基板101上に直接形成することができる。よって、上述のダイボンディング法などにより、半導体発光素子102を支持基板101に固着する工程を省略し得る。
【0046】
なお、上述の気相成長法などにより、支持基板であるシリコン基板に直接n層を形成させようとしても、n層形成成分がシリコン基板中に拡散してしまい、層を形成し難い。そのため、SiCまたはAlInGa1−X−YN(0≦X≦1,0≦Y≦1,0≦1−X−Y≦1)薄膜119を、n層104形成のための保護層として、支持基板101上に設ける。AlInGa1−X−YN(0≦X≦1,0≦Y≦1,0≦1−X−Y≦1)薄膜の好適な具体例としては、GaN、AlNなどが挙げられる。
【0047】
このSiCまたはAlInGa1−X−YN(0≦X≦1,0≦Y≦1,0≦1−X−Y≦1)薄膜も、n層などと同様に、上述の気相成長法(MOCVD法など)などで形成することができる。かかる薄膜の厚みは、10μm以下とすることが好ましく、0.1〜3μm以下とすることがより好ましい。
【0048】
また、第1実施形態と同様に、支持基板101の上記凹部の傾斜面に金属膜を設けたり、上記凹部底面の半導体発光素子102の形成部の周囲に粗面構造や金属膜を形成しておくことも、光の取り出し効率を高め得る観点から好ましい。さらに、第2実施形態と同様に、支持基板101上に半導体発光素子102を駆動するための駆動回路を設けることも、半導体発光装置の小型化を達成できることから推奨される。
【0049】
【発明の効果】
本発明の半導体発光装置では、支持基板が、熱伝導に優れるシリコン基板であるため、該シリコン基板を通じて発光時に発生する熱を効果的に排出することができ、半導体発光素子の熱劣化を抑制し得る。また、上記支持基板であるシリコン基板は、従来のセラミックス基板に比べて安価であるため、低コスト化を達成できる。
【0050】
さらに、上記支持基板上には、半導体発光素子を駆動するための駆動回路などを設けることも可能であるため、半導体発光装置を小型化することができる。
【0051】
加えて、上記支持基板の有する凹部の傾斜面で、半導体発光素子の側面から漏れる光を反射して、装置外部に取り出すことができるため、該素子から放射された光をより有効に活用することができる。
【図面の簡単な説明】
【図1】本発明の半導体発光装置の第1実施形態を示す平面模式図である。
【図2】図1のA−A線断面模式図である。
【図3】本発明の半導体発光装置の第2実施形態を示す平面模式図である。
【図4】図2のB−B線断面模式図である。
【図5】本発明の半導体発行装置の等価回路の一例を示す図である。
【図6】本発明の半導体発光装置の第3実施形態を示す断面模式図である。
【符号の説明】
10a 10b 10c 半導体発光装置
101 支持基板
102 半導体発光素子
103 透光性基板
104 n層
105 発光層
106 p層
107 n型電極
108 p型電極
109 封止樹脂
110 ワイヤボンド
111 傾斜面
112 金属膜
113 粗面構造
114 安定電源
115 絶縁膜
116 駆動回路形成部
117 駆動回路
118 ダイオード
119 SiCまたはAlInGa1−X−YN(0≦X≦1,0≦Y≦1,0≦1−X−Y≦1)薄膜
120 拡散層
a1 金属膜により装置上部側へ反射される光の経路
a2 粗面構造により装置上部側へ反射される光の経路
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor light emitting device, and more particularly, to a semiconductor light emitting device incorporating a blue or ultraviolet light emitting element.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as a semiconductor light emitting device, one having a configuration disclosed in Patent Document 1 or Patent Document 2, for example, is known. The devices disclosed in these patent documents are examples of a blue semiconductor light emitting device, and have a structure in which a semiconductor light emitting element is provided on an insulating circuit board.
[0003]
As an insulating substrate used in a conventional semiconductor light emitting device, a ceramic substrate such as alumina is generally used, but these ceramic substrates have low thermal conductivity. Therefore, the action of discharging the heat generated at the time of light emission is small, and this heat may cause a problem of deterioration of the semiconductor light emitting element.
[0004]
In the semiconductor light emitting device of Patent Document 2, a gap is provided between a resin sealing body for sealing the semiconductor light emitting element and the wiring board, and heat is radiated from the gap. In order to avoid the problem of heat generation at the time of light emission, it is necessary to adopt the special structure as described above.
[0005]
In a semiconductor light emitting device, a part of light generated from a semiconductor light emitting element usually leaks from a side surface of the element and is absorbed by constituent members of the device. For this reason, there is a problem that the ratio of light emitted from the semiconductor light emitting element that can be extracted to the outside of the semiconductor light emitting device and used effectively is reduced.
[0006]
[Patent Document 1]
JP-A-11-340517 [Patent Document 2]
JP 2002-208737 A
[Problems to be solved by the invention]
The present invention has been made in view of the above circumstances, and an object of the present invention is to suppress deterioration of a semiconductor light emitting device due to heat generated during light emission, and to more effectively utilize light emitted from the device. It is another object of the present invention to provide a semiconductor light emitting device that can achieve cost reduction and downsizing while being able to perform the operations.
[0008]
[Means for Solving the Problems]
The semiconductor light emitting device of the present invention is a semiconductor light emitting device having a semiconductor light emitting element including a GaN-based semiconductor as a component on a bottom surface of a concave portion of a support substrate having a mortar-shaped concave portion on the inner surface, wherein the support substrate is The feature is that it is a silicon substrate.
[0009]
In the semiconductor light emitting device of the present invention, since the supporting substrate is a silicon substrate having excellent heat conduction, heat generated during light emission can be effectively discharged through the silicon substrate, and thermal degradation of the semiconductor light emitting element can be suppressed. . In addition, the silicon substrate as the support substrate is inexpensive as compared with a conventional ceramic substrate, so that cost reduction can be achieved.
[0010]
Further, a driving circuit or the like for driving the semiconductor light emitting element can be provided on the supporting substrate, so that the size of the semiconductor light emitting device can be reduced.
[0011]
In addition, the light leaking from the side surface of the semiconductor light emitting element can be reflected on the inclined surface of the concave portion of the support substrate and taken out of the device. Therefore, of the light emitted from the semiconductor light emitting element, the ratio of light that can be extracted to the outside of the device and effectively used (hereinafter, may be referred to as “light extraction efficiency”) can be increased.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
<First embodiment>
FIG. 1 is a schematic plan view showing a first embodiment of the semiconductor light emitting device of the present invention, and FIG. 2 is a schematic diagram showing a cross section taken along line AA of FIG. 1 in more detail. In the semiconductor light emitting device 10a according to the first embodiment, a semiconductor light emitting element 102 is fixed to a bottom surface of a concave portion of a support substrate 101 which is a silicon substrate having a mortar-shaped concave portion on the inner surface. The semiconductor light emitting element 102 is sealed with a sealing resin 109.
[0013]
The semiconductor light-emitting element 102 includes a GaN-based semiconductor in which an n-layer 104, a light-emitting layer 105, and a p-layer 106 are sequentially stacked on a light-transmitting substrate 103 as a component, and further includes a p-type electrode 108 on the surface of the p-layer 106. And an exposed surface is formed so that a part of the n-layer 104 is exposed from the p-layer 106 side, and the n-type electrode 107 is provided on the exposed surface.
[0014]
The semiconductor light-emitting element 102 is fixed to the support substrate 101 so that a light-transmitting substrate 103 is interposed between the n-layer 104 and the support substrate 101, and is electrically connected to the support substrate 101 by wire bonds 110. It is connected. A power source (stable power source 114) is connected to the support substrate 101. The connection to the support substrate by wire bonding may be at a position other than the above-described concave portion of the support substrate as shown in FIG. 2 or may be an inclined surface of the concave portion.
[0015]
When a forward bias is applied between the n-type electrode 107 and the p-type electrode 108 by the stable power supply 114 (that is, a positive voltage is applied to the p-type electrode), electrons and holes are combined in the light emitting layer 105. Then, blue or ultraviolet light (wavelength: 500 to 250 nm) is generated, and this light is extracted to the outside of the device through the sealing resin 109. At this time, light traveling toward the side surface of the semiconductor light emitting element 102 is reflected by the inclined surface 111 of the support substrate 101 toward the upper side of the device (outside of the device) (a1 in FIG. 2), so that the light is also extracted. Therefore, the efficiency of extracting light generated inside the element can be increased.
[0016]
The support substrate 101, that is, the concave portion of the silicon substrate can be formed by known anisotropic etching. Anisotropic etching is a technique for forming a microstructure based on the crystal plane by utilizing the characteristic of silicon that the etching rate varies depending on the direction of the crystal plane. The recess can be formed by etching the (100) plane of single-crystal silicon to expose the (111) plane using, for example, a KOH aqueous solution. The shape (for example, opening area and depth) of the concave portion can be adjusted by controlling the etching depth by adjusting the shape of the etching mask and the etching time.
[0017]
Next, the semiconductor light emitting device 102 will be described. Sapphire is generally used as a material of the light-transmitting substrate 103. The thickness of the translucent substrate is usually 30 to 500 μm.
[0018]
n layer 104 is a layer formed from n-type GaN-based compound semiconductor, specifically, expressed by Al a In b Ga 1-a -b N (0 ≦ a, 0 ≦ b, a + b ≦ 1) Consists of compounds. For example, a can or Al a Ga 1-a N is 0.5 or less, b is In b Ga 1-b N is preferably 0.5 or less.
[0019]
Although the n-layer 104 is shown as a single layer in FIG. 2, the n-layer has a laminated structure in which an n-type contact layer and an n-type clad layer are laminated in this order from the support substrate side. Is also good. In this case, the exposed surface for forming the n-type electrode 107 is formed such that the n-type contact layer is exposed. As the n-type contact layer, GaN is generally used among the above compounds constituting the n-layer. In addition, as the n-type cladding layer, Al 0.3 Ga 0.7 N, AlN, GaN, or the like is generally used among the above-described compounds constituting the n-layer.
[0020]
It is desirable that the n-layer, the n-type contact layer, and the n-type clad layer having the single-layer structure be doped with an n-type impurity such as Si, Ge, or S because the carrier concentration can be increased.
[0021]
When the n-layer has a single-layer structure, the thickness of the n-layer is generally 0.5 to 10 μm. When the n-layer has a laminated structure of an n-type contact layer and an n-type clad layer, the thickness of the n-type contact layer is generally 0.2 to 10 μm, and the thickness of the n-type clad layer is particularly limited. However, it is usually 0.01 to 3 μm.
[0022]
Emitting layer 105 is a layer formed from GaN-based compound semiconductor, specifically, the Al c In d Ga 1-c -d N (0 ≦ c, 0 ≦ d, c + d ≦ 1) represented by compounds Be composed. In this light emitting layer, for example, by adjusting the composition ratio of In and Al of the above compound, the light emitting layer is doped with an n-type impurity such as Si, Ge, and S, or a p-type impurity such as Mg and Zn. By doing so, the wavelength of the generated light can be adjusted in the range from blue to ultraviolet.
[0023]
In FIG. 2, the light-emitting layer 105 is shown as a single layer; however, for example, the light-emitting layer has a stacked structure including a plurality of layers, and has a so-called multiple quantum well structure in which the composition of a compound forming each layer is changed. Is also preferred. The thickness of the light emitting layer is generally 0.001 to 0.5 μm in total thickness.
[0024]
The p layer 106 is a layer made of a p-type GaN-based compound semiconductor. Although the p-layer 106 is shown as a single layer in FIG. 2, it generally has a stacked structure in which a p-type cladding layer and a p-type contact layer are stacked in this order from the light emitting layer side.
[0025]
The p-type cladding layer is made of, for example, a compound represented by Al e Ga 1-e N (0 <e ≦ 1), and further doped with a p-type impurity. e is preferably 0.05 or more. The p-type contact layer is made of, for example, p-type GaN doped with a p-type impurity. Examples of p-type impurities doped into the p-type cladding layer and the p-type contact layer include Mg, Zn, and the like. The thickness of the p-type cladding layer is usually 0.001 to 1.5 μm, and the thickness of the p-type contact layer is generally 0.01 to 2 μm.
[0026]
The material of the n-type electrode 107 and the p-type electrode 108 of the semiconductor light emitting device 102 is not particularly limited as long as it can be electrically connected to the n-layer and the p-layer, respectively. A laminated structure of an Au layer (the Au layer is the outermost layer) is generally used. In this case, the thickness of each layer is usually 0.1 to 0.5 μm for the V layer and 1 to 3 μm for the Au layer. The p-type electrode generally has, for example, a laminated structure of a Ni layer and an Au layer (Au is the outermost layer). In this case, the thickness of each layer is usually 0.1 to 0.5 μm for the Ni layer and 1 to 3 μm for the Au layer.
[0027]
In forming the n-layer 102, the light-emitting layer 103, and the p-layer 104, a known film forming method such as a vapor phase growth method [metalorganic vapor phase epitaxy (MOCVD) or the like] can be employed. The doping of the n-type impurity into the n-layer and the doping of the p-type impurity into the p-layer are performed when these layers are formed (vapor phase growth).
[0028]
Although not shown in FIG. 2, when the supporting substrate is a sapphire substrate, it is difficult to form the n-layer directly, so that a buffer layer is preferably provided between the n-layer and the supporting substrate. Such a buffer layer has an effect of alleviating lattice mismatch between the supporting substrate and the n-layer. Due to the presence of the buffer layer, the formation of the n-layer (growth of the n-type GaN-based compound semiconductor crystal) can be improved. It is possible to proceed. Examples of the buffer layer include GaN, AlN, GaAlN, and ZnO. By the way, when forming an n-layer by vapor phase growth using GaN, a two-step growth method is adopted in which a buffer layer is formed by first forming a film under low-temperature conditions, and then the temperature is increased to form an n-layer. By doing so, the buffer layer and the n layer can be formed more easily. The thickness of the buffer layer is usually 0.001 to 1 μm.
[0029]
The exposed surface of the n-layer for forming the n-type electrode can be formed by an etching method using a photoresist or the like. Further, the p-type electrode and the n-type electrode may be formed by a known evaporation method or the like.
[0030]
The method for fixing the semiconductor light emitting element 102 to the support substrate 101 is not particularly limited. However, as shown in FIGS. 1 and 2, when the semiconductor light emitting element is electrically connected to the support substrate by wire bonding, a known die is used. A bonding method or the like can be adopted. Further, the semiconductor light emitting element may be fixed to the support substrate and electrically connected by so-called flip chip bonding.
[0031]
As shown in FIGS. 1 and 2, by providing a metal film 112 that can function as a reflective film on a part or the entirety of the inclined surface 111, the reflection efficiency of light toward the upper part of the device can be further increased. Can be.
[0032]
The material forming the metal film 112 preferably has a reflectance of 60% or more of light generated from the semiconductor light emitting element, and examples thereof include Al, Ag, and Rh. The metal film 112 can be formed by a known evaporation method or the like.
[0033]
Further, it is preferable that a rough surface structure 113 is formed around the formation portion of the semiconductor light emitting element 102 on the bottom surface of the concave portion. Due to the rough surface structure 113, light generated from the semiconductor light emitting element 102 and traveling toward the support substrate 101 is irregularly reflected and directed toward the top of the device (a2 in FIG. 2) or toward the inclined surface 111 (metal film 112). The light can be further reflected toward the upper side of the device by the inclined surface 111 (metal film 112), so that the light extraction efficiency can be further increased.
[0034]
The shape and configuration of the rough surface structure 113 are not particularly limited, as long as the rough surface structure 113 can diffusely reflect light traveling toward the support substrate 101 side. For example, a configuration in which a plurality of protrusions having the shapes shown in FIGS. 1 and 2 may be present. The protrusions have a shape like a continuous wall and are formed so as to surround the periphery of the formation portion of the semiconductor light emitting element. It may be a configuration. However, in order to more effectively diffuse the light traveling toward the support substrate side, it is preferable that a plurality of protrusions having the shapes shown in FIGS. 1 and 2 exist.
[0035]
The rough surface structure 113 can be formed by adjusting the etching conditions when the concave portion is formed by performing the above-described anisotropic etching on the support substrate 101.
[0036]
Although not shown in FIGS. 1 and 2, it is also preferable to provide the above-mentioned metal film (reflection film) on the bottom surface of the concave portion. In this case, light traveling toward the support substrate is more effectively transmitted to the upper portion of the device. Can be reflected to the side. Such a metal film can also be formed by a known vapor deposition method or the like.
[0037]
<Second embodiment>
FIG. 3 is a schematic plan view showing a second embodiment of the semiconductor light emitting device of the present invention, and FIG. 4 is a schematic diagram showing a cross section along line BB of FIG. 1 in more detail. Portions having the same functions as those in the first embodiment are denoted by the same reference numerals, and redundant description will be avoided. The second embodiment has the following features.
[0038]
In the semiconductor light emitting device 10b of the second embodiment, a drive circuit for driving the semiconductor light emitting element 102 is provided in the drive circuit forming section 116 of the support substrate 101. Thus, when the drive circuit is provided in the semiconductor light emitting device, it is not necessary to provide the drive circuit outside the support substrate 101, and the semiconductor light emitting device can be reduced in size.
[0039]
When a pattern for forming a drive circuit is provided on the inclined surface 111 of the concave portion of the support substrate 101, if a metal film (reflection layer) is directly formed on the inclined surface, current leaks. Since light emission of the semiconductor light emitting element may be hindered, an insulating film 115 such as a SiO 2 film is preferably provided between the inclined surface 111 and the metal film 112 as shown in FIG.
[0040]
Further, a driving circuit provided in the supporting substrate 101 is not particularly limited, and examples thereof include a circuit including a resistor for reducing a current value as needed. In the case where an AC power supply is employed, a circuit in which an AC / DC conversion circuit is combined with the above circuit can be used.
[0041]
FIG. 5 shows an example of an equivalent circuit of the semiconductor light emitting device of the present invention including the semiconductor light emitting element 102 and the driving circuit 117. In the semiconductor light emitting device of the present invention, in any of the first embodiment, the second embodiment, and the third embodiment described below, as shown in FIG. Are preferably connected in parallel. By employing such a configuration, it is possible to prevent the semiconductor light emitting element 102 from being damaged when an overvoltage is applied.
[0042]
<Third embodiment>
FIG. 6 is a schematic sectional view showing a third embodiment of the semiconductor light emitting device of the present invention. In the semiconductor light emitting device 10c of the third embodiment, the bottom surface of the recess of the support substrate 101 formed with the recess by anisotropic etching described above, SiC or Al X In Y Ga 1-X -Y N (0 ≦ X .Ltoreq.1,0.ltoreq.Y.ltoreq.1,0.ltoreq.1-XY.ltoreq.1) A semiconductor light emitting device in which an n-layer 104, a light-emitting layer 105, a p-layer 106, and a p-type electrode 108 are sequentially formed via a thin film 119. 102 are provided.
[0043]
n-type electrode 107 is provided on the supporting substrate 101, diffusion layer 120, and SiC or Al X In Y Ga 1-X -Y N (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ 1- XY ≦ 1) It is electrically connected to the n-layer 106 via the thin film 119. The diffusion layer 120 of the supporting substrate 101 has impurities diffused therein, and thus has lower electric resistance than other portions, so that current can flow. The diffusion layer 120 can be formed by a method in which an impurity such as boron is ion-implanted and then heat treatment is performed. The depth of the diffusion layer is usually about 0.5 μm or less.
[0044]
Although not shown in FIG. 6, a part of the support substrate 101 and the semiconductor light emitting element 102 are sealed with a sealing resin as in the first embodiment and the second embodiment.
[0045]
The configuration, material, thickness, and forming method of the n-layer 104, the light-emitting layer 105, the p-layer 106, the n-type electrode 107, and the p-type electrode 108 according to the semiconductor light emitting device 102 are the same as those in the first embodiment. In the semiconductor light emitting device 10c of the third embodiment, the components of the semiconductor light emitting element 102 can be formed directly on the support substrate 101. Therefore, the step of fixing the semiconductor light emitting element 102 to the support substrate 101 by the above-described die bonding method or the like can be omitted.
[0046]
Note that, even if an n-layer is directly formed on a silicon substrate as a supporting substrate by the above-described vapor deposition method or the like, an n-layer forming component diffuses into the silicon substrate, and it is difficult to form a layer. Therefore, protection of the SiC or Al X In Y Ga 1-X -Y N (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ 1-X-Y ≦ 1) thin film 119, for n layer 104 formed It is provided on the supporting substrate 101 as a layer. Preferable specific examples of Al X In Y Ga 1-X -Y N (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ 1-X-Y ≦ 1) thin film, GaN, AlN and the like .
[0047]
The SiC or Al X In Y Ga 1-X -Y N (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ 1-X-Y ≦ 1) thin film, similar to the like n-layer, the above-described air It can be formed by a phase growth method (such as a MOCVD method). The thickness of such a thin film is preferably 10 μm or less, more preferably 0.1 to 3 μm or less.
[0048]
Further, similarly to the first embodiment, a metal film is provided on the inclined surface of the concave portion of the support substrate 101, or a rough surface structure or a metal film is formed around the formation portion of the semiconductor light emitting element 102 on the bottom surface of the concave portion. It is also preferable from the viewpoint that the light extraction efficiency can be increased. Further, as in the second embodiment, it is also recommended to provide a drive circuit for driving the semiconductor light emitting element 102 on the support substrate 101, because the size of the semiconductor light emitting device can be reduced.
[0049]
【The invention's effect】
In the semiconductor light emitting device of the present invention, since the supporting substrate is a silicon substrate having excellent heat conduction, heat generated during light emission can be effectively discharged through the silicon substrate, and thermal degradation of the semiconductor light emitting element is suppressed. obtain. In addition, the silicon substrate as the support substrate is inexpensive as compared with a conventional ceramic substrate, so that cost reduction can be achieved.
[0050]
Further, a driving circuit or the like for driving the semiconductor light emitting element can be provided on the supporting substrate, so that the size of the semiconductor light emitting device can be reduced.
[0051]
In addition, since the light leaking from the side surface of the semiconductor light emitting element can be reflected and taken out of the device on the inclined surface of the concave portion of the support substrate, the light emitted from the element can be more effectively utilized. Can be.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing a first embodiment of a semiconductor light emitting device of the present invention.
FIG. 2 is a schematic cross-sectional view taken along line AA of FIG.
FIG. 3 is a schematic plan view showing a second embodiment of the semiconductor light emitting device of the present invention.
FIG. 4 is a schematic sectional view taken along line BB of FIG. 2;
FIG. 5 is a diagram showing an example of an equivalent circuit of the semiconductor issuing device of the present invention.
FIG. 6 is a schematic sectional view showing a third embodiment of the semiconductor light emitting device of the present invention.
[Explanation of symbols]
10a 10b 10c Semiconductor light emitting device 101 Support substrate 102 Semiconductor light emitting element 103 Translucent substrate 104 N layer 105 Light emitting layer 106 P layer 107 N type electrode 108 P type electrode 109 Sealing resin 110 Wire bond 111 Inclined surface 112 Metal film 113 Rough foliation 114 stable power supply 115 insulating film 116 driver circuit formation section 117 drive circuit 118 diode 119 SiC or Al X In Y Ga 1-X -Y N (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ 1-X −Y ≦ 1) Thin film 120 Diffusion layer a1 Path a2 of light reflected to the upper side of device by metal film Path a2 of light reflected to the upper side of device by rough surface structure

Claims (8)

内面が擂鉢状の凹部を有する支持基板の該凹部の底面上に、GaN系半導体を構成要素に含む半導体発光素子を有する半導体発光装置であって、
前記支持基板はシリコン基板であることを特徴とする半導体発光装置。
A semiconductor light-emitting device having a semiconductor light-emitting element including a GaN-based semiconductor as a component on a bottom surface of a concave portion of a support substrate having a mortar-shaped concave portion on an inner surface,
The semiconductor light emitting device according to claim 1, wherein the support substrate is a silicon substrate.
前記半導体発光素子は、n層と前記支持基板の間に透光性基板を有するものである請求項1に記載の半導体発光装置。The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting element has a light transmitting substrate between the n layer and the support substrate. 前記半導体発光素子は、SiCまたはAlInGa1−X−YN(0≦X≦1,0≦Y≦1,0≦1−X−Y≦1)薄膜を介して、n層から順次形成されてなるものである請求項1に記載の半導体発光装置。The semiconductor light emitting device, SiC or Al X In Y Ga 1-X -Y N (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ 1-X-Y ≦ 1) through the thin film, the n layer 2. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is formed sequentially. 前記底面における前記半導体発光素子の形成部周囲に、粗面構造を有するものである請求項1〜3のいずれかに記載の半導体発光装置。The semiconductor light emitting device according to any one of claims 1 to 3, wherein the semiconductor light emitting device has a rough surface structure around a formation portion of the semiconductor light emitting element on the bottom surface. 前記凹部の傾斜面に、半導体発光素子から発生する光の反射率が、少なくとも60%の金属膜を有するものである請求項1〜4のいずれかに記載の半導体発光装置。The semiconductor light emitting device according to claim 1, wherein the inclined surface of the concave portion has a metal film having a reflectance of at least 60% for light generated from the semiconductor light emitting element. 前記金属膜は、Al、AgまたはRhから構成されてなるものである請求項5に記載の半導体発光装置。The semiconductor light emitting device according to claim 5, wherein the metal film is made of Al, Ag, or Rh. 半導体発光素子と電気的に接続された該発光素子を駆動するための駆動回路を、前記支持基板上に有するものである請求項1〜6のいずれかに記載の半導体発光装置。The semiconductor light emitting device according to any one of claims 1 to 6, wherein a drive circuit for driving the light emitting element electrically connected to the semiconductor light emitting element is provided on the support substrate. 前記半導体発光素子と並列に接続されたダイオードを有するものである請求項1〜7のいずれかに記載の半導体発光装置。The semiconductor light emitting device according to claim 1, further comprising a diode connected in parallel with the semiconductor light emitting element.
JP2003149446A 2003-05-27 2003-05-27 Semiconductor light emitting device Expired - Fee Related JP4277583B2 (en)

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