KR100587016B1 - Led package having etching-stop layer and fabrication method thereof - Google Patents

Abstract

The present invention relates to a light emitting diode package having an etch stop film and a method of manufacturing the same. An Si base layer, an etch stop film made of oxide, and an Si upper layer are sequentially formed, and the Si upper layer is etched to form a cavity in the Si upper layer. In this case, since the etch stop layer is not etched and only the upper Si layer is etched, the cavity may be easily and reliably formed, and the difference in contact resistance due to the difference in roughness may be prevented.

Light Emitting Diode, Cavity, Roughness, Etch Stop, Oxide

Description

Light emitting diode package having an etch stop film and a method of manufacturing the same {LED PACKAGE HAVING ETCHING-STOP LAYER AND FABRICATION METHOD THEREOF}             

1 is a cross-sectional view of an LED package according to an embodiment of the present invention.

2 is a cross-sectional view of a modification of the LED package of FIG. 1.

3A to 3H are flowcharts illustrating a method of manufacturing an LED package according to an embodiment of the present invention.

4A to 4J are process charts illustrating a method of manufacturing an LED package according to another embodiment of the present invention.

<Explanation of symbols of main parts in drawings>

100, 200: LED package 102, 202: Si substrate

104, 204: etch stop layer 106, 206: Si upper layer

116, 216: LED chip

The present invention relates to a light emitting diode package and a method of manufacturing the same. More specifically, the cavity is easily formed by sequentially forming a Si base layer, an etch stop layer made of an oxide, and an upper Si layer, and etching the upper Si layer to form a cavity in the upper Si layer. The present invention relates to a light emitting diode package having an etch stop layer and a method of manufacturing the same.

Surface-mount (SMD) packages are typically completed by forming cavities (or grooves) on Si wafers through etching, embedding LED (light emitting diode) chips inside them, and then sealing them.

Such etching is performed by wet etching using the crystallographic direction of the Si wafer, and the depth of the cavity is determined by adjusting the etching time. Therefore, the depth of the cavity is difficult to precisely control and its surface roughness is not constant. In this case, since the thickness of the substrate is not constant, the thermal resistance value may vary, and may cause a difference in contact resistance due to a difference in roughness.

Therefore, the present invention has been made to solve the above-described problems of the prior art, an object of the present invention is to form a Si base layer, an etch stop film made of oxide and an upper Si layer in sequence and to etch the upper Si layer to form a cavity in the upper Si layer The present invention provides a light emitting diode package having an etch stop film which can be easily and reliably formed by forming a light emitting diode package, and a method of manufacturing the same.

In order to achieve the above object of the present invention, the present invention is Si substrate; An etch stop layer deposited on the Si substrate; An upper Si layer having a cavity bonded to the etch stop layer; A light emitting diode chip mounted in the cavity; And a terminal portion electrically connecting the light emitting diode chip to an external power source, wherein the terminal portion passes through the etch stop layer and the Si base layer from inside the cavity to provide a light emitting diode package formed on a bottom surface of the Si base layer. It is characterized by.

In addition, the present invention

(A) preparing a base layer with a Si wafer;

(B) depositing an etch stop layer on the Si substrate;

(C) forming an upper layer of the Si wafer on the etch stop layer;

(D) wet etching the upper Si layer to form a cavity to expose a portion of the etch stop layer in the upper Si layer;

(E) forming a hole for an electrode that penetrates a part of the exposed etch stop layer and the Si base layer below it;

(F) forming a power supply terminal portion extending from the cavity to the bottom surface of the Si base layer through the hole for the electrode;

(G) It provides a light emitting diode package manufacturing method comprising the step of mounting a light emitting diode chip in the cavity to be electrically connected to the terminal portion.

In addition, the present invention

(A) preparing a base layer with a Si wafer;

(B) depositing an etch stop layer on the Si substrate;

(C) forming an upper layer of the Si wafer on the etch stop layer;

(D) wet etching the upper Si layer to form a cavity to expose a portion of the etch stop layer in the upper Si layer;

(E) forming a hole for an electrode penetrating a portion of the exposed etch stop layer;

(E) depositing a metal layer on an inner wall of the cavity and a portion of an upper surface of the etch stop layer exposed adjacent to the inner wall;

(G) forming a hole for the electrode penetrating the Si base layer corresponding to the hole for the electrode of the etch stop film;

(H) performing plating or deposition and subsequent patterning to form a power supply terminal portion extending from the cavity to the bottom of the Si substrate through the hole for the electrode; And

(I) provides a light emitting diode package manufacturing method comprising the step of mounting a light emitting diode chip in the cavity to be electrically connected to the terminal portion.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of an LED package according to an embodiment of the present invention. Referring to FIG. 1, the LED package 100 has a Si base layer 102, an etch stop layer 104 and a cavity 108 deposited on the Si base layer 102, on the etch stop layer 104. The bonded Si upper layer 106, the LED chip 116 mounted in the cavity 108, and a terminal portion electrically connecting the LED chip 116 to an external power source. In addition, a transparent cover 122 is attached to an upper end of the upper Si layer 106 to seal the cavity 108.

The Si base layer 102 is obtained from a Si wafer of constant thickness, and the etch stop film 104 is obtained by depositing an oxide on the Si base layer 102 in a constant thickness.

The upper Si layer 106 is obtained by bonding a Si wafer having a predetermined thickness to the etch stop layer 104 by an anodic bonding, and the cavity 108 in the upper Si layer 106 is the upper Si layer 106. Is formed by wet etching using a photoresist. KOH (potassium hydroxide) or TMAH (tetramethylammonium hydroxide) is used as an etching solution at this time.

In this case, since the etch stop film 104 is not etched, the bottom of the cavity 108, that is, the top surface of the etch stop film 102 in the cavity 108 remains smooth. Further, since only the Si upper layer 106 is etched, the depth of the cavity 108 is determined by the thickness of the Si upper layer 106. Thus, the cavity 108 can be formed accurately and reliably.

The cavity 108 may be filled with a gas, unlike the prior art, which is usually filled with a resin, and preferably filled with an inert gas. In this way, problems such as stress caused by the difference in thermal expansion coefficient between the LED chip and the resin can be prevented. Alternatively, the cavity 108 may be filled with silicon or the like having a thermal expansion coefficient similar to that of the LED chip 116 to relieve stress due to a difference in thermal expansion coefficient.

On the other hand, the terminal portion is composed of a positive terminal 112 and a negative terminal 114 to electrically connect the LED chip 116 with an external power source. The positive terminal 112 and the negative terminal 114 are internal terminals respectively located inside the cavity 108, vias passing through the etch stop film 104 and the Si base layer 102, and externally attached to the bottom of the Si base layer 102. It consists of terminals. Meanwhile, although the anode terminal 112 is illustrated as being connected to a reflector formed on the inner wall of the cavity 108, the reflector may be connected to the cathode terminal 114 instead of the anode terminal 112.

The positive or negative terminals 112 and 114 may be connected to a heat sink of a circuit board (not shown) on which the LED package 100 is mounted to extract heat generated from the LED chip 116 into the heat sink. In this case, since the internal terminals are attached to the smooth etch stop layer 104, the thermal resistance and the contact resistance therebetween may be greatly reduced.

In addition, the inner terminal of the anode terminal 112 is formed to cover the side wall of the cavity 108 to guide the light generated from the LED chip 116 to the upper side.

The LED chip 116 is mounted inside the cavity 108 in a flip chip manner, such that the positive electrode 118 is connected to the positive terminal 112 of the terminal portion by solder bumps or the like, and the negative electrode 120 is also negative electrode terminal by the solder bumps or the like. Connected with 114.

Also, although not shown, the formation of an insulating wall between the positive and negative terminals 112 and 114 of the Si base layer 102 is likely to conduct current between these terminals 112 and 114 through the Si base layer 102. Can be eliminated.

Meanwhile, the sealing cover 122 attached to the upper portion of the upper Si layer 106 may be formed of a planar optical device such as Fresnel glass. In this way, the light generated in the LED chip 116 can be further directed to the front of the LED package 100.

In the LED package 100 having such a configuration, by using the etch stop film 104, the cavity 108 can be formed accurately and reliably. In addition, thermal resistance and contact resistance between the internal terminals of the anode and cathode terminals 118 and 120 and the etch stop layer 104 may be greatly reduced.

2 is a cross-sectional view of a modification of the LED package of FIG. 1. Referring to FIG. 2, the LED package 200 of FIG. 2 is substantially the same as the LED package 100 of FIG. 1 except that the LED chip 216 is mounted inside the cavity 206 by a wire bonding method. Do. Accordingly, the positive and negative electrodes 218 and 220 of the LED chip 216 are electrically connected to the internal terminals of the positive and negative terminals 212 and 214 by a pair of wires W, respectively. Since the rest of the configuration is the same as that of FIG. 1, the description thereof is omitted and corresponding components are denoted by reference numerals 200.

3A to 3H are flowcharts illustrating a method of manufacturing an LED package according to an embodiment of the present invention.

First, as shown in FIG. 3A, a constant Si wafer is prepared to form a Si base layer 102.

Subsequently, as shown in FIG. 3B, an etch stop layer 104 is deposited on the Si base layer 102 to a predetermined thickness. The etch stop layer 102 is made of an oxide, and performs the function of an etch mask in a subsequent etching operation.

Then, as shown in FIG. 3C, a Si wafer having a constant thickness is bonded to the etch stop layer 104 to form an upper Si layer 106. In this case, the Si upper layer 106 is bonded to the etch stop layer 104 by anodic bonding or the like.

Subsequently, as shown in FIG. 3D, the photoresist 130 having a predetermined pattern 132 is attached and etched on the upper Si layer 106. In this case, the pattern 132 of the photoresist 130 has a shape for obtaining a desired cavity 108 through an etching operation. Etching is performed using KOH (potassium hydroxide) or TMAH (tetramethylammonium hydroxide).

In this way, the upper Si layer 106 is etched through the opening of the pattern 132, but the etch stop layer 104 is not etched and performs an etching mask function, so as shown in FIG. 3E by the selective etching of the upper Si layer 106. A cavity 108 such as one is formed, through which the portion of the etch stop film 104 is exposed upward.

The bottom surface of the cavity 108 thus formed, that is, the exposed top surface of the etch stop layer 104, has a constant surface roughness unlike the conventional cavity bottom surface, and thus the contact resistance is reduced. In addition, since the depth of the cavity 108 can be precisely controlled, the thickness of the Si base layer 102 in the final product is constant, resulting in a constant thermal resistance value.

Subsequently, a through hole 110 penetrating through the etch stop layer 104 and the Si base layer 102 through etching is formed as shown in FIG. 3F. Detailed steps of forming the through-hole 110 are as follows.

First, a photoresist is coated on the etch stop layer 104 exposed in the cavity 108 and etched with HF to form an upper hole in the etch stop layer 104. Subsequently, a photoresist is coated on the bottom surface of the Si base layer 102 and the Si base layer 102 is etched by plasma to form a lower hole which is connected to the upper hole of the etch stop layer 102. To complete.

Then, a plating mold (not shown) is prepared, and the inside of the cavity 108 and the bottom of the Si base layer 102 and the through hole 110 are plated and / or deposited, patterned and / or laser treated as shown in FIG. 3G. Likewise, the positive terminal 112 and the negative terminal 114 are formed.

Subsequently, as shown in FIG. 3H, the prepared LED chip 116 is mounted inside the cavity 108 such that the positive electrode 118 is connected to the positive terminal 112 and the negative electrode 120 is connected to the negative terminal 114. do.

The cavity 108 is then filled with a gas, preferably an inert gas, and a cover 122, preferably a planar optical element, is attached to the top of the Si upper layer 106, as shown in FIG. Complete the LED package 100. Alternatively, the cavity 108 may be filled with silicon or the like having a thermal expansion coefficient similar to that of the LED chip 116.

Alternatively, the LED package 200 of FIG. 2 may be obtained by mounting the LED chip by wire bonding in the step of FIG. 3H.

Optionally, when the lower through hole is formed in the Si base layer 102, the through hole for the insulating wall is formed in the center of the base layer, and the insulating wall is later filled with the insulator to form the insulating wall. 114) the possibility of current conduction between them can be eliminated.

4A to 4J are cross-sectional views illustrating a method of manufacturing an LED package according to another embodiment of the present invention.

First, since the steps of FIGS. 4A to 4E are the same as those of FIGS.

Then, as shown in FIG. 4F, a photoresist (not shown) is coated on the etch stop layer 104 exposed in the cavity 108 and etched with HF to be a part of the desired through hole 110 (see FIG. 4H). An upper through hole 110a is formed in the etch stop layer 104.

Subsequently, as illustrated in FIG. 4G, the metal conductive layer 112a is formed on the sidewall of the cavity 108 and the bottom thereof. This metal conductive layer 112a acts as a seed layer in subsequent work and in the finished product it will function as a reflector and internal terminals.

Subsequently, a photoresist is coated on the bottom surface of the Si base layer 102 and the Si base layer 102 is etched by plasma, and as shown in FIG. 4H, the lower hole connected to the upper hole 110a of the etch stop layer 102 is shown. Form 110b to complete the through-hole 110.

Then, as shown in Fig. 4I, positive and negative terminals 112 and 114 are formed. The steps of forming the positive and negative terminals 112 and 114 are as follows.

First, a nitride film or an oxide film is deposited inside the through hole 110, and then a plating frame (not shown) is installed on the Si base layer 102 and plated using the metal conductive layer 112a as a seed layer. Subsequently, the plating frame is removed, a protective layer (not shown) is formed to protect the plating layer on the surface of the Si upper layer 106 including the metal conductive layer 112a, and the bottom surface of the Si base layer 102 is planarized and then conductive. Deposit a layer. Then, the positive and negative terminals 112 and 114 are completed through patterning. Subsequently, the protective layer is removed, and the cathode terminal 114 is separated from the metal conductive layer 112a serving as a reflector through laser treatment or the like.

The subsequent step of FIG. 4J is the same as that of FIG. 3H, and the LED package 100 shown in FIG. 1 is obtained through the following process.

Alternatively, the LED package 200 of FIG. 2 may be obtained by mounting the LED chip by wire bonding in the step of FIG. 4J.

On the other hand, when forming the lower through holes (110b), the through-hole for the insulating wall is formed in the center of the base layer 102 between the lower through holes (110b), and later filled with an insulator to form the insulating wall through the Si base layer 102 The possibility of current conduction between the positive and negative terminals 112, 114 can be eliminated.

As described above, according to the present invention, the cavity can be easily and reliably formed by sequentially forming a Si base layer, an etch stop film made of an oxide, and an upper Si layer, and etching the upper Si layer to form a cavity in the upper Si layer. .

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. I will understand that it can be modified and changed.

Claims (19)

Si substrate; An etch stop layer deposited on the Si substrate; An upper Si layer having a cavity bonded to the etch stop layer; A light emitting diode chip mounted in the cavity; And And a terminal portion electrically connecting the light emitting diode chip to an external power source, wherein the terminal portion is formed on a bottom surface of the Si base layer through the etch stop layer and the Si base layer from inside the cavity. The light emitting diode package of claim 1, further comprising a transparent cover coupled to an upper portion of the Si upper layer to seal the cavity. The light emitting diode package of claim 2, wherein the cavity is filled with a gas, and the cover is a planar optical element. The light emitting diode package of claim 3, wherein the gas is an inert gas. The light emitting diode package according to any one of claims 1 to 4, wherein the etch stop layer is formed of an oxide. The light emitting diode package according to any one of claims 1 to 4, wherein the upper Si layer is bonded to the etch stop layer by an anodic bonding. The light emitting diode package according to any one of claims 1 to 4, further comprising an insulating wall formed in the Si base layer between portions passing through the Si base layer of the terminal portion. (A) preparing a base layer with a Si wafer; (B) depositing an etch stop layer on the Si substrate; (C) forming an upper layer of the Si wafer on the etch stop layer; (D) wet etching the upper Si layer to form a cavity to expose a portion of the etch stop layer in the upper Si layer; (E) forming a hole for an electrode that penetrates a part of the exposed etch stop layer and the Si base layer below it; (F) forming a power supply terminal portion extending from the cavity to the bottom surface of the Si base layer through the hole for the electrode; (G) mounting a light emitting diode chip in the cavity to be electrically connected to the terminal portion. The method of claim 8, wherein the step (e) comprises etching the etch stop layer using HF and etching the Si base layer using plasma. The method of claim 8, wherein the step (bar) is performed to form at least one of plating and deposition to form a metal layer extending from the cavity to the bottom surface of the Si base layer through the hole for the electrode, and patterning the metal layer to obtain the terminal portion. Method for manufacturing a light emitting diode package. The method of claim 8, further comprising attaching a cover of the planar optical device to the upper end of the Si upper layer after step (h). (A) preparing a base layer with a Si wafer; (B) depositing an etch stop layer on the Si substrate; (C) forming an upper layer of the Si wafer on the etch stop layer; (D) wet etching the upper Si layer to form a cavity to expose a portion of the etch stop layer in the upper Si layer; (E) forming a hole for an electrode penetrating a portion of the exposed etch stop layer; (E) depositing a metal layer on an inner wall of the cavity and a portion of an upper surface of the etch stop layer exposed adjacent to the inner wall; (G) forming a hole for the electrode penetrating the Si base layer corresponding to the hole for the electrode of the etch stop film; (H) forming a power supply terminal portion from the cavity to the bottom of the Si substrate through the hole for the electrode through plating or deposition and subsequent patterning; And (I) mounting a light emitting diode chip in the cavity to be electrically connected to the terminal portion. The method of claim 12, wherein in the step (e), the etch stop layer is etched using HF. The method of claim 12, wherein step (d) uses KOH (potassium hydroxide) or TMAH (tetramethylammonium hydroxide) for etching, and step (g) uses plasma for etching. A light emitting diode package manufacturing method. The method of claim 12, wherein the step (h) is performed to form at least one of plating and deposition to form a metal layer extending from the cavity to the bottom of the Si base layer through the hole for the electrode and patterning the metal layer to obtain the terminal portion. Method for manufacturing a light emitting diode package. The method of claim 12, further comprising attaching a cover of the planar optical element to the upper portion of the upper Si layer after the (d) step. 17. The method of claim 11 or 16, wherein the cavity is filled with an inert gas. The light emitting diode package manufacturing method of claim 8 or 12, wherein the etch stop layer is formed of an oxide. The method of claim 8, wherein the upper Si layer is bonded to the etch stop layer by an anodic bonding.

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