JP2004334774A - Controller device, image forming device, computer program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily confirm operations of an arbiter circuit without operations of an I/F circuit. <P>SOLUTION: In this controller device, a plurality of DMA circuits 101, 102, 103 access a common memory. In addition to respective I/F circuits 301, 302, 303 to which the respective DMA circuits 101, 102, 103 are connected, a common DMA circuit control circuit 600 having functions to simultaneously start the respective DMA circuits 101, 102, 103 by a common start signal is provided for confirming the operations of a memory arbiter circuit 400 without operations of the respective I/F circuits 301, 302, 303. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a controller device using a DMA circuit, an image forming apparatus equipped with the controller device, a method of controlling a memory using the DMA circuit, a computer program for executing the control method, and a computer program recorded with the computer program. It relates to a recording medium.
[0002]
[Prior art]
Conventionally, many DMA circuits are built in a controller device, and circuits are formed so as to access a common memory device. Therefore, each DMA circuit adjusts the memory access by the memory arbiter and accesses the memory sequentially. Therefore, the operating speed of the memory device has an influence on the performance of the system, and the development of a high-speed memory device is in progress. As the access speed of the memory device increases, the system performance is affected by the speed of the I / F connected to the DMA circuit, and the speed of the I / F increases with the speed of the memory device.
[0003]
However, in a system to which a plurality of I / Fs are connected, the priority of each DMA circuit is determined by a memory arbiter, and a memory access is performed. At this time, if the memory access requests of a plurality of DMA circuits compete for the I / F with a low priority, the system performance due to the speeding up of the I / F does not improve so much. For this reason, the memory arbiter circuit has a function of switching the priority depending on conditions, and has a function of ensuring performance even with an I / F having a low priority.
[0004]
[Problems to be solved by the invention]
As described above, the memory arbiter circuit has a function of switching priorities depending on conditions, and a function of ensuring performance even with an I / F with a low priority, but in order to confirm the function, It is necessary to operate and check each I / F at the same time. However, the circuit scale in recent years is very large, and the functions of each I / F are also complicated, and a large amount of knowledge is required. It is becoming impossible to confirm without doing it.
[0005]
Therefore, an object of the present invention is to provide a controller device capable of easily confirming the operation of an arbiter circuit without operating each I / F circuit, an image forming apparatus including the controller device, and a method of controlling a memory using a DMA circuit. Another object of the present invention is to provide a computer program for executing the control method and a recording medium on which the computer program is recorded.
[0006]
Another object is to provide a controller device capable of easily confirming the operation of an arbiter circuit by a combination operation, an image forming apparatus including the controller device, a method of controlling a memory using a DMA circuit, and a method for executing the control method. It is to provide a computer program and a recording medium on which the computer program is recorded.
[0007]
[Means for Solving the Problems]
The first means is, in a controller device in which a plurality of DMA circuits access a common memory, an interface circuit to which each of the DMA circuits is connected, an arbitration circuit for arbitrating an access request of each of the DMA circuits, and an arbitration circuit for each of the DMA circuits. And a control circuit for confirming the operation of the arbitration circuit without passing through the interface circuit. The second means is the first means, wherein the control circuit is A common activation signal for simultaneously activating each DMA circuit is output, and an execution time from the activation of each DMA circuit to the completion of data transfer is measured.
[0008]
Third means is a controller device in which a plurality of DMA circuits access a common memory, an interface circuit to which each DMA circuit is connected, an arbitration circuit for arbitrating an access request of each DMA circuit, and a DMA device. And a control circuit for individually selecting and checking a combination operation of the arbitration circuit without passing through the interface circuit.
[0009]
A fourth means is the third means, wherein the control circuit activates a DMA circuit to which an interface circuit other than the interface circuit to be measured is connected, and activates the DMA circuit to which the interface circuit to be measured is connected. It is characterized in that the execution time from when the data transfer is completed until the data transfer is completed is measured.
[0010]
A fifth means is the second or fourth means, wherein the control circuit diagnoses a state of the arbitration circuit from a change in the execution time.
[0011]
A sixth aspect is characterized in that the image forming apparatus includes the controller device according to the first to fifth aspects.
[0012]
The seventh means is a memory control method in which a plurality of DMA circuits access a common memory, comprising: an interface circuit connected to each DMA circuit; and an arbitration circuit arbitrating an access request of each DMA circuit. Each DMA circuit is activated simultaneously, and the operation of the arbitration circuit is confirmed without passing through the interface circuit.
[0013]
Eighth means is a memory control method in which a plurality of DMA circuits access a common memory, comprising: an interface circuit connected to each DMA circuit; and an arbitration circuit arbitrating an access request of each DMA circuit. DMA circuits are individually selected, and a combination operation of the arbitration circuits is confirmed without passing through the interface circuit.
[0014]
The ninth means is characterized in that a computer program is constructed to execute the memory control method according to the seventh or eighth means on a computer.
[0015]
A tenth means is characterized in that the computer program according to the ninth means is read by a computer and recorded on a recording medium in an executable manner.
[0016]
In the following embodiments, the common memory is the external memory 700, the DMA circuit is the first to third DMA circuits (Direct Memory Access) 1, 2, 3 (101, 102, 103), and the interface circuit is the The interface circuits (I / Fs 1, 2, 3) (301, 302, 303) correspond to the memory arbiter circuit 400, and the control circuit corresponds to the common DMA test control circuit 600.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
<First embodiment>
FIG. 1 is a block diagram showing the configuration of the controller device according to the first embodiment of the present invention.
[0019]
In the figure, the controller device according to the present embodiment includes first to third DMA circuits (Direct Memory Access) 1, 2, 3 (101, 102, 103), and first to third selection circuits (selection circuits). (1, 2, 3) (201, 202, 203), first to third interface circuits (I / Fs 1, 2, 3) (301, 302, 303), memory arbiter circuit 400, memory I / F circuit 500 And a common DMA test control circuit 600, which is connected to the external memory 700 via the memory I / F circuit 500. In FIG. 1, three DMA circuits and I / F circuits are shown, but the number is not limited.
[0020]
In FIG. 1, a DMA circuit 1 (101) performs memory access for an I / F1 (301), a DMA circuit 2 (102) performs an I / F2 (302), and a DMA circuit 3 (103) performs an I / F3 (303). ) Indicates memory access. The memory arbiter circuit 400 is connected in parallel with the first to third DMA circuits 1, 2, 3 (101, 102, 103), and is given priority according to the state (regardless of how the arbitration is performed). A DMA circuit that operates depending on the degree is selected, and the memory I / F circuit 500 is accessed. The memory I / F circuit 500 does not limit a circuit directly accessing the external memory 700.
[0021]
The selection circuit 1 (201) selects the I / F1 (301) and the DMA circuit signal of the common DMA test control circuit 600. The selection circuit 2 (202) includes the I / F2 (302) and the selection circuit (203). ) 3 is a circuit for similarly selecting the I / F3 (303). The selection circuits 1 to 3 (201, 202, 203) switch signals to be selected by the DMA circuit-sel signal.
[0022]
The activation 1 signal is a signal for individually activating the DMA circuit 1 (101), the activation 2 signal is a signal for activating the DMA circuit 2 (102), and the activation 3 signal is a signal for activating the DMA circuit 3 (103). In operation, the circuit operates with this signal.
[0023]
The common DMA test control circuit 600 outputs a common activation signal for simultaneously activating each of the DMA circuits (101, 102, 103) and is connected to the DMA circuits 1 to 3 (101, 102, 103). When the common start signal is turned on, when the data transfer direction is from the DMA circuits 101, 102, 103 to the memory I / F circuit 500, the common DMA test control circuit 600 is unique to each of the DMAs 101, 102, 103. Start transferring the same data. Next, each of the DMAs 101, 102, and 103 issues a memory WRITE request to the memory arbiter circuit 400. The memory arbiter circuit 400 sequentially processes the DMA requests with the priority determined in that state and transfers the data to the memory I / F circuit 500.
[0024]
When the data transfer direction is from the memory I / F circuit 500 to the DMA circuits 101, 102, and 103, each of the DMA circuits 101, 102, and 103 sends a memory READ request to the memory arbiter circuit 400 when the common start signal is turned on. do. The memory arbiter circuit 400 sequentially processes the DMA requests at the priority determined in that state, takes in data from the memory I / F circuits 301, 302, and 303, and transfers the data to the DMA circuits 101, 102, and 103. Thus, the respective DMA circuits 101, 102, 103 can be operated without operating the respective I / F circuits 301, 302, 303. Thus, the operation of the memory arbiter circuit 400 can be confirmed at the circuit TOP level without knowing the circuit specifications for operating each of the I / F circuits 301, 302, and 303.
[0025]
As described above, according to the present embodiment, since the common DMA test control circuit 600 is provided, when the plurality of DMA circuits 101, 102, and 103 access the common external memory 700, the DMA circuits 101, 102, and 103 Apart from the respective connected I / F circuits 301, 302, 303, each of the DMA circuits 101, 102, 103 can be activated simultaneously, and the operation of the memory arbiter circuit 400 is controlled. It can be confirmed without operating 302 and 303.
[0026]
Also, by turning on the common start signal, each DMA circuit can be easily started at the same time, which is the most crowded condition for the memory I / F circuit 500 at that time. Therefore, the bus performance of the memory I / F circuit 500 is in the worst condition at this time. Thus, at this time, the execution time from the start of each DMA circuit to the completion of data transfer is observed (measured) by the common DMA test control circuit 600, and from the result, it is determined whether or not the current circuit satisfies the required performance. it can. Therefore, the bus performance of the memory I / F bus 800 can be easily observed.
[0027]
Further, the shipping pattern that the user submits to the ASIC vendor needs to be at the circuit TOP level, and the state of a circuit in which an external PIN does not exist in an internal circuit such as an arbiter circuit is included in the inspection because of each I / F. It is very difficult to set the operation timing depending on the operation speed. However, by providing the common DMA test control circuit 600, the state change of the memory arbiter circuit 400 can be easily set and operated at the TOP level, and the number of patterns can be reduced. As a result, the failure detection rate can be easily increased.
[0028]
Note that the common DMA test control circuit 600 can be configured by a computer. In that case, the functions of the above-described common DMA test control circuit can be replaced by a computer program, and at that time, the above-mentioned functions may be programmed. This computer program is downloaded to a computer and used. At this time, the program may be downloaded from a server via a network, or a computer program may be written in a known recording medium such as an FD or a CD-ROM, and read and downloaded by a computer.
[0029]
Such a controller device is used for memory control of a digital multi-function peripheral, also called an MFP (Multi Function Preferential).
[0030]
FIG. 2 is a diagram showing a schematic configuration of an image forming apparatus provided with the controller device shown in FIG. 1, and FIG. 3 is a block diagram showing a schematic configuration of a control circuit of the image forming device shown in FIG.
[0031]
Hereinafter, the image forming apparatus according to the present embodiment will be described.
When a start key on the operation unit 30 is pressed, a document bundle placed on a document table 2 in an automatic document feeder (hereinafter ADF) 1 is fed from the bottom document. The sheet is fed to a predetermined position on the contact glass 6 by the feed roller 3 and the feed belt 4. After the reading unit 50 reads the image data of the document on the contact glass 6, the document that has been read is discharged by the feed belt 4 and the discharge roller 5. Further, when the document set detection sensor 7 detects that the next document is present on the document table 2, the document is fed onto the contact glass 6 in the same manner as the previous document. The feed roller 3, the feed belt 4, and the discharge roller 5 are driven by a transport motor 26.
[0032]
The transfer sheets stacked on the first tray 8, the second tray 9, and the third tray 10 are fed by the first sheet feeding device 11, the second sheet feeding device 12, and the third sheet feeding device 13, respectively, and are vertically conveyed. The sheet is transported by the unit 14 to a position where it contacts the photoconductor 15. The image data read by the reading unit 50 is written on the photoconductor 15 by the laser from the writing unit 57, and passes through the developing unit 27 to form a toner image. Then, the toner image on the photoconductor 15 is transferred while the transfer paper is conveyed by the conveyance belt 16 at the same speed as the rotation of the photoconductor 15. Thereafter, the image is fixed by the fixing unit 17, and the image is discharged to the finisher 60 of the post-processing device by the sheet discharging unit 18.
[0033]
The finisher 60 of the post-processing device can guide the transfer paper conveyed by the paper discharge roller 19 of the main body toward the normal paper discharge roller 62 and the staple processing unit. When the switching plate 61 is switched upward, the sheet is discharged to the normal paper output tray 64 via the transport roller 63, and when the switching plate 61 is switched downward, the staple table 68 is transported via the transport rollers 65 and 67. Can be transported.
[0034]
The transfer paper stacked on the staple table 68 is aligned by a paper alignment jogger 69 every time one sheet is discharged, and is stapled by the stapler 66 when a part of the copy is completed. The transfer paper group bound by the stapler 66 is stored in the stapling completion paper discharge tray 70 by its own weight.
[0035]
On the other hand, the normal paper discharge tray 64 is a paper discharge tray that can move back and forth. The paper discharge tray section 64 that can be moved back and forth has a function of moving back and forth for each document or each copy section sorted by the image memory, and sorting the copy paper that is simply discharged.
[0036]
When images are formed on both sides of the transfer paper, the transfer paper fed and imaged from each of the paper feed trays 8 to 10 is not guided to the paper output tray 64 side, and the branch claw 41 for path switching is used. By setting it on the upper side, it is once stocked in the duplex paper supply unit 111. Thereafter, the transfer paper stocked in the duplex paper supply unit 111 is re-fed from the duplex paper supply unit 111 in order to transfer the toner image formed on the photoconductor 15 again, and the branch pawl 41 for switching the path is used. Is set on the lower side, and guided to the discharge tray 64.
[0037]
As described above, the double-sided paper feeding unit 111 is used when forming images on both sides of the transfer paper.
[0038]
The photoconductor 15, the transport belt 16, the fixing unit 17, the paper discharging unit 18, and the developing unit 27 are driven by a main motor 25, and the respective paper feeding devices 11 to 13 drive the main motor 25 by paper feeding clutches 22 to 24, respectively. Driven by transmission. The vertical transport unit 14 is driven to transmit the drive of the main motor 25 by the intermediate clutch 21.
[0039]
FIG. 3 illustrates a control device with a focus on the main controller. The main controller 20 controls the entire image forming apparatus. The main controller 20 is connected with a main motor 25 and various clutches 21 to 24 necessary for paper conveyance and the like. An operation unit 30 for displaying to an operator, inputting function settings from the operator, controlling a scanner, controlling to write a document image in an image memory, controlling to form an image from an image memory, and the like. 49, a distributed control device such as an automatic document feeder (ADF) 1 is connected. The display is performed via the liquid crystal display 31, and the function setting input from the operator is performed by the key input unit 32. Each decentralized control device and the main controller 20 exchange machine status and operation commands as needed. A control program executed by each distributed control device is stored in a ROM inside each distributed control device. An IC card slot 27 is connected to the main controller 20, and control program data stored in an IC card external to the image forming apparatus is downloaded to the ROM inside the distributed control device via the IC card slot 27 and controlled. It is possible to change the program. The controller device of FIG. 1 is provided in the IPU 49.
[0040]
The operation from image reading to image writing in the image forming apparatus will be described with reference to FIG. 2 again.
[0041]
The reading unit 50 includes a contact glass 6 on which a document is placed and an optical scanning system. The optical scanning system includes an exposure lamp 51, a first mirror 52, a lens 53, a CCD image sensor 514, and the like. I have. The exposure lamp 51 and the first mirror 52 are fixed on a first carriage (not shown), and the second mirror 55 and the third mirror 56 are fixed on a second carriage (not shown). When reading an original image, the first carriage and the second carriage are mechanically scanned at a relative speed of 2: 1 as described above so that the optical path length does not change.
[0042]
This optical scanning system is driven by a scanner drive motor (not shown). The document image is read by the CCD image sensor 54, converted into an electric signal, and processed. By moving the lens 53 and the CCD image sensor 54 in the horizontal direction in FIG. 7, the image magnification changes. That is, the positions of the lens 53 and the CCD image sensor 54 in the left-right direction are set corresponding to the designated magnification.
[0043]
The writing unit 57 includes a laser output unit 58, an imaging lens 59, and a mirror. Inside the laser output unit 58, a rotating polygon mirror (polygon mirror) that rotates at high speed at a constant speed by a laser diode as a laser light source and a motor. Is provided.
[0044]
The laser light emitted from the laser output unit 58 is deflected by a polygon mirror that rotates at a constant speed, passes through an imaging lens 59, is turned back by the mirror, and condenses and forms an image on the surface of the photoconductor 15.
[0045]
The polarized laser light is exposed and scanned in a direction (main scanning direction) orthogonal to the direction in which the photoconductor 15 rotates, and performs recording in units of lines of an image signal output from a selector of an image processing unit described later. An image (electrostatic latent image) is formed on the photoconductor surface by repeating main scanning at a predetermined cycle corresponding to the rotation speed of the photoconductor 15 and the recording density.
[0046]
As described above, the laser beam output from the writing unit 58 is applied to the photoconductor 15 of the image forming system. Although not shown, a beam sensor that generates a main scanning synchronization signal is disposed at a position near one end of the photoconductor 15 where the laser beam is irradiated.
[0047]
<Second embodiment>
FIG. 4 is a block diagram illustrating a configuration of a controller device according to the second embodiment. This embodiment is different from the first embodiment in that the selection circuits 1, 2, and 3 (201, 202, and 203) change from the DMA circuit-sel [1] to the DMA circuit-sel [3] from the common DMA test control circuit. The only difference from the first embodiment is that a signal to be selected by a signal is switched and that a common signal can be output individually, and other components are the same as those of the first embodiment. Only different points from the first embodiment will be described.
[0048]
In the second embodiment, the common DMA test control circuit 600 outputs common activation signals [1] to [3] for simultaneously activating the selected DMA circuits 101, 102, and 103, and outputs the DMA circuits 1 to 3 ( The circuits are connected to 101, 102, and 103. The DMA circuits -sel [1] to [3] and the common start signals [1] to [3] are paired, and the DMA circuits -sel [1] are connected to each other. When the common DMA test control circuit 600 is selected, the common start signal [1] is turned ON, and the common DMA test control circuit 600 similarly controls the DMA circuit-sel [2] and the DMA circuit-sel [3]. When selected, the common start signals [2] and [3] are turned on, and when the common start signals are turned on, the data transfer direction is changed from the DMA circuits 101, 102 and 103 to the memory I / F circuit 500. Direction In this case, the common DMA test control circuit 600 starts transferring the same data unique to each of the DMAs 101, 102, and 103. Next, each of the DMAs 101, 102, and 103 outputs a memory WRITE request to the memory arbiter circuit 400. The arbiter circuit 400 sequentially processes the DMA requests with the priority determined in that state, and transfers the data to the memory I / F circuit 500.
[0049]
When the data transfer direction is from the memory I / F circuit 500 to the DMA circuits 101, 102, and 103, when the common activation signal is turned on, the DMA arbiter circuit 400 of each of the DMA circuits 101, 102, and 103 sends the memory READ signal to the memory arbiter circuit 400. Make a request. The memory arbiter circuit 400 sequentially processes the DMA requests at the priority determined in that state, takes in data from the memory I / F circuit 500, and transfers the data to the DMA circuits 101, 102, and 103. Thus, the respective DMA circuits 101, 102, and 103 can be operated without operating the respective I / F circuits 301, 302, and 303, and the respective I / F circuits 301, 302, and 303 are operated. Without knowing the circuit specifications for the arbiter circuit at the circuit TOP level.
[0050]
In addition, each unit not particularly described is configured and functions equivalently to the above-described first embodiment.
[0051]
As described above, according to the present embodiment, the common DMA test control circuit is provided, the signals selected by the DMA circuit-sel [1] to the DMA circuit-sel [3] signals are switched, and the common signal for selecting the DMA circuit is individually set. , So that separately selected I / F circuits 301, 302, and 303 to which the respective DMA circuits 101, 102, and 103 are connected, start simultaneously selected DMA circuits 101, 102, and 103. It is possible to confirm a plurality of combined operations of the memory arbiter circuit 400 without operating each of the I / F circuits 301, 302, and 303.
[0052]
When the worst state of the bus performance of the I / F circuits 301, 302, and 303 is observed, when the I / F circuit to be observed is the I / F1 circuit (301), the DMA circuits 102 other than the I / F1 circuit 301 , 103 are selected so as to be activated by the common DMA test control circuit 600, and the I / F1 circuit (301) performs the normal operation so that the I / F1 in the state where the memory arbiter circuit 400 competes most is obtained. The bus performance of the circuit 301 can be observed. Similarly, the I / F2 circuit 302 and the I / F3 circuit 303 can be observed. At this time, by observing (measuring) the execution time from the start of the observation target DMA circuit to the completion of data transfer, it is possible to determine whether the current circuit satisfies the required performance. In addition, a variation in bus performance due to the combination can be easily confirmed without operating other I / F circuits. Therefore, the bus performance of the memory I / F bus can be easily confirmed.
[0053]
Further, as in the first embodiment, the shipping pattern submitted by the user to the ASIC vendor needs to be at the circuit TOP level, and is used to inspect the state of a circuit such as an arbiter circuit in which there is no external PIN in an internal circuit. The inclusion also depends on the operation speed of each I / F, and it is very difficult to set the operation timing. However, by adding the above test circuit, the state change of the arbiter circuit can be easily set and operated at the TOP level, and the number of patterns can be reduced. As a result, the failure detection rate can be easily increased.
[0054]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a controller device capable of easily confirming the operation of the arbiter circuit without operating each I / F circuit.
[0055]
Further, according to the present invention, it is possible to provide a controller device capable of easily confirming the operation of the arbiter circuit by the combination operation.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a controller device according to a first embodiment of the present invention.
FIG. 2 is a schematic configuration diagram illustrating an example of an image forming apparatus including the controller device of FIG. 1;
FIG. 3 is a block diagram schematically illustrating an image forming apparatus control circuit of FIG. 2;
FIG. 4 is a block diagram illustrating a configuration of a controller device according to a second embodiment of the present invention.
[Explanation of symbols]
101, 102, 103 DMA circuits 201, 202, 203 Selection circuits 301, 302, 303 I / F circuit 400 Memory arbiter circuit 500 Memory I / F circuit 600 Common DMA test control circuit 700 External memory

Claims (10)

In a controller device in which a plurality of DMA circuits access a common memory,
An interface circuit to which each DMA circuit is connected;
An arbitration circuit for arbitrating an access request of each of the DMA circuits;
A control circuit for simultaneously activating the DMA circuits and checking the operation of the arbitration circuit without passing through the interface circuit;
A controller device comprising: 2. The controller according to claim 1, wherein the control circuit outputs a common activation signal for simultaneously activating the DMA circuits, and measures an execution time from activation of the DMA circuits to completion of data transfer. apparatus. In a controller device in which a plurality of DMA circuits access a common memory,
An interface circuit to which each DMA circuit is connected;
An arbitration circuit for arbitrating an access request of each of the DMA circuits;
A control circuit that individually selects the DMA circuits and checks a combination operation of the arbitration circuits without passing through the interface circuit;
A controller device comprising: The control circuit activates a DMA circuit to which an interface circuit other than the interface circuit to be measured is connected, and measures an execution time from activation of the DMA circuit to which the interface circuit to be measured is connected until completion of data transfer. The controller device according to claim 3, wherein The controller device according to claim 2, wherein the control circuit diagnoses a state of the arbitration circuit based on a change in the execution time. An image forming apparatus comprising the controller device according to claim 1. In a memory control method in which a plurality of DMA circuits access a common memory,
An interface circuit to which each DMA circuit is connected;
An arbitration circuit for arbitrating an access request of each of the DMA circuits;
A memory control method comprising: simultaneously activating the DMA circuits; and confirming the operation of the arbitration circuit without passing through the interface circuit. In a memory control method in which a plurality of DMA circuits access a common memory,
An interface circuit to which each DMA circuit is connected;
An arbitration circuit for arbitrating an access request of each of the DMA circuits;
A memory control method comprising: selecting the DMA circuits individually; and checking a combination operation of the arbitration circuits without passing through the interface circuit. A computer program for causing a computer to execute the memory control method according to claim 7. A recording medium in which the computer program according to claim 9 is read and executed by a computer.

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