JP2005004348A - Bus transfer device and image forming device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To definitely ensure that a plurality of functional units whose latency of access to a memory or the like should be ensured have such values. <P>SOLUTION: A bus transfer device comprises: the plurality of functional units consisting of access request issuing functional units 101 to 104 and non-access-request-issuing functional units 105 to 108; an RBUS 121 that is a bus forming a flow of data input into the access request issuing functional units 101 to 104; a TBUS 130 that is a bus forming a flow of data output from the access request issuing functional units 101 to 104; a TBUS arbiter 109 for handling requests for access to other functional units via the TBUS 130 and arbitrating the right to use the TBUS 130; and an RBUS arbiter 110 for arbitrating the right to use the RBUS 121. The TBUS arbiter 109 performs bus arbitration in preset order of priority and moves a requester acquiring the bus use right to the last place. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a design and verification for each functional unit, and relates to an image forming apparatus such as a printer and a copying machine using a bus transfer device, and a bus transfer device preferably using the bus transfer device as a whole for a semiconductor integrated circuit.
[0002]
[Prior art]
Due to significant progress in semiconductor integrated technology, a circuit (system) that has heretofore been configured by a plurality of semiconductor chips can be configured by a single chip. Along with this, there is a strong demand for a mechanism that can be reused efficiently. In order to improve reusability, it is necessary to design it robustly so that it can withstand some specification changes and additional functions. Particularly important is how to guarantee the worst value of the latency of access to the memory or the like (the period from the request issuance to the response to the request).
[0003]
For example, in the case of a printer controller, in order to transfer image data to the printer engine at a constant rate, the data read from the memory is stored in a local buffer memory, the data is read from the buffer memory, and the image data is transferred to the printer engine. In this process, the buffer memory is emptied and the transfer to the printer engine must not stop. For this reason, the design is performed based on the worst guaranteed value of the latency of access to the memory. In other words, the addition of functions increases the number of requests to execute access to the memory. As a result, the worst value of the latency of access to the memory falls below the guaranteed value, and the transfer to the printer engine stops. Since this should not occur, it is desired to develop a device that guarantees the worst value of the access latency to a memory or the like even in a slight change in specifications or addition of functions so as not to be in such a state.
[0004]
As a conventional technique considering such points, the invention disclosed in Patent Document 1 is known. In the present invention, when memory access requests from a plurality of clients that need to guarantee a data transfer rate compete, data is stored in a data buffer generated by each client and provided in each client. The present invention relates to a memory access arbitration method that performs access arbitration based on the remaining buffer capacity.
[0005]
The invention disclosed in Patent Document 2 is also known. In the present invention, among bus acquisition requests from a plurality of bus masters, in order to ensure data transfer efficiency, the occurrence of a specific event temporarily reduces the bus usage frequency of other bus masters, and the priority order The present invention relates to a bus arbiter that realizes this for those who want to ensure data transfer efficiency without ignoring a request from a low bus master.
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-132707
[Patent Document 2]
JP 2002-269032 A
[Problems to be solved by the invention]
In this way, the conventional technology can guarantee the worst value of the access latency to the memory, etc., even with some specification changes and function additions, but for multiple requesters who want to guarantee the access latency to the memory, etc. It is difficult to clearly guarantee that latency.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to make it possible to clearly guarantee the value for a plurality of functional units that want to guarantee the latency of access to a memory or the like.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the first means comprises a plurality of access request issuing functional units that issue access requests to other functional units and non-access request issuing functional units that do not issue access requests to other functional units. A first bus that is a flow in a data input direction as viewed from the access request issuing function unit, and a bus in a data output direction as viewed from the access request issuing function unit. A request for access to a second bus and another functional unit is made using the second bus, and second arbitration means for arbitrating the bus use right of the second bus; First arbitration means for arbitrating the right to use the bus, and the second arbitration means performs bus arbitration in a preset priority order and acquires the right to use the bus. And wherein the moving the source to the lowest.
[0011]
The second means is characterized in that, in the first means, a request source of a specific group is interrupted to the next highest priority as the priority of the second arbitration means.
[0012]
The third means is characterized in that, in the first means, as a priority of the second arbitration means, a reserve that does not have a target request source and is not a bus acquisition target is set as a constituent factor.
[0013]
According to a fourth means, in the image forming apparatus, the bus transfer device according to the first to third means is provided.
[0014]
In the following embodiments, the access request issuing function unit is in CPU 101, DMAC0 (102), DMAC1 (103) and RSV01 (104), and the non-access request light emitting unit is in RAMC105, ROMC106, IREG107 and RSV10 (108). The first bus corresponds to the RBUS 121, the second bus corresponds to the TBUS 130, the first arbitration means corresponds to the RBUS arbitration device 110, and the second arbitration means corresponds to the TBUS adjustment device 109.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
FIG. 1 is a block diagram showing a schematic configuration of a bus transfer apparatus according to an embodiment of the present invention. The bus transfer device according to the present embodiment is formed in a semiconductor integrated circuit, and includes a CPU 101, first and second DMA controllers (DMAC) 102 and 103 (shown as DMAC0 and DMAC1, respectively), Is provided, and has an access request issuing function unit RSV01 (104) that is reserved for the future. Each of the functional units 101 to 104 is an access request issuing functional unit that issues an access request to another functional unit.
[0017]
Also, an SDRAM controller (RAMC) 105 that performs SDRAM access control, a ROM controller (ROMC) 106 that performs ROM access control, an internal register access controller (IREG) 107 that executes access to internal registers of each functional unit, A non-access request issuing function unit 108 that is not currently used and is reserved for the future is provided. Note that each of the functional units 105 to 108 is a non-access request issuing functional unit that does not issue an access request to other functional units.
[0018]
Also, the access request from each access request issuing function unit 101 to 104 is received, and based on the status of whether or not a new access request from each non-access request issuing function unit 105 to 108 can be accepted, the TBUS 130 as the second bus A TBUS arbitration device 109 is provided as second bus arbitration means for arbitrating the bus use right. In this embodiment, for the sake of simplicity of explanation, the arbitration of the TBUS arbitration device 109 is performed on the condition that all new access request acceptances from the non-access request issue function units 105 to 108 are possible. To do.
[0019]
Further, upon receiving an access request from each of the non-access request issuing function units 105 to 108, the RBUS 121 as the first bus based on the RBUS usage status as the first bus of each non-access request issuing function unit 105-108. RBUS arbitration device 110 as a first bus arbitration means for arbitrating the right to use the bus, and TBUS for selecting which one of signals 117 to 120 is to be selected and output to TBUS 130 based on the arbitration result of TBUS arbitration device 109 A selector 111 and an RBUS selector 112 that selects which of the data 126 to 129 is selected and output to the RBUS 121 based on the arbitration result of the RBUS arbitration device 110 are provided.
[0020]
113 to 116 are control signals for transmitting an access request / access permission between each of the access request function units 101 to 104 and the TBUS arbitration device 109. 117 to 120 are basic data issued to the TBUS 130 by each access request function unit. Reference numerals 122 to 125 are control signals for transmitting an access request / access permission between each non-access request functional unit and the RBUS arbitration device 110. 126 to 129 are basic data issued by each non-access request functional unit to the RBUS 121.
[0021]
FIG. 2 illustrates the arbitration of the TBUS 130.
[0022]
What is indicated as “initial setting” is the initial setting of the priority order of the TBUS 130. In the arbitration of the TBUS 130 in the present embodiment, the request source of the specific group is assigned to the next priority after the highest priority. In this embodiment, the CPU 101 is set as the request source of the specific group. Therefore, the CPU 101 always comes in the second priority. In FIG. 2, the second priority order is shaded to facilitate identification. As the actual priority order, as shown in “actual initial setting” in FIG. 2, the CPU 101 is always interrupted to the second priority order. In this “actual initial setting” state, when all of the non-access request issuing function units 105 to 108 are ready to accept requests, if there is a request from the first DMAC 102, bus arbitration is performed. 1 DMAC 102 acquires the right to use the bus, and the priority level changes to the priority level shown in “After acquiring DMA0 bus”. That is, since the first DMAC 102 has acquired the right to use the bus, the first DMAC 102 becomes the lowest order and other priorities are advanced. However, the second priority order remains unchanged.
[0023]
Similarly, when all of the non-access request issuing function units 105 to 108 are ready to accept a request in the “after DMAC0 bus acquisition” state, there is a request from the CPU 101, but there is a request from the second DMAC 103. If there is no request, bus arbitration is performed, the CPU 101 acquires the bus right, and transitions to the first “after CPU bus right acquisition” state. In this state, RSV01 (104) has the highest priority, but in this embodiment, since a request from RSV01 (104) does not occur, this part is the same as it does not exist. .
[0024]
Similarly, when all of the non-access request issuing function units 105 to 108 are ready to accept a request after the CPU bus right has been acquired, if there is a request from the CPU 101, bus arbitration is performed, and the CPU 101 The bus right is acquired, and the state is “after the acquisition of the CPU bus right” for the second time.
[0025]
FIG. 3 is a timing chart showing the timing of the TBUS arbitration device 109.
[0026]
In FIG. 3, a CPU TBUS source is a base signal of the TBUS 130 that the functional unit of the CPU 101 transmits to the TBUS selector 111, and corresponds to the signal 117 of FIG. Similarly, the DMAC0 TBUS source, the DMAC1 TBUS source, and the RSV01 TBUS source are base signals of the TBUS 130 that each functional unit transmits to the TBUS selector 109.
[0027]
The CPU TBUS REQ is a signal for requesting the use of the TBUS 130 by the CPU 101 issued to the TBUS arbitration device 109. Similarly, DMAC0TBUS REQ, DMAC1 TBUS REQ, and RSV01 TBUS REQ are signals for requesting use of the TBUS 130 issued by the respective functional units to the TBUS arbiter 109.
[0028]
The BUSY signal is a signal indicating that the non-access request issuing function units 105 to 108 can accept new access requests. TBUS 130 is a signal after selection by the TBUS selector 111. GNT is an arbitration result signal of the TBUS 130 output from the TBUS arbitration device 109.
[0029]
First, at the rising edge of the first clock, BUSY = L and the non-access request issuing function unit 105 recognizes that a new access request can be accepted, and selects the CPU 101 according to the priority order among the issued requests. As a result, the contents of the CPU TBUS source are retaken with the clock and output to the TBUS 130, and 1 is indicated in GNT, and number 1 = the CPU has acquired the bus right. Since this request is a write request, the contents of the CPU TBUS source are retaken with the clock up to the sixth clock and output to the TBUS 130. At the rising edge of the second clock, since the access request of the CPU 101 is accepted, the CPU BUS REQ is negated and the write data is output to the CPU TBUS source. Further, the non-access request issuing function units 105 to 108 detect a new request on the TBUS 130 and set BUSY to H to prohibit new bus arbitration in order to implement this. New arbitration is performed at the rising edge of 6 clocks that detect L of BUSY. Here, 3 is shown in GNT, and the bus right is given to DMAC1. Since this request is a read request, preparation for the next bus arbitration is performed without transferring write data on the TBUS 130. As described above, arbitration of the TBUS 130 is performed.
[0030]
Such a bus transfer device is used, for example, for data transfer of a digital multi-function peripheral, also called MFP (Multi Function Preference). 4 is a diagram showing a schematic configuration of an image forming apparatus including the bus transfer device shown in FIG. 1, and FIG. 5 is a block diagram showing a schematic configuration of a control circuit of the image forming apparatus shown in FIG.
[0031]
Hereinafter, the image forming apparatus according to the present embodiment will be described.
When a start key on the operation unit 30 is pressed, a document bundle placed on the document table 2 in the automatic document feeder (hereinafter ADF) 1 is fed from the bottom document. The paper is fed to a predetermined position on the contact glass 6 by the feed roller 3 and the feed belt 4. After the image data of the original on the contact glass 6 is read by the reading unit 50, the original that has been read is discharged by the feeding belt 4 and the discharge roller 5. Further, when it is detected by the document set detection sensor 7 that there is a next document on the document table 2, it is fed onto the contact glass 6 in the same manner as the previous document. The feeding roller 3, the feeding belt 4, and the discharging roller 5 are driven by a conveyance motor 26.
[0032]
The transfer papers stacked on the first tray 8, the second tray 9, and the third tray 10 are fed by the first paper feeding device 11, the second paper feeding device 12, and the third paper feeding device 13, respectively, and are conveyed vertically. The unit 14 is transported to a position where it abuts on the photoreceptor 15. The image data read by the reading unit 50 is written on the photoconductor 15 by the laser from the writing unit 57 and passes through the developing unit 27 to form a toner image. Then, the toner image on the photoconductor 15 is transferred while the transfer paper is conveyed by the conveyance belt 16 at the same speed as the rotation of the photoconductor 15. Thereafter, the image is fixed by the fixing unit 17 and is discharged by the paper discharge unit 18 to the finisher 60 of the post-processing apparatus.
[0033]
The finisher 60 of the post-processing apparatus can guide the transfer paper conveyed by the paper discharge roller 19 of the main body in the direction of the normal paper discharge roller 62 and the direction of the staple processing unit. When the switching plate 61 is switched upward, the paper is discharged to the normal paper discharge tray 64 via the transport roller 63, and when the switching plate 61 is switched downward, the staple table 68 is transported via the transport rollers 65 and 67. Can be conveyed.
[0034]
The transfer paper loaded on the staple table 68 is aligned by the paper jogger 69 every time one sheet is discharged, and is bound by the stapler 66 upon completion of a partial copy. The group of transfer sheets bound by the stapler 66 is stored in the staple completion discharge tray 70 by its own weight.
[0035]
On the other hand, the normal paper discharge tray 64 is a paper discharge tray that can be moved back and forth. The paper discharge tray section 64 that can be moved back and forth has a function of moving back and forth for each original document or each copy section sorted by the image memory and sorting the copy paper that is simply discharged.
[0036]
When forming an image on both sides of the transfer paper, the transfer paper fed from each of the paper feed trays 8 to 10 and imaged is not guided to the paper discharge tray 64 side, and the branch claw 41 for switching the path is provided. By setting it on the upper side, it is once stocked in the duplex feeding unit 80. Thereafter, the transfer paper stocked on the double-sided paper feed unit 80 is re-fed from the double-sided paper feed unit 80 to transfer the toner image formed on the photosensitive member 15 again, and the branching claw 41 for switching the path. Is set on the lower side and guided to the paper discharge tray 64. In this way, the duplex feeding unit 80 is used when creating images on both sides of the transfer sheet.
[0037]
The photoreceptor 15, the transport belt 16, the fixing unit 17, the paper discharge unit 18, and the development unit 27 are driven by a main motor 25, and the paper feeding devices 11 to 13 drive the main motor 25 by paper feeding clutches 22 to 24, respectively. Driven by transmission. The vertical conveyance unit 14 is driven to transmit the drive of the main motor 25 by the intermediate clutch 21.
[0038]
FIG. 5 illustrates a control device with a main controller as a center. The main controller 20 controls the entire image forming apparatus. A main motor 25 and various clutches 21 to 24 necessary for paper conveyance and the like are connected to the main controller 20. Further, an image processing unit (IPU) that performs display for an operator, an operation unit 30 that performs function setting input control from the operator, control of a scanner, control for writing a document image into an image memory, control for image formation from an image memory, and the like. 49, a distributed control device such as an automatic document feeder (ADF) 1 is connected. The display is performed via the liquid crystal display 31, and the function setting input from the operator is performed by the key input means 32. Each distributed controller and the main controller 20 exchange machine status and operation commands as necessary. A control program executed by each distributed control device is stored in a ROM inside each distributed control device. An IC card slot 27 is connected to the main controller 20, and control program data stored in an IC card outside the image forming apparatus is downloaded to the ROM inside the distributed control apparatus via the IC card slot 27 for control. It is possible to change the program. Note that the IPU 49 is provided with the bus transfer apparatus of FIG.
[0039]
The operation from image reading to image writing in the image forming apparatus will be described with reference to FIG. 4 again.
[0040]
The reading unit 50 includes a contact glass 6 on which an original is placed and an optical scanning system. The optical scanning system includes an exposure lamp 51, a first mirror 52, a lens 53, a CCD image sensor 514, and the like. Yes. The exposure lamp 51 and the first mirror 52 are fixed on a first carriage (not shown), and the second mirror 55 and the third mirror 56 are fixed on a second carriage (not shown). When reading a document image, the first carriage and the second carriage are mechanically scanned as described above at a relative speed of 2: 1 so that the optical path length does not change.
[0041]
This optical scanning system is driven by a scanner drive motor (not shown). The document image is read by the CCD image sensor 54, converted into an electrical signal, and processed. The image magnification is changed by moving the lens 53 and the CCD image sensor 54 in the left-right direction in FIG. That is, the positions of the lens 53 and the CCD image sensor 54 are set in the left-right direction corresponding to the designated magnification.
[0042]
The writing unit 57 includes a laser output unit 58, an imaging lens 59, and a mirror. Inside the laser output unit 58, a rotary polygon mirror (polygon mirror) that rotates at a high speed at a high speed by a laser diode that is a laser light source and a motor. Is equipped.
[0043]
Laser light emitted from the laser output unit 58 is deflected by a polygon mirror that rotates at a constant speed, passes through an imaging lens 59, is folded by the mirror, and is focused on the surface of the photoconductor 15.
[0044]
The deflected laser light is exposed and scanned in a direction (main scanning direction) perpendicular to the direction in which the photoconductor 15 rotates, and recording is performed in line units of an image signal output from a selector of an image processing unit described later. An image (electrostatic latent image) is formed on the surface of the photosensitive member by repeating main scanning at a predetermined cycle corresponding to the rotational speed and recording density of the photosensitive member 15.
[0045]
As described above, the laser beam output from the writing unit 58 is applied to the photoconductor 15 of the image forming system. Although not shown, a beam sensor for generating a main scanning synchronization signal is disposed at a position where a laser beam near one end of the photoconductor 15 is irradiated.
[0046]
As described above, according to the present embodiment, since the bus is divided into the two buses RBUS 121 and TBUS 130, it is possible to avoid the speed reduction due to the concentration of the load, and the semiconductor integrated circuit can have a preferable configuration. . As the bus allocation, TBUS130 is used for transfer of access requests and write data, and RBUS121 is used for read data. Further, since bus arbitration is performed independently, the address of the read request on the bus. The bus can be used effectively without occupying the bus until the read data corresponding to it is returned.
[0047]
Also, as the priority order of the TBUS arbitration device 109, the request source of a specific group, in this case the CPU 101, is interrupted at the next highest priority order, so that the shorter the latency, the more functional units that lead to performance improvement In addition, the timing reserved for allocation to higher-order functional units can be allocated for the purpose of improving performance in a surplus timing space that is no longer used because no request is generated. Such a configuration can be realized without adversely affecting the functional unit whose latency is to be guaranteed.
[0048]
Further, as a priority order of the TBUS arbitration device 109, a reserve that does not exist as a target request source and does not become a bus acquisition target can be configured to be set as its constituent factor. Therefore, in particular, when the reservation has the highest priority, the request source (for example, the CPU in the above description) that is the next priority becomes the highest priority in the future. The reservation function unit can be assigned to the time space for performance improvement. This can also be realized without adversely affecting the functional unit whose latency is to be guaranteed.
[0049]
Furthermore, by applying such a data transfer apparatus to an image forming apparatus, it is possible to construct an image forming apparatus that exhibits the effects described above.
[0050]
【The invention's effect】
As described above, according to the present invention, the value can be clearly guaranteed for a plurality of functional units for which the access latency to the memory or the like is to be guaranteed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a bus transfer apparatus according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram showing a TBUS arbitration method.
FIG. 3 is a timing chart showing the timing of the TBUS arbitration device.
4 is a diagram illustrating an outline of a mechanical configuration of an image forming apparatus including the bus transfer device of FIG. 1;
5 is a diagram showing an outline of an electrical configuration of an image forming apparatus including the bus transfer device of FIG.
[Explanation of symbols]
101 CPU
102 DMA controller 0
103 DMA controller 1
104 Access Request Issuing Function Unit 105 SDRAM Controller 106 ROM Controller 107 Internal Register Access Controller 108 Non-Access Request Issuing Function Unit 109 TBUS Arbiter 110 RBUS Arbiter

Claims (4)

A plurality of functional units comprising an access request issuing functional unit that issues an access request to another functional unit and a non-access request issuing functional unit that does not issue an access request to another functional unit;
A first bus which is a bus in the flow direction of data as viewed from the access request issuing function unit;
A second bus which is a bus in the flow direction of data as viewed from the access request issuing function unit;
Access requests to other functional units are made using the second bus,
Second arbitration means for arbitrating the right to use the second bus;
First arbitration means for arbitrating the first bus use right;
With
The second arbitration means performs bus arbitration in a preset priority order, and moves the request source that has acquired the right to use the bus to the lowest level. 2. The bus transfer apparatus according to claim 1, wherein a request source of a specific group is interrupted to the next highest priority as the priority of the second arbitration means. 2. The bus transfer apparatus according to claim 1, wherein the priority of the second arbitration means is set to a reserve that does not have a target request source and is not a bus acquisition target. An image forming apparatus comprising the bus transfer device according to claim 1.

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