JP2004281488A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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JP2004281488A
JP2004281488A JP2003067553A JP2003067553A JP2004281488A JP 2004281488 A JP2004281488 A JP 2004281488A JP 2003067553 A JP2003067553 A JP 2003067553A JP 2003067553 A JP2003067553 A JP 2003067553A JP 2004281488 A JP2004281488 A JP 2004281488A
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Prior art keywords
bump
wire
semiconductor device
gold
bending point
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JP2004281488A5 (ja
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Hideyuki Shinkawa
秀之 新川
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2003067553A priority Critical patent/JP2004281488A/ja
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Publication of JP2004281488A5 publication Critical patent/JP2004281488A5/ja
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Abstract

【課題】ワイヤループの高さを低く抑えることによりループが垂れるのを防ぎ、安定かつ高精度な半導体装置を提供する。
【解決手段】半導体チップ３上に形成された金バンプ４とインナーリード５上に形成された金バンプ６を金線７により接続して構成する際、金線７には第二屈曲点Ｂ及び第三屈曲点Ｃを形成し、これらバンプ間の水平距離をＬとしたとき、インナーリード５上に形成された金バンプ６と第二屈曲点Ｂ及び第三屈曲点Ｃとの距離をそれぞれ０．１５×Ｌ及び０．４×Ｌとなるよう形成し、金バンプ４と第三屈曲点Ｃの高さが金線７の高さの最高点となるように形成する。
【選択図】 図１

Description

【０００１】
【発明の属する技術分野】
この発明は半導体装置及びその製造技術に関するものであり、特に半導体チップ上のバンプにワイヤをスティッチボンド技術を用いて接続するものである。
【０００２】
【従来の技術】
半導体装置の小型化、薄型化、メモリ容量の大容量化並びに高機能化に伴い、チップヘのワイヤ配線方式も、逆ワイヤ方式、チップｔｏチップワイヤ方式などが従来から採用されていた。
そしてこれら逆ワイヤ方式及びチップｔｏチップワイヤ方式とも、チップヘのワイヤ接合に関しては、バンプ上にワイヤをスティッチボンドする技術が採用されている（例えば、特許文献１参照）。
【０００３】
【特許文献１】
特開２００１−１５５４２号公報
【０００４】
【発明が解決しようとする課題】
従来の半導体装置は以上のように構成されていたので、バンプ上にスティッチボンド技術を用いてワイヤを接続するループ方式は、第１のボンドから第２のボンドヘの接続は、打上げ形状のループとなる場合が多く、ループの形状を安定させる為に、ループ中央付近に屈曲点を配置することとなるが、この方式ではループ形状が山なりとなり、ループ高さが高く、パッケージからの金線が露出してしまうという問題点があった。
一方、ループ中央付近の屈曲点をなくすと、ループ中央付近の高さのばらつきが大きくなり、上ワイヤと下ワイヤとが接触してしまうという問題点があった。
【０００５】
又、バンプ上にワイヤをスティッチボンドする技術では、バンプ上の狭い領域にスティッチボンドする為に、キャピラリ先端部でワイヤを屈曲することができず、形成されるループは垂れやすくなり、チップエッジと接触してしまうという問題点もあった。
従って、半導体装置の小型化、薄型化、大容量化並びに多機能化を図るために、ワイヤ配線の高集積化が必要となり、バンプ上スティッチ技術を用いたループ形成の高精度制御を達成する必要がある。
【０００６】
この発明は上記のような課題を解決するためになされたものであり、ループ高さを低く抑制し、かつループが垂れることなく、ループ高さのばらつきを低減して、安定し、かつ高精度にループ形成された半導体装置を得ることを目的としている。
【０００７】
【課題を解決するための手段】
この発明の請求項１に係る半導体装置は、半導体チップ上に形成されたバンプとインナーリード上に形成されたバンプをワイヤにより接続して構成されるものであって、ワイヤには第二屈曲点及び第三屈曲点を形成し、バンプ間の水平距離をＬとしたとき、インナーリード上に形成されたバンプと第二屈曲点及び第三屈曲点との距離をそれぞれ０．１５×Ｌ及び０．４×Ｌとなるよう形成したものである。
【０００８】
【発明の実施の形態】
実施の形態１．
以下、この発明の一実施形態を図に基づいて説明する。
図１はこの発明の実施の形態１による半導体装置を示す側面図であり、図において、ダイパッド１上にダイボンド材２を介して半導体チップ３が載置されている。
そして半導体チップ３上に形成された金バンプ４とインナーリード５上に形成された金バンプ６とをワイヤとなる金線７で接続し、全体を半導体封止材８で封止する。
【０００９】
金線７には第一屈曲点Ａ、第二屈曲点Ｂ、第三屈曲点Ｃが形成され、金バンプ４と金バンプ６との水平距離をＬとした場合、金バンプ６と第二屈曲点Ｂとの距離を０．１５×Ｌ、金バンプ６と第三屈曲点Ｃとの距離を０．４×Ｌになるようにそれぞれ形成されている。
更に、金バンプ４と第三屈曲点Ｃ間は同じ高さに形成されており、この高さが金線７のループの最高点となるよう形成されている。
【００１０】
このようにループの屈曲点を、ループ長Ｌに対して相対的に、第二屈曲点Ｂを０．１５×Ｌ、第三屈曲点Ｃを０．４×Ｌの位置に分散配置し、ループ高さ最高部が、金バンプ４上スティッチ点とこの金バンプ４上スティッチ点に隣接する第三屈曲点Ｃになるようループ形状を形成することで、ループが長尺化してもループが垂れることなく、かつ半導体チップ３を基準としたときのループ高さが１００μｍ以下に安定的かつ高精度にループを形成できる。
以上のように本発明によれば、高精度なワイヤ配線が可能になり、高集積ワイヤ配線が達成でき、小型化、薄型化、大容量化並びに多機能化に対応した半導体装置を生産できる。
【００１１】
実施の形態２．
図２は、この発明の実施の形態２による半導体装置の金パンプ４部を示す側面図であり、キャピラリ８内に金線７が通されており、ポンディングパッド９上に金バンプ４が載置されている。
本実施形態においては、スティッチボンディングする際、金パンプ４を利用するものであり、金パンプ４上にキャピラリ８の先端から出た金線７を載せ、更にこの金線７を直角又は鋭角（９０°以下）に屈曲させ、金バンプ４上でスティッチボンディングするものである。これにより、スティッチ部の金線７のループの垂れを抑制できる。
又、このようにすることにより、半導体チップ３のエッジ３ａと金線７との接触を回避することができる。
【００１２】
実施の形態３．
図３〜図６はこの発明の実施の形態３による半導体装置の金パンプ４を示す側面図であり、本実施形態においては、先ず図３に示すように、金パンプ４部の中心４ａからキャピラリ８の中心８ａをワイヤ進入方向にＸだけずらし、キャピラリ８から出た金線７を金バンプ４の突起部に押し当て、金線７を直角又は鋭角に屈曲させる。
そして図４，図５に示すように、キャピラリ８を金バンプ４に押し当て、金線７を金バンプ４に圧接し、図６に示すように、最後に金線７を切断する。
【００１３】
実施の形態４．
図７，図８はこの発明の実施の形態４による半導体装置の金バンプ４部を示す側面図であり、本実施形態は上記実施の形態３によるスティッチボンディングを更に発展させたものである。
図７において、金バンプ４には突起部４ｂが設けられており、この突起部４ｂの段差Ｙは１０μｍ以上に設定されている。
又、金バンプ４の半径Ｒと突起部４ｂの半径との差Ｚは３μｍ以上に設定されている。
【００１４】
そして図８に示すように、キャピラリ８のチャンファー半径をＳとしたとき、金パンプ４の中心４ａからキャピラリ８の中心８ａのワイヤ進入方向ずらし量ＸをＸ＝Ｒ＋Ｓになるように設定する。
このようにして、バンプ突起部４ｂに金線７を押し当て、キャピラリ８を押し込むことにより、金線７を直角又は鋭角に屈曲させ、金線７を切断するようにする。
以上のように構成することにより、半導体チップ３のエッジ３ａと金線７との接触を回避することができる。
【００１５】
実施の形態５．
図９，図１０はこの発明の実施の形態５による半導体装置の金バンプ４部を示す側面図であり、本実施形態においては、図９に示すように、金バンプ４の上面をワイヤ進入方向に対して傾斜させるように構成したものである。
そして図１０に示すように、金バンプ４に金線７を押し当て、キャピラリ８を押し込むことにより、金線７を直角又は鋭角に屈曲させ、金線７を切断するようにする。
以上のように構成することにより、上記実施の形態１〜４に比べ、更に有効に半導体チップ３のエッジ３ａと金線７との接触を回避することができる。
【００１６】
【発明の効果】
この発明の請求項１に係る半導体装置によれば、半導体チップ上に形成されたバンプとインナーリード上に形成されたバンプをワイヤにより接続して構成されるものであって、ワイヤには第二屈曲点及び第三屈曲点を形成し、バンプ間の水平距離をＬとしたとき、インナーリード上に形成されたバンプと第二屈曲点及び第三屈曲点との距離をそれぞれ０．１５×Ｌ及び０．４×Ｌとなるよう形成したので、ループが長くなっても垂れることがなく、高精度にワイヤを配線することができる。
【図面の簡単な説明】
【図１】この発明の実施の形態１による半導体装置を示す側面図である。
【図２】この発明の実施の形態２による半導体装置のバンプ部を示す側面図である。
【図３】この発明の実施の形態３による半導体装置のバンプ部を示す側面図である。
【図４】この発明の実施の形態３による半導体装置のバンプ部を示す側面図である。
【図５】この発明の実施の形態３による半導体装置のバンプ部を示す側面図である。
【図６】この発明の実施の形態３による半導体装置のバンプ部を示す側面図である。
【図７】この発明の実施の形態４による半導体装置のバンプ部を示す側面図である。
【図８】この発明の実施の形態４による半導体装置のバンプ部を示す側面図である。
【図９】この発明の実施の形態５による半導体装置のバンプ部を示す側面図である。
【図１０】この発明の実施の形態５による半導体装置のバンプ部を示す側面図である。
【符号の説明】
３ 半導体チップ、４，６ バンプ、４ｂ 突起部、５ インナーリード、Ｂ第二屈曲点、Ｃ 第三屈曲点。

Claims (6)

  1. 半導体チップ上に形成されたバンプとインナーリード上に形成されたバンプをワイヤにより接続して構成される半導体装置において、上記ワイヤには第二屈曲点及び第三屈曲点を形成し、上記バンプ間の水平距離をＬとしたとき、上記インナーリード上に形成された上記バンプと上記第二屈曲点及び上記第三屈曲点との距離をそれぞれ０．１５×Ｌ及び０．４×Ｌとなるよう形成したことを特徴とする半導体装置。
  2. 上記半導体チップ上に形成された上記バンプと上記第三屈曲点の高さが上記ワイヤ高さの最高点となるように形成したことを特徴とする請求項１記載の半導体装置。
  3. 半導体チップ上に形成されたバンプとインナーリード上に形成されたバンプをワイヤにより接続して構成される半導体装置の製造方法において、キャピラリから出たワイヤを９０°以下に屈曲させ、上記バンプ上でスティッチボンディングすることを特徴とする半導体装置の製造方法。
  4. 上記バンプの中心から上記キャピラリの中心を上記ワイヤ進入方向にずらしてスティッチボンディングすることを特徴とする請求項３記載の半導体装置の製造方法。
  5. 上記バンプの半径と上記キャピラリのチャンファー半径との和を上記ずらし量に設定するとともに、上記バンプの突起部の段差が１０μｍ以上で、上記バンプの半径と上記突起部の半径との差が３μｍ以上に設定された上記バンプ上でスティッチボンディングすることを特徴とする請求項４記載の半導体装置の製造方法。
  6. 上面がワイヤ進入方向に対して傾斜した上記バンプ上でスティッチボンディングすることを特徴とする請求項４記載の半導体装置の製造方法。
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011117905A (ja) * 2009-12-07 2011-06-16 Pioneer Electronic Corp ルート選択支援装置及びルート選択支援方法
JPWO2014083805A1 (ja) * 2012-11-28 2017-01-05 パナソニックＩｐマネジメント株式会社 発光装置および発光装置の製造方法
WO2020121852A1 (ja) * 2018-12-12 2020-06-18 浜松ホトニクス株式会社 光検出装置
JP2020096158A (ja) * 2018-12-12 2020-06-18 浜松ホトニクス株式会社 光検出装置
CN113161468A (zh) * 2021-03-17 2021-07-23 佛山市国星光电股份有限公司 一种发光器件及连接线加工方法
US11513002B2 (en) 2018-12-12 2022-11-29 Hamamatsu Photonics K.K. Light detection device having temperature compensated gain in avalanche photodiode
WO2023223843A1 (ja) * 2022-05-16 2023-11-23 ローム株式会社 半導体装置
US12080822B2 (en) 2018-12-12 2024-09-03 Hamamatsu Photonics K.K. Photodetector and method for manufacturing photodetector

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011117905A (ja) * 2009-12-07 2011-06-16 Pioneer Electronic Corp ルート選択支援装置及びルート選択支援方法
JPWO2014083805A1 (ja) * 2012-11-28 2017-01-05 パナソニックＩｐマネジメント株式会社 発光装置および発光装置の製造方法
US11513002B2 (en) 2018-12-12 2022-11-29 Hamamatsu Photonics K.K. Light detection device having temperature compensated gain in avalanche photodiode
JP2020096158A (ja) * 2018-12-12 2020-06-18 浜松ホトニクス株式会社 光検出装置
CN113167638A (zh) * 2018-12-12 2021-07-23 浜松光子学株式会社 光检测装置
WO2020121852A1 (ja) * 2018-12-12 2020-06-18 浜松ホトニクス株式会社 光検出装置
US11561131B2 (en) 2018-12-12 2023-01-24 Hamamatsu Photonics K.K. Determination method and light detection device
US11901379B2 (en) 2018-12-12 2024-02-13 Hamamatsu Photonics K.K. Photodetector
US11927478B2 (en) 2018-12-12 2024-03-12 Hamamatsu Photonics K.K. Light detection device
JP7455520B2 (ja) 2018-12-12 2024-03-26 浜松ホトニクス株式会社 光検出装置
CN113167638B (zh) * 2018-12-12 2024-06-11 浜松光子学株式会社 光检测装置
US12080822B2 (en) 2018-12-12 2024-09-03 Hamamatsu Photonics K.K. Photodetector and method for manufacturing photodetector
CN113161468A (zh) * 2021-03-17 2021-07-23 佛山市国星光电股份有限公司 一种发光器件及连接线加工方法
CN113161468B (zh) * 2021-03-17 2023-01-10 佛山市国星光电股份有限公司 一种发光器件及连接线加工方法
WO2023223843A1 (ja) * 2022-05-16 2023-11-23 ローム株式会社 半導体装置

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