JP2004259744A - Electron beam lithography system, method of exposing hole pattern, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the exposure time by reducing the number of shots at the time of exposing the hole pattern of a logic device. <P>SOLUTION: The second shaping aperture 102 of an electron beam lithography system is used for exposing the hole layer of the logic device and hole patterns having high appearance ratios are formed in cells (1-21) in the hole layer. In the cells (2-21), pluralities of hole patterns are respectively arranged at intervals which are a multiple of a natural number of the interval between power supply lines in the logic device. At the center of the second shaping aperture 102, an opening 22 is formed for variable shaping beams. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electron beam exposure method, and more particularly to a reduction in exposure time of a hole layer of a logic device.
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor integrated circuit manufacturing process, a transfer technique using a reticle by light has been conventionally used as a mainstream.
On the other hand, electron beam direct writing technology has been used for advanced prototypes of advanced devices and for production of devices manufactured in small quantities due to its high resolution.However, since a point beam is used, throughput is low, and mass production is not possible. It could not be used for device fabrication.
[0003]
To improve the throughput, a variable shaped beam method has been proposed. As shown in FIG. 4, by using the corner portions of the first aperture 111 and the second aperture 112 which are rectangular, a rectangular beam having an arbitrary vertical and horizontal dimension is generated, thereby improving the throughput. Technology. With this technology, an arbitrary rectangular beam that does not exceed the maximum shot size can be generated and can be exposed with one shot, so that a dramatic improvement in throughput can be realized as compared with the direct electron beam drawing technology using a point beam. . However, even if this variable shaped beam method is used, it is not possible to cope with high integration of a semiconductor integrated circuit, and a more efficient method has been sought.
[0004]
For the purpose of reducing the number of shots, a partial batch method has been proposed. The key to improving the throughput of the electron beam direct writing method is to reduce the actual number of shots. Therefore, a second aperture (reticle) in which a relatively repetitively appearing pattern is stored in a predetermined area is prepared in advance, and the repetitively appearing pattern is exposed using the second aperture, and the repetition is performed. The pattern which is not stored in the reticle is exposed by a variable shaping beam using a pattern creation function. According to this partial batch method, the number of shots can be reduced as compared with the case where all patterns are exposed using the pattern creation function, and the throughput can be improved. However, even if the partial batch method is used, the achievable throughput is at most several wafers / hour in terms of an 8-inch wafer, which is still insufficient for practical use from the viewpoint of productivity.
[0005]
In electron beam lithography, as in optical lithography, an electron beam projection lithography technique has been proposed in which a reticle having an image completely identical to that of a chip is introduced and a reticle image is collectively transferred. Since this method completely sacrifices the pattern creation function, the success or failure of the technique depends on the reticle.
[0006]
[Problems to be solved by the invention]
As described above, the variable shaped beam method and the partial batch method including the same do not sacrifice the best pattern creation function of the electron beam lithography technology, but have a very slow processing speed and a practical processing speed. For use, it is essential to further reduce the number of shots or the required exposure time.
[0007]
By the way, it has been considered relatively easy to apply the partial batch method to a device such as a memory including a figure (common figure) having a relatively high repeatability in a device pattern.
[0008]
However, it has been difficult to apply the partial lump sum method to devices such as random logic with few common figures because the allowable number of cells in the second shaping aperture is limited. Therefore, when exposing the pattern of the logic device, the number of shots cannot be reduced by using the partial batch method, and the exposure time cannot be reduced, resulting in a problem of low throughput.
[0009]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has as its object to reduce the number of shots and the exposure time when exposing a hole pattern of a logic device.
[0010]
[Means for solving the problem]
An electron beam lithography apparatus according to the present invention is an electron beam lithography apparatus that performs partial batch exposure using an electron beam,
A second forming aperture having a plurality of cells in which a plurality of hole patterns of the logic device are arranged,
In the cell, the plurality of hole patterns are arranged at intervals of a natural number times the interval of power supply lines in the logic device.
[0011]
In the electron beam lithography apparatus according to the present invention, a length of one side of the cell is a dimension obtained by adding a half of a diameter of a hole pattern formed on a wafer to an interval between power supply lines formed on the wafer. It is preferred that:
[0012]
A method of exposing a hole pattern according to the present invention is characterized by exposing a hole pattern of a logic device using the above-described electron beam lithography apparatus.
[0013]
A method of manufacturing a semiconductor device according to the present invention includes a step of exposing a hole pattern of a logic device using the electron beam lithography apparatus.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts have the same reference characters allotted, and description thereof may be simplified or omitted.
[0015]
FIG. 1 is a conceptual diagram for explaining an electron beam lithography apparatus according to an embodiment of the present invention.
As shown in FIG. 1, an electron beam (electron beam) emitted from an electron gun is shaped into a rectangle by passing through a first shaping aperture (first shaping opening) 101. The shaped electron beam is incident on the second shaping aperture (second shaping opening) 102 while the size of the cross-sectional area is controlled by the shaping polarizer. The electron beam that has passed through the second shaping aperture 102 is converged by the objective lens, enters a predetermined position on the wafer 103 by the positioning polarizer, and draws a desired pattern.
[0016]
FIG. 2 is a view for explaining the second shaping aperture 102 of the electron beam writing apparatus according to the present embodiment. In detail, FIG. 2 is a diagram showing an example of the arrangement of the hole patterns formed in the cells (1 to 21) in the second forming aperture having the stencil structure. The arrangement example shown in FIG. 2 shows an example in which vertical and horizontal patterns are assigned so as to be compatible with a plurality of wiring layers.
The second shaping aperture 102 shown in FIG. 2 is for exposing a hole layer (contact hole layer or through hole layer) of the logic device shown in FIG. 3, for example. (1 to 21). In the cells (2 to 21), a plurality of hole patterns of a logic device are arranged. Further, in the cells (2 to 21), the plurality of hole patterns are arranged at intervals of a natural number (an integer of 1 or more) times the interval of power supply lines (wirings) of the logic device.
Generally, in the case of an electron beam lithography apparatus currently supplied to the market, the number of cells that can be selected for the second shaping aperture 102 is 100 in the case of an electron beam lithography apparatus manufactured by Advantest, and is selected by Hitachi. In this case, the number is 21.
[0017]
In the center of the second shaping aperture 102, an opening 22 for a variable shaping beam is formed.
Here, as shown in FIG. 3, when the device layer data of the hole layer is composed of only hole patterns of the same size, the pattern can be exposed only by the exposure using the partial batch method, and the exposure can be performed using the variable shaped beam method. The opening 22 is not necessary because the above is not always necessary. In this case, the cell (1) having one hole pattern may be formed in the second forming aperture 102.
On the other hand, when the device layer data of the hole layer includes hole patterns of different sizes, it is necessary to use both the partial batch method and the variable shaped beam method, so that the aperture 22 for the variable shaped beam is necessary. .
[0018]
Note that the arrangement example of the hole patterns shown in FIG. 2 is merely an example, and another arrangement example having a high hit ratio can be adopted. In FIG. 2, 21 types of cells (hole patterns) are arranged. However, the present invention is not limited to this, and the variable shaped beam opening 22 is omitted, and for example, a total of 25 types of cells are arranged. You may.
[0019]
The power supply line (wiring) pitch in the cell-based logic is about 3.5 μm when the design rule is 100 nm, and is about 2.5 μm when the design rule is 70 nm. In consideration of this, it is conceivable to further reduce the maximum shot size of 5 μm × 5 μm employed in the current partial batch exposure apparatus.
Specifically, the size of each cell (1 to 21) of the second shaping aperture 102 is set to the power supply line pitch formed on the wafer by half the length of the hole pattern formed on the wafer. , The maximum shot size can be reduced especially in devices of 100 nm or less. In this case, there is a demerit that the maximum shot size that can be exposed with the variable shaping beam is reduced, but the cell size of the second shaping aperture 102 can be reduced, and the number of cells that can be stored in the second shaping aperture 102 is increased. be able to. That is, it is possible to further increase the number of storage cells of the second shaping aperture, which is 21 for the electron beam lithography apparatus manufactured by Hitachi and 100 for the electron beam lithography apparatus manufactured by Advantest. For example, if the cell size is about 2.5 μm × 2.5 μm, the maximum storable cell number is more than doubled. Therefore, many types of cells having more complicated hole patterns can be stored. As a result, the hit rate of the partial batch cell can be further increased, and the number of shots can be reduced.
[0020]
Next, a method of extracting a pattern used for the cells 1 to 21 of the second shaping aperture 102 and an exposure method using the second shaping aperture 102 will be described.
First, layout data of a hole layer near a power supply line is created, and grouping is performed by focusing on the regularity of hole patterns in the created layout data. Among them, patterns are extracted as a pattern to be used for the cells of the second shaping aperture 102 in order from the group having the highest appearance frequency. When extracting the pattern, it is preferable to consider not only the appearance frequency but also the reduction in the number of shots. This is because a high shot number reduction effect can be obtained by placing as many hole patterns in the same cell as possible. For example, if two hole patterns are put in the same cell, the number of shots becomes １ ／, and if four hole patterns are put, it becomes １ ／. However, if a group having a low frequency of appearance is formed in the second shaping aperture 102, the hit rate decreases, and the effect of reducing the total number of shots decreases. A series of these processes, that is, extraction of a hole pattern in consideration of the reduction in the number of shots, can be performed, for example, using Vexelwin (manufactured by Advantest), which is commercially available data conversion software for an EB exposure apparatus.
Then, the extracted hole pattern is formed in each of the cells (1 to 21), thereby forming, for example, the second shaping aperture 102 having a stencil structure as shown in FIG.
[0021]
For example, when exposing a hole layer as shown in FIG. 3, the produced second shaping aperture 102 is set in an electron beam lithography apparatus. Here, FIG. 3 is a diagram showing a hole pattern and a wiring pattern in the logic device. There is a hole pattern in the pad portion of FIG. Since the hole pattern and the wiring pattern have different layers, no wiring pattern is formed on the hole layer.
Prior to exposure, the device pattern of the hole layer to be actually exposed is converted from GDS-II (stream format) data into data readable by an electron beam lithography apparatus. At the time of this data conversion, the hole patterns assigned to the cells (1 to 21) of the second shaping aperture 102 are assigned as shots. These operations can also be performed using the above-described Vexelwin (made by Advantest), but the converted data is dedicated to the electron beam drawing apparatus made by Advantest. Therefore, when using an electron beam lithography apparatus manufactured by Hitachi, it is necessary to perform data conversion using another dedicated software.
When exposing the hole pattern 31 shown in FIG. 3, the conventional variable shaping beam method shown in FIG. 4 requires three shots, but by using the cell 17 shown in FIG.
Although the variable pattern beam method requires four shots to expose the hole pattern 32 shown in FIG. 3, the exposure can be performed in one shot by using the cell 14 in FIG.
[0022]
Next, specific examples of the present invention will be described.
<Example>
First, layout data of the hole layer was created with SX9000 manufactured by Seiko Electronics. Here, all the sizes of the holes were 80 nm.
Next, after converting the created layout data into GDS-II (stream format), the data is converted into a format for Hitachi's electron beam drawing apparatus (PFH) by self-made data conversion software, and the Hitachi's electron beam drawing apparatus HL800 is used. Sent to. The total number of figures for one chip was 4568027, and the total number of shots taking into account shots using cells (partial collective openings) of the second shaping aperture 102 was 1532101.
Then, after an 8-inch wafer was subjected to a surface hydrophobization treatment using hexamethyldisilazane vapor, an electron beam positive resist ZEP-520 made by Zeon Corporation of Japan was applied to the wafer with a thickness of 0.5 μm. Thereafter, post baking was performed at 110 ° C. for 90 seconds.
Thereafter, the wafer was transferred to a vacuum chamber of an electron beam lithography apparatus, and after positioning, the data was drawn using a partial batch method. Here, the appropriate exposure amount was 70 μC / cm ² .
After drawing, the wafer was taken out of the vacuum chamber, developed by a dip method using a dedicated developer containing methyl ethyl ketone as a main component, and then rinsed to form a resist pattern of a hole layer on the wafer. .
In this example, 40 chips were exposed on one wafer, and the time required for exposing one wafer was 1 hour and 10 minutes.
[0023]
Next, a comparative example to be compared with the above embodiment will be described.
<Comparative example>
In this comparative example, an exposure experiment was performed in exactly the same manner as in the above example, except that all the electron beam lithography data was exposed by the variable shaped beam method. In addition, since it is a hole layer, the number of shots is the same as the total number of figures, that is, 4568027. In this comparative example, 40 chips were exposed on one wafer, and the time required for exposing one wafer was 2 hours and 50 minutes.
[0024]
As described above, the inventor of the present invention has proposed that even in a logic device which is generally considered to be difficult to apply the partial lump sum method, a hole pattern is formed at a multiple of a certain pitch in a region near a power line of a cell-based logic. Are found, and a hole pattern with a large number of appearances is formed in the second forming aperture 102. By exposing using the second shaping aperture 102, the partial batch method could be applied when exposing the pattern of the hole layer. As a result, the number of shots can be reduced to a fraction or less, and the actual exposure time can be shortened, as compared with the case where the conventional variable shaped beam method is used.
Furthermore, regarding the hole pattern arranged other than near the power supply line, by using a logic cell, which is arranged and designed with a certain restriction on the place and interval to some extent, assuming the use of the partial batch method, as a library (second forming aperture), The number of shots can be further reduced.
[0025]
Further, by making the size of each cell (1 to 21) of the second shaping aperture 102 equal to or less than half the size of the power supply line pitch + hole in the wafer image, especially for devices of 100 nm or less, the size is smaller than the conventional 5 × 5 μm. Can be smaller. Thereby, for example, the number of storage cells of the second shaping aperture 102, which is 21 in the case of the electron beam lithography apparatus manufactured by Hitachi and 100 in the case of the electron beam lithography apparatus manufactured by Advantest, can be increased. Therefore, a large number of hole patterns having a more complicated arrangement in the hole layer can be accommodated in the second forming aperture 102. Therefore, by selecting and exposing a hole pattern having such a complicated arrangement, it is possible to further reduce the number of shots and thereby shorten the actual exposure time.
[0026]
As a secondary effect, in the partial batch exposure method, the same pattern is always used with the same size opening, so that the size uniformity can be ensured as compared with the variable shaping beam method. For this purpose, the dimensional accuracy of the second forming aperture 102 is important. However, the size of the second forming aperture 102 is larger than the dimension on the wafer (25 times for Hitachi and 60 times for Advantest). Due to the stencil structure, high dimensional controllability can be secured, and high dimensional uniformity can be secured.
[0027]
Further, when a logic device is manufactured by optical lithography, mask revision is frequently performed in a prototype stage before mass production is applied, and the frequency of the revision is usually much higher than that in a transistor forming process. By applying the present invention, a mask revision is not required, and the cost can be reduced. Therefore, the present invention is particularly suitable in a prototype stage.
[0028]
It should be noted that the present invention is not limited to the above-described embodiments or examples, and it is apparent that the present invention can be appropriately modified within the scope of the technical idea of the present invention.
[0029]
【The invention's effect】
According to the present invention, when exposing a hole pattern of a logic device, the number of shots can be reduced and the exposure time can be shortened.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram for explaining an electron beam lithography apparatus according to an embodiment of the present invention.
FIG. 2 is a view for explaining a second shaping aperture of the electron beam writing apparatus according to the embodiment of the present invention.
FIG. 3 is a diagram showing a hole pattern and a wiring pattern in a logic device to be exposed according to the embodiment of the present invention.
FIG. 4 is a conceptual diagram for explaining a conventional electron beam drawing apparatus.
[Explanation of symbols]
1-21 cell 22 opening 31, 32 hole pattern 101 first forming aperture 102 second forming aperture 103 wafer

Claims (4)

An electron beam drawing apparatus that performs partial batch exposure using an electron beam,
A second forming aperture having a plurality of cells in which a plurality of hole patterns of the logic device are arranged,
An electron beam lithography apparatus, wherein a plurality of the hole patterns are arranged in the cell at intervals of a natural number times an interval between power supply lines in the logic device. The electron beam drawing apparatus according to claim 1,
An electron beam, wherein a length of one side of the cell is equal to or less than a distance obtained by adding a half of a diameter of a hole pattern formed on the wafer to an interval between power supply lines formed on the wafer. Drawing device. A method for exposing a hole pattern of a logic device, comprising using the electron beam lithography apparatus according to claim 1. A method for manufacturing a semiconductor device, comprising a step of exposing a hole pattern of a logic device using the electron beam lithography apparatus according to claim 1.

Images