JP2945471B2 - Charged beam mask and charged beam exposure method and apparatus using the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-throughput charged beam exposure method and a charged beam exposure apparatus using a collective exposure beam in a charged beam exposure method.

BACKGROUND ART Taking the case of exposing a pattern 20 shown in FIG. 2 as an example,
The prior art will be described with reference to FIG.

In the conventional variable shaping method, since the shape of the charged beam is only rectangular, it is necessary to perform exposure according to division according to the pattern shape as shown in FIG. Therefore, the number of shots increases for a pattern having a large number of oblique lines or a complicated pattern, so that the throughput decreases. In particular, for an exposure with a large number of patterns such as a highly integrated electronic storage element, the number of exposure shots becomes enormous, so that the exposure requires a long time.

In the above prior art, high-speed processing of exposure having a large number of patterns and having periodic repetition of a highly integrated electronic storage element or the like has not been sufficiently considered. As one method for solving this, there is an exposure method disclosed in Japanese Patent Application Laid-Open No. 59-169131.
In this idea, the shape of the charged beam was
The pattern 23 or the pattern 24 shown in the figure is prepared to have a shape that is an element part of the pattern. However, since the conventional aperture material is a metal material, its workability is poor, and it is impossible to actually form a complicated shape of a 64-Mbit dynamic random access memory (hereinafter abbreviated as MbDRAM) level. Further, in the above example, only a part of the pattern such as one oblique line or one fold line is exposed at a time, and the arrangement including the arrangement is not considered. For this reason, performing pattern division is not changed, and the number of shots is not drastically reduced. Further, when the shot density per unit area is increased due to the high integration, the total number of shots is correspondingly increased.

DISCLOSURE OF THE INVENTION The above object is achieved by exposing all patterns within a certain area to one shot at a time without pattern division. For this purpose, it is sufficient to consider all the pattern shapes and arrangements included in a certain area of the aperture and to make them all.

In addition, as the material of the aperture having a complicated pattern as described above, a semiconductor single crystal, in particular, a silicon single crystal is used.

An object of the present invention is to provide an exposure method and an exposure apparatus capable of maintaining a high throughput even with such a large number of patterns, regardless of the shot density per unit area.

Another object of the present invention is to provide an exposure method and an exposure apparatus having a high processing speed irrespective of whether a pattern is complicated or not.

Another object of the present invention is to provide an aperture stop that can be used in the above-described exposure method and exposure apparatus, and a method for manufacturing the same.

Other objects of the present invention will become apparent from the description of the specification and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 (a) is a schematic view of an exposure apparatus of the present invention, FIG. 1 (b) is a plan view showing a typical example of an aperture for a 64MbDRAM, and FIGS. FIG. 3 is a diagram illustrating a conventional aperture pattern, FIG. 4 is a diagram illustrating pattern division by a conventional variable shaping method, and FIG. 6 is a contact diagram of a 64 Mb DRAM pattern. FIG. 7 shows a layer pattern, and FIG. 7 shows a 64 Mb DRAM.
FIG. 8 is a diagram showing the exposure time per wafer of the gate layer of the pattern, FIG. 8 is a diagram showing the relationship between the acceleration voltage (E ₀ ) of the incident electron beam and the range (R), and FIGS. Figure 12 shows a cross-sectional view of a single crystal silicon aperture according to the present invention, twelfth,
13, 14, 15 are diagrams showing a method of forming a single crystal silicon aperture, FIGS. 16, 17 are diagrams showing the relationship between shot density and throughput when exposing a 64Mb DRAM pattern,
FIG. 18 is a plan view showing a typical example of an aperture for a 256 Mb DRAM.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described.

First, the principle of the present invention will be described with reference to FIG. 1, FIG. 2 and FIG. For an intended repeating pattern 20, an area 21 including at least one or more repeating elements is set, and all the patterns in this area are magnified several times, and aperture means, specifically, single-crystal silicon Build in aperture 1. Further, the other several patterns are formed in the aperture 1 by the same processing. The thickness of the single-crystal silicon depends on the energy of the charged beam used for exposure. However, even the lightest electron beam, which is the charged beam, has the same range (R) as the accelerating voltage as shown in FIG. This can be dealt with by setting the silicon film thickness. 15 μm to 20 μm is a preferred thickness. In this silicon film pattern processing, fine processing on a submicron level is possible by dry etching. In the case of a 64 Mb DRAM having a minimum processing size of 0.3 μm, the area 21 can include 2 bits or more as a repetitive element when 2 μm × 2 μm or more is set. In FIG. 1 (a), a charged beam generating means, that is, a charged beam emitted from a beam source 10 passes through a first rectangular aperture 11, and is rectangularly formed on the aperture 1 by two shaping lenses 12, 14 serving as control means. It is imaged as a beam. For pattern selection, the deflector 13 as control means
Only the desired pattern portion is irradiated. The beam formed into a pattern shape is reduced and imaged on a wafer 19 as a processing object by a swingback deflector 18 as a control means, a reduction lens 15 and an objective lens 16. Needless to say, a photoresist is provided on the wafer 19.
This is repeated while moving by the pattern pitch, whereby a desired pattern 20 is obtained.

In the above exposure method, the number of shots is obtained by dividing the entire area of the pattern by the area of the region formed in the aperture 1, and does not depend at all on the complexity of the pattern shape. For this reason, the number of shots can be significantly reduced as compared with the related art.

The time required for exposure is determined by the product of the sum of the exposure time for one shot and the electrostatic waiting time of electron optics and the total number of shots required for exposing the entire pattern. According to the present invention, it is possible to reduce the total number of shots to at least about half and at most one-thousandth or less of the above, as compared with the conventional method. Naturally, the effect of reducing the number of shots further increases as the area of the region formed in the aperture increases. Next, more specific examples will be described.

Example 1 Examples of exposure of a 64 mb DRAM pattern having a minimum processing dimension of 0.3 μm are described as first, second, eighth, ninth, tenth, eleventh, thirteenth, thirteenth, and thirteenth.
This will be described with reference to FIG.

In the following description, in the drawings, reference numeral 1 denotes a second shaping aperture, 2, 6 denotes an aperture pattern of a gate layer, 3, 5, 7
Is an aperture pattern, 4 is a rectangular pattern, 8 is an aperture pattern of a contact layer, 9 is an aperture for a gate pattern of a 256 Mb DRAM, 10 is a charged beam source,
11 is the first molded aperture, 12 is the first molded lens, 13
Is a shaping deflector, 14 is a second shaping lens, 15 is a reduction lens, 16 is an objective lens, 17 is a swingback lens, 18 is an auxiliary lens, 19 is a wafer, and 20 is a gate layer of a 64 Mb DRAM. Pattern, 21 is a 2 μm × 2 μm area, 22 is 4 μm
× 4 μm area, 23 and 24 are aperture patterns, 25 is 6
4Mb DRAM contact layer pattern, 26 is a (100) silicon substrate, 26 'is a silicon thin film, 27 is a silicon dioxide film, 28 is a gold thin film, 29 is a high concentration layer, 30 is an opening pattern, 31 Indicates a back opening pattern, 32 and 32 'indicate a silicon nitride film, 33 indicates a resist, and 34 indicates a silicon thin film portion.

2 is a pattern of a gate layer of a switching MOS transistor constituting a memory cell of a 64 Mb DRAM. Here, assuming an area 21 of 2 μm × 2 μm, 2-bit pattern elements can be captured. The reduction ratio of the electron beam writing apparatus shown in FIG. 1 is 1/25.
Therefore, the two-bit pattern shape and its arrangement were multiplied by 25 as they were, and formed on the aperture 1. here,
The minimum dimension on the aperture is 7.5 μm, and
Since it is a process with a complicated shape including diagonal lines,
Processing was performed using a silicon single crystal having an excellent fine workability as an aperture material. The structure of this aperture is
Shown in the figure. FIG. 1 (b) is a plan view of the aperture,
FIG. 9 is a sectional view of the aperture. Reference numeral 2 in FIG. 1B denotes an opening for the gate layer. Region 21 in FIG.
Corresponding to An opening for exposing a 4 μm × 4 μm area of the same gate layer is indicated by reference numeral 6. Reference numeral 3 denotes a wiring layer,
Reference numeral 7 denotes an opening for exposing a 4 μm × 4 μm area of the same wiring layer, and reference numeral 4 denotes a wiring connection hole (contact hole).
Reference numeral 8 is an opening for a contact hole in a different arrangement, reference numerals 5 and 9 are openings for an aluminum wiring layer, 5 corresponds to 2 μm × 2 μm, and 9 corresponds to 4 μm ×
It corresponds to 4 μm.

Reference numeral 44 denotes a rectangular opening similar to the conventional one for use in a large area. The hatched portion in FIG. 1 (b) is the opening.

A square line surrounding each opening indicates a region (2 μm × 2 μm or 4 μm × 4 μm) corresponding to the exposure target.

The openings 2, 3, 4, and 5 in FIG. 1B are the minimum repeating units according to the present invention. These openings are a unit capable of exposing a complete pattern only by repeating exposure. From the results of FIG. 8, the thickness of the silicon thin film portion may be 20 μm in the case of the electron beam source 1 having the acceleration voltage of 50 kV used this time. The pattern processing was performed with a dimensional accuracy of 0.5 μm or less using dry etching. A method for creating this aperture will be described. First, after a resist 33 is spin-coated on a (100) silicon substrate 26 shown in FIG. 12 (a), a desired pattern 30 is exposed and developed by a conventional variable molding exposure method (FIG. 12 (b) ). Next, using the resist pattern 33 as a mask, 20 μm
Etching to a depth of m is performed (FIG. 12 (c)). Thereafter, as shown in FIG. 12 (d), the (100) silicon substrate 2
After a resist pattern 31 is formed on the back surface of 6, a silicon thin film 34 of 20 μm is formed by etching with an aqueous solution of potassium hydroxide or pyrocatechol as shown in FIG. 12 (f). Finally, as a surface protective film, 0.3 μm gold 2
8 is completed by vapor deposition. Alternatively, as shown in FIG. 13, by changing the processing order, first forming the silicon thin film portion 34 by wet etching, and then forming a pattern by dry etching, the aperture can be created with exactly the same accuracy. . Also, as a silicon substrate, 20μ from the surface
When a bonded silicon substrate including a silicon dioxide film 27 inside or a silicon substrate having a high-concentration layer 29 into which ions such as boron are implanted from the surface to a depth of 20 μm is used, the film of the thin film portions 26 ′ and 29 is formed. The aperture could be created with good thickness controllability. In both cases, the creation process is the first
It is common with Figures 12 and 13. FIG. 14 shows a production process using a bonded substrate, and FIG. 15 shows an aperture production process using an ion-implanted substrate. In either case,
Since the etching is stopped at the silicon dioxide film 27 or the ion-implanted film 29 during the back surface etching of the potassium hydroxide aqueous solution or the like in (d), the thickness control of the silicon thin film portions 26 'and 29 can be easily performed. When a bonded substrate is used, the oxide film 27 is finally removed with hydrofluoric acid as shown in FIG. In each case, the same result was obtained even when the back surface etching was performed prior to the formation of the front surface pattern, as in FIG.

In the formation of the pattern on the surface, the pattern other than the gate layer was similarly formed in the same aperture 1 for the layer to be exposed and the variable pattern rectangular pattern 44 conventionally used. The gate pattern 2 which is one of the patterns of the aperture 1 was selected by the deflector 13 and the wafer 19 was exposed. A pattern obtained by one shot using this method is equivalent to a pattern obtained by performing 20 shots in the conventional variable molding method shown in FIG. Therefore, the number of shots in the memory array section can be reduced to one twentieth of the conventional case.

Second Embodiment Similarly, an embodiment in which a 4 × 4 μm region of a 64 Mb DRAM pattern is exposed collectively is described in the first, fifth, sixth, seventh and first embodiments.
This will be described with reference to FIGS. The devices used are the same as in the first embodiment. In this case, the 4 × 4 μm regions 22 and 222 include a 12-bit element pattern. The most complicated pattern is the gate layer described in the first embodiment. When this is exposed by the conventional variable shaping method, 120 shots are required. With 64Mb DRAM, 64M bits are exposed even with the memory pattern alone. Conventional variable shaping requires 10 shots per bit, so the total number of shots per chip is 6.4 × 10 ⁸ shots . In contrast, in the present invention, the number of shots is reduced to 5.3 × 10 ⁶ shots. As in the first embodiment, a 64 MbDR
The pattern shape and its arrangement included in the 4 × 4 μm area of the AM pattern were multiplied by 25 as they were, and a rectangular pattern for all layers was created. Gate layer pattern 6 by deflector 13
Was selected and exposure was performed. As shown in FIG. 7, the exposure time when 100 chips were exposed per wafer was 3 hours or more in the conventional variable molding method,
In the exposure according to the present invention, all chips could be exposed in 1.5 minutes.

Subsequently, a contact layer different from the gate layer was exposed to the second wafer. Since the contact layer pattern 25 (FIG. 8) has already been formed in the aperture 1, the deflector 13 can be used without changing the aperture.
Selects pattern 8. This pattern is an example of the simplest pattern. With this pattern, one pattern can be exposed in one shot in the case of the conventional variable molding. Since there are 3.2 × 10 ⁷ patterns per chip, the conventional exposure method requires only one pattern in the memory array.
The total number of shots per chip is 3.2 × 10 ⁷ shots. Next, the exposure according to the present invention will be described. In FIG. 6, in the 4 × 4 μm area 222, there are patterns for six shots in the prior art, so that the total number of shots per chip only in the memory array portion according to the method of the present invention is 5.3 × 10 ⁶ same as the total number of shots
It is a shot. Actually, the exposure time when 100 chips were exposed per wafer was 7.5 minutes in the case of the conventional variable shaping method, but all the chips could be exposed in 1.5 minutes in the exposure according to the present invention. As described above, in the present invention, a high throughput can be realized without depending on the pattern density by dedicating the aperture pattern (opening) to the target pattern layer. The exposure time per wafer (T) is the resist sensitivity (S), the current density (J), the waiting time (t) of the electron optical system, the total number of shots (N), and the overhead time (t ₀ ) such as evacuation. Expressed as T = (S / J + t) × N + t ₀ . here,
As a standard value of each parameter, the resist sensitivity (S) is 1
μC / cm ² , electron beam current density (J) is 10 A / cm ² , electron optical system waiting time (t) is 100 ns, overhead time (t ₀ )
FIGS. 16 and 17 show the throughput when only the memory section is exposed, assuming 160 seconds. The horizontal axis shows the exposure shot density, and the vertical axis shows the throughput, and shows the results of examining the effect on the throughput when each parameter is changed. FIG. 16 (a) is a diagram in which the register sensitivity (S) is changed to 0.5, 1, 2.5 μC / cm ² ,
FIG. (B) shows the current density (J) changed to ²⁰ , 10, 5 A / cm ^2, and FIG. 17 (a) shows the electrostatic waiting time (t) of 50, 100, 2
FIG. 17B is a diagram in which the overhead time (t ₀ ) is changed to 80, 160, and 320 μC. From this result, it can be seen that the one that most affects the throughput is the shot density, that is, the total number of shots (N) itself. In the conventional variable shaping method, a more complicated pattern such as a gate layer has a higher shot density, so that the throughput is significantly reduced. On the other hand, according to the present invention, the exposure shot density is constant irrespective of the pattern contents, so that the same high throughput can be obtained with any layer pattern. In actual memory exposure, in addition to the repetitive pattern, peripheral circuits with poor periodicity are included, so the rectangular pattern 44 built in the aperture is selected and the variable shaping method is used together. The number is less than 10% of the whole and has little effect on the throughput. As a result, the exposure of any layer can be performed at a constant and high speed, so that in more than 100 memory processing steps, not only can the process be operated without delay caused by complex layers, but also the processing time Has the advantage that an accurate process schedule can be set.

Further, even if the integration degree is advanced, as in the case of 256Mb DRAM, this method only increases the number of patterns that can be formed in the aperture, such as the gate layer pattern 35 in FIG. The shot density does not change as shown in FIGS.

In FIG. 18, reference numeral 35 denotes an aperture for a gate layer of a 256 Mb DRAM, reference numeral 36 denotes an aperture for a contact layer of a 256 Mb DRAM, reference numeral 37 denotes an aperture for a contact layer of a 256 Mb DRAM, reference numeral 38 denotes an aperture for an aluminum layer of a 256 Mb DRAM, and reference numeral 39 denotes a variable shape. Reference numeral 40 denotes a rectangular aperture and a region corresponding to 4 μm × 4 μm on the wafer.

Therefore, the throughput in the exposure of the 256 Mb DRAM was almost as high as that of the 64 Mb DRAM.

When the gate layer pattern 9 in FIG. 18 is exposed by the conventional variable molding method, 320 shots are required.

In the present invention, as described above, the pattern density (that is,
High throughput is maintained for any complex pattern since the throughput does not change with the complexity of the pattern. Therefore, when used for exposure of highly integrated elements,
The effect is that not only the performance is maintained in every layer, but also a high throughput is maintained for the degree of integration of any generation.

In addition, it goes without saying that the above-mentioned features are more effective as the area that can be exposed at one time is larger.

In this embodiment, the electron beam exposure has been described. However, the same effect can be obtained in the exposure using an ion beam.

INDUSTRIAL APPLICABILITY The present invention is useful for a method for manufacturing a semiconductor device, particularly for a method for manufacturing ultra-highly integrated dynamic random access memories, static random access memories, various logics, microcomputers, and the like. The industrial applicability is great in that the throughput, which is the biggest drawback of the electron beam exposure method, is improved, and the electron beam exposure method can be used for actual production.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-246318 (JP, A) JP-A-2-114513 (JP, A) JP-A-2-76216 (JP, A) JP-A 52-1979 119185 (JP, A) JP-A-62-260322 (JP, A) JP-A-54-71992 (JP, A) JP-A-53-144676 (JP, A) JP-B-58-24009 (JP, B2) (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 21/027

Claims (18)

(57) [Claims] 1. A mask for a charged or electron beam, comprising: a mask substrate; a first opening formed with a first pattern in the mask substrate; and an area of the mask substrate different from the first opening. Forming a second pattern in which a second pattern formed by repeating the first pattern in the size thereof is formed in a region different from the first and second openings of the mask substrate to form a rectangular pattern At least one
Said mask comprising a plurality of third openings. 2. A charged or electron beam mask, comprising: a mask substrate; a first opening in which a first pattern is formed in the mask substrate; and an area of the mask substrate different from the first opening. A second opening in which a second pattern in which the first pattern is repeated with the size thereof is formed; and a first opening formed in the mask substrate in a different region from the first opening. The mask, wherein the mask includes at least one third opening having a rectangular pattern larger than the second pattern. 3. The mask according to claim 1, wherein said mask substrate is formed of a material mainly containing silicon. 4. The mask according to claim 1, wherein said first opening forms a plurality of first repeating patterns of different types, and said second opening is The mask, wherein a plurality of different types of second repeating patterns corresponding to the first repeating patterns are formed. 5. The mask according to claim 1, wherein the mask substrate is a bonded substrate including an oxide film. 6. The mask according to claim 5, wherein the material of the bonded substrate is a semiconductor. 7. A charged beam exposure method for exposing a semiconductor substrate to a repetitive pattern using a charged beam, comprising: a first opening in which a first pattern is formed; and a region different from the first opening. A second opening in which a second pattern formed by repeating the first pattern with the size is formed,
Selecting the first pattern from the substrate having the above, exposing the first pattern to the semiconductor substrate, selecting the second pattern from the mask substrate, and replacing the second pattern with the semiconductor The above-described charged beam exposure method, comprising exposing a substrate. 8. A charged beam exposure method for exposing a semiconductor substrate to a repetitive pattern using a charged beam, comprising: a first opening in which a first pattern is formed; and a region different from the first opening. A second opening in which a second pattern formed by repeating the first pattern with the size is formed,
Selecting the third pattern from a mask substrate having a third opening in which a rectangular pattern larger than the first and second patterns is formed, and transferring at least a part of the third pattern to the semiconductor substrate. The above charged beam exposure method, comprising: exposing. 9. A pattern exposure apparatus, comprising: a) a charged beam generating means; b) a mask for forming a pattern, a mask substrate; and a first pattern formed on the mask substrate with a first pattern formed thereon. An opening formed in a region of the mask substrate different from the first opening, a second pattern formed by repeating the first pattern with the same size, and a second opening formed in the mask substrate. At least one formed in a region different from the first and second openings and formed in a rectangular pattern
A pattern exposure apparatus, comprising: the mask including a plurality of third openings; and c) means for controlling the charged beam. 10. An electron beam exposure apparatus, comprising: a) an electron beam generating means; b) a mask for forming a pattern, a mask substrate; and a mask formed with a first pattern on the mask substrate. A second opening formed by repeating the first pattern in a region of the mask substrate different from the first opening to form a second pattern having a multiple size larger than the first opening; Said mask including at least one third opening formed in a region different from said first and second openings and having a rectangular pattern larger than said first and second patterns; c) Means for controlling the charged beam. 11. An exposure apparatus according to claim 9, wherein said mask controls said charged beam plane projected shape, and said mask has an opening for controlling said charged beam plane projected shape. A thin film region, and a thick film region that supports the thin film region and is thicker than the thin film region. A main material forming the thin film region and a main material forming the thick film region are the same material. , The above exposure apparatus. 12. The exposure apparatus according to claim 11, wherein said thin film region is a semiconductor. 13. The exposure apparatus according to claim 11, wherein said thin film region has a thickness of 15 to 20 μm. 14. The exposure apparatus according to claim 9, wherein the mask substrate is a bonded substrate including an oxide film. 15. The exposure apparatus according to claim 14, wherein a material of said bonded substrate is a semiconductor. 16. A pattern exposure apparatus, comprising: a) a charged beam generator; and b) a mask for forming a pattern, the mask comprising: a mask substrate; And a plurality of second patterns formed by repeating the first pattern in a size different from the first openings in the mask substrate. At least one of a plurality of second openings formed in a region different from the first and second openings of the mask substrate and having a rectangular pattern.
A pattern exposure apparatus, comprising: the mask including a plurality of third openings; and c) means for controlling the charged beam. 17. A pattern exposure apparatus according to claim 16, wherein said mask has an opening for controlling said charged beam in a planar projection shape and for controlling said charged beam in a planar projection shape. A thin film region, having a thick film region that supports the thin film region and is thicker than the thin film region, wherein a main material forming the thin film region and a main material forming the thick film region are the same material; Exposure equipment. 18. The pattern exposure apparatus according to claim 17, wherein said thin film region is a semiconductor.