JP2004227027A - Data backup device for image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data backup device for an image forming apparatuswhich can easily and securely back up a first storage means even if a main substrate is removed from the apparatus and can reduce manufacturing cost. <P>SOLUTION: A sub-substrate mounting a primary battery and a main substrate on which a first storage means preserving setting data and a second storage means preserving image data which is backed up by a secondary battery are mounted and to which main power supply is provided are connected by a connector so that they can be attached/detached. The first storage means is backed up by the primary battery when the main substrate is connected to the sub-substrate by the connector. The main substrate mounts a data transfer means transferring setting data stored in the first storage means to the second storage means so as to make it hold data when interruption of main power supply is detected. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image forming apparatus, and more particularly to an apparatus capable of easily backing up setting data and the like backed up by a primary battery even when a main board is removed.
[Prior art]
Conventionally, data backup when the power of an image forming apparatus used for a facsimile or the like is turned off is performed by power supply from a battery. For example, the following techniques are known as related art.
[Patent Document] Japanese Patent Application Laid-Open No. 08-328965
FIG. 3 shows a circuit configuration proposed in this document.
This circuit uses the backup battery 108 mounted on the extended memory board 106 when the extended memory board 106 is connected to the main control board 101 when the first memory element 102 that needs to be backed up and is provided on the main control board 101 is connected. , With the second storage element provided on the extended memory board 106.
[0003]
Therefore, in this circuit configuration, data stored in the DRAM provided as the first storage element 102 on the main control board 101 and the data stored in the DRAM provided as the second storage element 107 on the extended memory board 106 are turned off. The main control board 101 and the extended memory board 106 are sometimes held by a backup battery 108 mounted on the extended memory board 106, but are connected by a detachable connector 104, and a backup circuit is formed only when the connector 104 is connected. It is a mechanism that works.
[Problems to be solved by the invention]
However, in this example, since the first and second storage elements 102 and 107 are mounted on the main control board 101 and the extended memory board 106, the wiring patterns of both boards 101 and 106 are complicated, and the multi-layer wiring It is a substrate, which increases the manufacturing cost.
[0004]
Further, when the main control board 106 is detached from the apparatus for maintenance, in order to retain data, it is necessary to handle the main control board 101 and the extended memory board 106 with the connector 104 connected. Difficulties have arisen.
[0005]
According to the present invention, in order to improve the situation, the manufacturing cost is reduced, and even when the main power supply is turned off and the main control board is removed from the apparatus, the data stored in the primary storage means can be reliably backed up. To provide a backup device that can be used.
[Means for Solving the Problems]
The present invention is proposed to achieve the above object, and in claim 1, a sub-board on which a primary battery is mounted, a first storage means which is backed up by the primary battery and stores setting data, and a secondary battery The second storage means which stores the image data, which is backed up in, is mounted, and the main board to which the main power is supplied is detachably connected by a connector to form a basic configuration, The storage means is backed up by the primary battery when the main board and the sub-board are connected by the connector, and the main board has the first storage And data transfer means for transferring data stored in the means to the second storage means.
[0006]
According to a second aspect of the present invention, in the first aspect, when the data transfer unit detects that the main power supply interrupted by removal of the main board or the like is turned on again, the second data is transferred from the first storage unit. The data transferred and stored in the storage means is returned to the first storage means and transferred.
[0007]
Further, the third aspect is characterized in that, in the first or second aspect, the sub-substrate is configured as a single-sided, single-layer wiring board.
[Action]
According to the image forming apparatus of the first aspect, when the main power supply is cut off due to the work of removing the main board, the data transfer unit transfers the setting data stored in the first storage unit to the image data and the like. Automatic transfer to the stored second storage means. Therefore, if the main board is detached from the sub-board after the data transfer, the setting data held by the first storage means is backed up by the secondary battery mounted on the main board, so that it is unnecessary. Will not disappear.
[0008]
According to the image forming apparatus of the second aspect, after the main power supply is turned on again after the main board is connected to the sub-board, the data transfer means transfers the data from the first storage means to the second storage means. The transferred setting data is transferred to the first storage means again. As a result, the first storage means is backed up by both the main power supply of the main board and the sub-board secondary battery, so that the user does not need to perform any special operation or processing for retaining the setting data.
[0009]
According to the image forming apparatus of the third aspect, since the sub-substrate is formed of a single-sided, single-layer wiring substrate having a simple structure, the manufacturing cost can be reduced.
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing the configuration of an embodiment of the image forming apparatus of the present invention.
[0010]
Here, 1 is a main board of four-layer wiring, 2 is a sub-board of single-layer wiring, and a primary battery 3 is mounted on the sub-board 2.
On the main board 1, mounted are diodes 4 to 7, a CPU 8, a memory bus interface 9, an SDRAM 10 constituting a primary storage unit, an SRAM 11 constituting a secondary storage unit, and a secondary battery 12 charged as needed with a main power supply Vcc. Have been. The main board 1 and the sub-board 2 are connected to each other by a connector 13 and can be freely attached and detached. The connector 13 includes a connection portion 13a on the main board 1 side and a connection portion 13b on the sub board 2 side.
[0011]
In this embodiment, the data transfer means 14 is configured by combining the CPU 8 and the memory bus interface 9 and performs data transfer processing as described later, but is limited to such a combined configuration. Not something.
[0012]
The anodes of the diodes 4 and 6 are connected to the main power supply Vcc, the anode of the diode 5 is connected to the positive electrode of the secondary battery 12, and the anode of the diode 7 is connected to the primary battery 3 of the sub-board 2 via the connector 13. Connected to positive electrode. On the other hand, the cathodes of the diodes 4 and 5 are connected to each other, and further connected to the CPU 8, the memory bus interface 9, and the power supply terminals of the SDRAM 11.
The cathodes of the diodes 6 and 7 are connected to each other, and further connected to a power supply terminal of the SRAM 10. The ground terminal of the CPU 8, the memory bus interface 9, the SDRAM 11 and the negative electrode of the secondary battery 12 are connected to each other, and further connected to the negative electrode of the primary battery 3 via the connector 13, and these are held at the same potential. .
[0013]
The CPU 8 and the memory bus interface 9 are connected by a system bus, and the memory bus interface 9 and the SDRAM 11 and the SRAM 10 are connected by a memory bus. The memory bus interface 9 accesses the SDRAM 11 or the SRAM 10 in accordance with a command from the CPU 8, and sends an RAS signal, a CAS signal, a RW signal, an OE signal and the like to the SDRAM 11, and further multiplexes and sends an address signal. Also, it sends an RW signal, an OE signal, an address signal, etc. to the SRAM 10.
[0014]
According to the backup device having the above-described configuration, power is supplied from the main power supply Vcc during the normal power-on period, and the CPU 8 performs the setting data such as the transmission source data and the data for one-touch transmission held in the SRAM 10. , The image data is stored in the SDRAM 11 or the image data stored in the SDRAM 11 is read and processed. At this time, the power supply voltage dropped by the diode 4 is applied to the power supply terminals of the CPU 8, the memory bus interface 9, and the SDRAM 11, and the power supply voltage dropped by the diode 6 is applied to the power supply terminal of the SRAM 10.
The power supply voltage dropped by the diodes 4 and 6 has a higher potential than the voltage generated by the primary battery 3 or the secondary battery 12, so that a current flows from the primary battery 3 or the secondary battery 12 to each of the members 8 to 11. It does not flow.
On the other hand, when the power supply is off, the main power supply Vcc becomes high impedance, and the voltage generated by the secondary battery 12 is applied to the power supply terminals of the CPU 8, the memory bus interface 9, and the SDRAM 11 through the diode 5, and the power supply terminal of the SRAM 10 , The voltage generated by the primary battery 3 is applied through the diode 7. Therefore, even when the power is off, the CPU 8, the memory bus interface 9, and the SDRAM 11 can operate with the secondary battery 12, and the SRAM 10 can operate with the primary battery 3. However, from the viewpoint of battery capacity, it is desirable that the CPU 8 be in the sleep state in which the clock is stopped during the power-off period, and for that purpose, the SDRAM 11 is desirably in the self-refresh state with low power consumption.
[0015]
Next, the operation of the backup device will be described with reference to the flowchart of FIG.
At the start of the operation, the CPU 8 waits for an interrupt processing request (No in step S1 and step S2). Here, the interrupt request informs the CPU 8 of a normal processing request, power off, and the like. When an interrupt is input (Yes in step S2), the CPU 8 masks the interrupt to prevent multiple interrupts (step S3), and determines whether the received interrupt is power off (step S4). . Then, when determining that the interruption is to notify the power-off (Yes in step S4), the CPU 8 changes the power display LED (not shown) from the lighting state to the blinking state (step S5). Such processing can be easily realized by connecting the LED to the programmable port of the CPU 8.
[0016]
Thereafter, the CPU 8 reads the setting data held in the SRAM 10 through the memory bus interface 9 and writes and transfers the setting data to an empty area of the SDRAM 11 (step S6). When this data transfer process is completed, the CPU 8 instructs the memory bus interface to shift the SDRAM 11 to the self-refresh mode (step S7), turns off the power display LED (step S8), and accepts an interrupt. (Step S9), and enters a sleep state in which the clock stops (step S10). This sleep state continues until an interrupt is input again, but the interrupt is monitored by the hardware function of the CPU 8 (No in steps S11 and S12). During the sleep state, the user can freely perform maintenance such as attaching and detaching the main board 1 and removing and charging the primary battery 3 and thus, there is no fear that data in the SDRAM 11 will be lost during this time.
[0017]
Then, when the user turns on the main power supply Vcc again thereafter, this is input to the CPU 8 as an interrupt, and the clock of the CPU 8 is restarted (Yes in step S12, step S13). When restarting the processing, the CPU 8 first masks the interrupt and prohibits multiple interrupts (step S14). Thereafter, the power LED is turned on and off (step S15), and the setting data saved in the SDRAM 11 is read out through the memory bus interface 9, transferred to the SRAM 10, and the contents are restored (step S16). Finally, the power display LED is turned on (step S17), the interrupt is unmasked to be accepted (step S18), and the process ends.
However, if the first interrupt is a normal processing request interrupt (No in step S2), the CPU 8 performs the requested processing (step 19), unmasks the interrupt, and accepts the interrupt (step 19). S20), the process ends.
[0018]
In the operation according to the above-described flowchart, the data transfer between the SDRAM 11 and the SRAM 10 is notified to the user by blinking the power display LED. However, this is saved, and the time is specified as, for example, 2 minutes. After that, maintenance such as removal of the main board may be allowed.
【The invention's effect】
In the image forming apparatus of the first aspect, when the main power is turned off, the setting data stored in the first storage unit is transferred to the second storage unit and backed up. The setting data stored in the first storage means is securely held even when the device is removed or when maintenance such as charging of the primary battery is performed.
[0019]
According to the image forming apparatus of the present invention, the setting data backed up by the second storage means is automatically transferred to the first storage means when the main power supply is turned on again, so that the user has a special need. There is no need to perform any operations or processes.
[0020]
In the image forming apparatus according to the third aspect, the secondary battery is mounted not on the high-cost four-layer wiring main board but on the inexpensive single-sided single-layer wiring sub-board connected by the connector to the main board. , The overall cost is reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a data backup device of the present invention.
FIG. 2 is a flowchart showing a basic operation of the data backup device.
FIG. 3 is a diagram showing a configuration of a conventional circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Main board of four-layer wiring 2 Sub-board of one-sided single-layer wiring 3 Secondary batteries 4-7 Diode 8 CPU
9 memory bus interface 10 first storage means (SRAM)
11 Second storage means (SDRAM)
12 Primary battery 13 Connector 14 Data transfer means

Claims (3)

A sub-board mounted with a primary battery, a first storage unit storing setting data, a second storage unit storing image data backed up by the secondary battery, and a main board supplied with main power. Is configured to be detachably connected with a connector,
The first storage means is backed up by the primary battery when the main board and the sub-board are connected by the connector, and the main board detects the main power supply cutoff when the main board and the sub-board are connected by the connector. A data backup device in an image forming apparatus, comprising a data transfer unit for transferring and holding setting data stored in a first storage unit to the second storage unit. In claim 1,
The data transfer means returns the setting data transferred from the first storage means to the second storage means to the first storage means when the power transfer of the interrupted main power supply is detected. A data backup device in an image forming apparatus, wherein the data backup device transfers the data. In claim 1 or 2,
A data backup device in an image forming apparatus, wherein the sub-substrate is a single-sided, single-layer wiring substrate.

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