JP2009129026A - Data management device, information processor, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a time required for saving of data when a state is shifted to a power non-supply state. <P>SOLUTION: When receiving an instruction to start data saving processing from a memory access monitoring device 70, a CPU 10 refers to access frequency of only records whose saving completion flags are "0" in an access management table 71, and stores the page ID in an RAM 30 in the order of record whose access frequency is small. The sequence of page ID stored on the RAM 30 is defined as a saving queue. Then, the CPU 10 reads the page ID at the leading of the saving queue created by the RAM 30, and specifies a memory address by referring to the access management table 71, and saves the page corresponding to the page ID to a flash memory 40. Then, the CPU 10 erases the page ID of the saved page from the saving queue, and sets the corresponding saving completion flag of the access management table to "1". <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for moving data between a storage unit that maintains a state in which data is stored by receiving power supply and a storage unit that maintains a state in which data is stored without receiving power supply.

A technique called hibernation is known in which when a computer is turned on, the work contents when the power is turned off are restored. For example, Patent Document 1 describes that when data in a volatile memory is written in a nonvolatile memory before turning off the power, the power is turned off and the power is turned off, and the power is turned on again. A technique for writing back data written in a volatile memory to a volatile memory is disclosed. Patent Document 2 discloses a technique for writing only data stored in a data area and a backup area, out of data in a volatile memory, into a nonvolatile memory before shifting to a sleep mode. According to the technique disclosed in Patent Document 2, since the amount of data to be written to the nonvolatile memory is smaller than when all the data in the volatile memory is written back, the data stored in the nonvolatile memory is reduced. Can be written back to the volatile memory in a short time.
JP 2005-115720 A JP 2007-38580 A

  When shifting to the non-power supply state as described above, all data stored in the volatile memory is written into the nonvolatile memory. In general, the time required to read / write data from / to a nonvolatile memory is longer than the time required to read / write data from / to a volatile memory, so it is quite appropriate to write all the data stored in the volatile memory to the nonvolatile memory. There is a problem that it takes time. In particular, in the case of a device equipped with a small power source such as a portable terminal, since there is no room for the remaining amount of power, all data stored in the volatile memory is stored when the power is not supplied. There is also a possibility that a situation in which data could not be written to the nonvolatile memory could be caused.

  The present invention has been made in view of such a background, and an object thereof is to shorten the time required to shift to a power non-supply state.

In order to solve the above-described problems, a data management device according to the present invention is configured to receive a power supply and maintain a state in which the data is stored, and a state in which the data is stored without receiving the power supply. The second storage means for maintaining the power and the state transition for shifting to either the power supply state for supplying power to the first storage means or the power non-supply state for not supplying power to the first storage means Means, processing execution means for executing processing using data stored in the first storage means in the power supply state, and an instruction to shift from the power supply state to the power non-supply state And a retreating unit for performing retreat processing for reading out data stored in the first storage unit part by part at different times and storing them in the second storage unit, The from the saving processing being performed by the saving means, and wherein the shifting from the power supply state to the power non-supply state to the data stored in the first storage unit.
According to the present invention, data stored in the first storage means is read out part by part at different times until an instruction to shift from the power supply state to the power non-supply state is given to the second storage means. Since the save processing to be stored is performed, the time required to shift to the power non-supply state can be shortened.

  The saving unit may start the saving process every time processing as a unit of execution by the processing execution unit is completed, and performs the saving process during a period when the process is not executed by the processing execution unit. Also good. In this way, it is possible to prevent the save process from applying a load to processes other than the save process.

  Further, the process execution means temporarily suspends execution of the process from the start to completion of the process as a unit of execution, and the save means temporarily suspends execution of the process by the process execution means The evacuation process may be performed during the period of time. In this way, the save process can be performed even during a period in which a process other than the save process is being executed.

  In the above-described aspect, the process execution unit is a CPU that executes a process according to a procedure described in a program, and a process that is a unit of execution by the process execution unit is a CPU according to a procedure described in the program. It is desirable that the task is a unit of processing to be executed.

  Preferably, when the data is divided into a plurality of partial data, the number of times the processing execution unit uses the partial data stored in the first storage unit is stored for each partial data. It is preferable that the save unit performs the save process on the partial data stored in the number storage unit before the partial data with the high number of times. In this way, since the priority of saving can be determined from the number of times partial data is used, more efficient saving processing can be performed.

  Preferably, the save unit performs the save process when the total number of times stored in the number storage unit is equal to or greater than a first threshold value. In this way, when the total number of times data is used is less than or equal to the threshold value, the data is not stored in the nonvolatile storage device, so that the execution speed of processes other than the save process can be prevented from being reduced by the save process.

  Preferably, the save unit saves the save during a period when the process is not executed by the process execution unit when the total number of times stored in the number storage unit is equal to or greater than a first threshold. A period during which processing is executed by the processing execution means when the total number of times stored in the number storage means is equal to or greater than a second threshold value greater than the first threshold value. Also in the above, it is preferable to perform the saving process. In this way, according to the total number of times of data use, “a state in which saving is not necessary” is performed until the value reaches the first threshold, and “processing execution means” is performed from the first threshold to the second threshold. If the process is not performed, the save process is performed ", and if the process is greater than or equal to the second threshold value, the process is forcibly performed even if the process is being performed by the process execution unit. Therefore, it is possible to perform an appropriate saving process according to the total number of times data is used.

  Further, preferably, the saving unit has not been able to save all the data stored in the first storage unit until there is an instruction to shift from the power supply state to the power non-supply state. In this case, after the instruction is given, the data that has not been saved may be read from the first storage unit and stored in the second storage unit. In this way, even if the storage content of the first storage unit is changed after the instruction to shift to the power non-supply state is issued, the saving process reflecting the change can be performed.

  Preferably, in the power supply state, when data used for processing executed by the processing execution unit is not stored in the first storage unit, the data stored in the second storage unit Is read out and stored in the first storage means, and in the second storage means, a first restoration means for storing a restoration order of related data related to the data, and the process execution means Based on the restoration order stored by the first restoration unit, the related data stored in the second storage unit is read out and stored in the first storage unit during a period when the processing is not executed by It is good to provide a 2nd decompression | restoration means. In this way, when moving from the non-power supply state to the power supply state, the data that should be restored quickly is restored, and the data that needs to be restored next is inferred based on the restored data. Since it is stored as data and restored preferentially, the data restoration process can be efficiently distributed.

  Preferably, the data size of the related data is determined for each process executed by the process execution unit. This is because the size of the related data may be different for each process.

  An information processing apparatus according to the present invention includes the data management apparatus described above and an output unit that outputs a result processed by the process execution unit.

In addition, the program according to the present invention includes a first storage unit that maintains a state in which data is stored by receiving power supply, and a second storage unit that maintains a state in which data is stored without receiving power supply. A state transition unit that shifts the computer provided to either a power supply state that supplies power to the first storage unit or a power non-supply state that does not supply power to the first storage unit; and the power In a supply state, a process execution means for executing processing using data stored in the first storage means, and in the power supply state, data stored in the first storage means in part Each of the state transition means is stored in the first storage means and functions as a save means for performing a save process that is read at different times and stored in the second storage means. From said save processing is performed by the saving means to the data, a program for transition to the power non-supply state from the power supply state.
According to the present invention, data stored in the first storage means is read out part by part at different times until an instruction to shift from the power supply state to the power non-supply state is given to the second storage means. Since the save processing to be stored is performed, the time required to shift to the power non-supply state can be shortened.

[A: Configuration]
[A-1: Overall configuration of display device]
FIG. 1 is a diagram illustrating a configuration of a display device 1 according to the present embodiment. As shown in the figure, the display device 1 includes a CPU (Central Processing Unit) 10, a ROM (Read Only Memory) 20, a RAM (Random Access Memory) 30, a flash memory 40, an operation unit 50, and a display. Unit 60, memory access monitoring device 70, and power supply unit 80. The CPU 10, ROM 20, RAM 30, flash memory 40, operation unit 50, display unit 60, and memory access monitoring device 70 are connected via a bus 90. Further, these units 10 to 70 and the power supply unit 80 are connected via a power supply line (not shown). The power supply unit 80 includes, for example, a rechargeable battery and a power supply control circuit, and supplies power to each unit constituting the display device 1 through the power supply line.

  The ROM 20 is a read-only memory, and stores a boot program that controls the startup process of the display device 1 and various control programs such as an OS (Operation System). The CPU 10 executes the control program stored in the ROM 20 and various processing programs stored in the flash memory 40 to control the operation of the display device 1 and perform various processes and obtain the processing results. Or output by the display unit 60.

  The RAM 30 is a volatile memory that receives power supply from the power supply unit 80 and maintains a state in which data is stored. In other words, the data stored in the RAM 30 continues to be stored for a period during which power is supplied from the power supply unit 80 to the RAM 30, but is erased when the power supply from the power supply unit 80 is lost. The RAM 30 is used as a work area for the CPU 10, and stores data used in processing being executed by the CPU 10, for example. This data includes various programs and functions read from the ROM 20 and the flash memory 40 and loaded into the RAM 30, as well as various values and arguments used in the processing being executed. Hereinafter, these data stored in the RAM 30 are collectively referred to as “process data”.

  The flash memory 40 is a non-volatile memory that can maintain a state in which data is stored without receiving power supply from the power supply unit 80. In addition to storing the above-described processing program, the flash memory 40 is provided with a storage area for storing processing data on the RAM 30 being processed by the CPU 10. As described above, the RAM 30 receives power supply and functions as a first storage unit that maintains the state in which processing data is stored, whereas the flash memory 40 stores processing data without receiving power supply. It functions as second storage means for maintaining the state.

  The operation unit 50 includes, for example, a pen device or a joystick, and supplies an operation signal corresponding to a user operation to the CPU 10. The display unit 60 includes, for example, a storage liquid crystal display using a cholesteric liquid crystal or electrophoresis, and a display control circuit, and displays various images under instructions from the CPU 10. The memory access monitoring device 70 is a device that monitors the access status of the CPU 10 to the RAM 30, and stores an access management table 71 in a volatile memory included in the memory access monitoring device 70. The access management table 71 is a table in which the above monitoring result is described.

[A-2: Configuration of access management table]
FIG. 2 is a diagram showing an example of the access management table 71.
As shown in FIG. 2, the access management table 71 is a table having fields such as a saved flag, a restored flag, a memory address of the RAM 30 indicating a storage location of processing data, an access frequency, and a page ID. Further, the access management table 71 has a field of total access frequency in which the total access frequency is described. In the display device 1, data is exchanged between the RAM 30 and the flash memory 40 in units called “pages”. The “memory address” in the access management table 71 is the top address of the storage area when each of these pages is stored as processing data in the RAM 30. The “access frequency” is the number of times the CPU 10 has accessed the page indicated by the memory address. This number of times is always counted by the memory access monitoring device 70 and described in the access frequency field corresponding to the page. “Page ID” is identification information assigned to each page. The “saved flag” is information indicating whether each page stored in the RAM 30 is stored in the flash memory 40, that is, whether or not the page has been saved, and “1” is saved and “0”. Means not saved. The “restored flag” is information indicating whether each page stored in the flash memory 40 is stored in the RAM 30, that is, whether or not the page has been restored. “1” is restored and “ “0” means not restored.

[A-3: Activation state of display device]
Here, the activation state of the display device 1 will be described. The display device 1 has three activation states of “on state”, “sleep state”, and “off state”, and takes one of these activation states. First, the “on state” is a power supply state in which power is supplied to each part of the display device 1, and the display device 1 performs a normal operation. In the “on state”, the CPU 10 performs various processes. Next, the “sleep state” is a state in which power is supplied to only a limited part of the display device 1 and a part of the display device 1 does not operate. In this “sleep state”, power is not supplied to the CPU 10 or the display unit 60, but power is supplied to other components (including the RAM 30). Therefore, it can be said that the “on state” is a first power supply state with high power consumption, and the “sleep state” is a second power supply state with low power consumption. The “off state” is a state when the power supply unit 80 is turned off. In this “off state”, power is not supplied to each part of the display device 1, so the display device 1 does not operate at all. The above-described transition from the “on state” to the “sleep state” is performed, for example, when the standby time during which the CPU 10 does not perform processing in the “on state” is a predetermined time or more. The transition from the “sleep state” to the “on state” is performed, for example, when the operation unit 50 is operated. As described above, the “on state” and the “sleep state” are “power supply states” that supply power to at least the RAM 30 among the respective units of the display device 1, whereas the “off state” supplies power to the RAM 30. It is a “no power supply state”.

[B: Operation]
Next, the operation of the display device 1 will be described.
[B-1: Access frequency counting process]
FIG. 3 is a flowchart showing a flow of access frequency counting processing executed by the memory access monitoring device 70. With reference to FIG. 3, the access frequency totaling process for determining the priority order for saving the data stored in the RAM 30 will be described. For example, it is assumed that when the display device 1 is in the “on state”, the user operates the operation unit 50 to browse a document represented by document data. In response to this operation, the CPU 10 generates processing data used for each processing or reads it from the flash memory 40 and stores it in the RAM 30, and executes processing for displaying a document using these processing data. . At this time, the CPU 10 executes processing in units called tasks.

  For example, when the CPU 10 executes display processing as described above, data (a set of page data) read from the flash memory 40 is stored in the RAM 30 as processing data. At this time, the memory access monitoring device 70 The access management table 71 having a format as shown in FIG. 2 is generated and stored in its own volatile memory. However, in the initial state, 0 is described in the access frequency and the total access frequency corresponding to each memory address.

  The memory access monitoring device 70 monitors the pages indicated by these memory addresses, and determines whether or not a memory access has occurred by the CPU 10 (step Sa11). Here, “memory access” refers to both operations in which the CPU 10 reads and writes a page. However, the memory access may be limited to when the page is written. This is because when only reading a page, the content of the page does not change, and it is not necessary to newly save it. While there is no memory access (step Sa11; NO), the memory access monitoring device 70 continues to monitor the page (step Sa11). On the other hand, when the CPU 10 accesses any page, the memory access monitoring device 70 determines that a memory access has occurred (step Sa11; YES), and sets the saved flag corresponding to the accessed page to “0”. (Step Sa12) The access frequency is increased by 1 (Step Sa13), and the total access frequency is increased by 1 (Step Sa14).

  Next, the memory access monitoring device 70 compares the total access frequency with a predetermined threshold Lim1 (for example, 1000 times), and determines whether the total access frequency is equal to or greater than the threshold Lim1 (step Sa15). If the total access frequency is not equal to or greater than the threshold value Lim1 (step Sa15; NO), the memory access monitoring device 70 continues to monitor the page (step Sa11). As a result, the access frequency of each page is tabulated one by one until the total access frequency reaches the threshold value Lim1 or more.

  On the other hand, if the total access frequency is greater than or equal to the threshold Lim1 (step Sa15; YES), the memory access monitoring device 70 determines whether the CPU 10 is in an idle state (step Sa16). The idle state is a state where the CPU 10 is not executing any task. If the CPU 10 determines that it is not in the idle state (step Sa16; NO), the memory access monitoring device 70 compares the total access frequency with a predetermined threshold value Lim2 (a numerical value greater than the threshold value Lim1, for example, 2000 times). Then, it is determined whether or not the total access frequency is greater than or equal to the threshold value Lim2 (step Sa17). If the total access frequency is not equal to or greater than the threshold value Lim2 (step Sa17; NO), the memory access monitoring device 70 continues to monitor the page (step Sa11). As a result, even if the total access frequency is equal to or higher than the threshold value Lim1, if the task is executed by the CPU 10, the CPU 10 prioritizes the processing of the task over the save processing and continues the processing of the task. become. However, this is until the total access frequency reaches the threshold value Lim2.

  On the other hand, when it is determined that the CPU 10 is in the idle state (step Sa16; YES) and when the total access frequency is determined to be equal to or greater than the threshold Lim2 (step Sa17; YES), the memory access monitoring device 70 Instructs the CPU 10 to start the data saving process (step Sa18). Therefore, in a state where the total access frequency is equal to or greater than the threshold Lim2 and the necessity of saving increases, even if a task is being executed by the CPU 10, this is interrupted and the computing resources of the CPU 10 are allocated to the saving process. It will be.

[B-2: Data saving process]
Next, data saving processing by the CPU 10 will be described with reference to FIG. The term “saving data” as used herein means that the data stored in the RAM 30 is stored in the flash memory 40. FIG. 4 is a flowchart showing the flow of the data saving process. When the CPU 10 receives an instruction to start the data saving process from the memory access monitoring device 70, the CPU 10 creates a save queue describing the order of pages to be saved in the RAM 30 based on the access management table 71 (step Sb11). ). Specifically, the CPU 10 refers to the access frequency of the record whose saved flag is “0” in the access management table 71 and stores the page ID in the RAM 30 in order from the record with the lowest access frequency. A permutation of page IDs stored on the RAM 30 is a save queue.

FIG. 5 is a diagram illustrating an example of the save queue.
In FIG. 2, the saved flags for page A1, page A2, and page A3 are “0”, and therefore all of these are treated as objects to be saved by the CPU 10. Since the access frequency of the page A1 is 15, the access frequency of the page A2 is 0, and the access frequency of the page A3 is 12, the page A2 → the page A3 when these data are arranged from the one with the lower access frequency. → Page A1 Therefore, the CPU 10 creates an evacuation queue in the order as shown in FIG. The order of page IDs in this save queue means the save order of pages with that page ID.

  Next, the CPU 10 reads the page ID at the head of the save queue created in the RAM 30, identifies the memory address with reference to the access management table 71, and saves the page corresponding to the page ID in the flash memory 40. (Step Sb12). Then, the CPU 10 deletes the page ID of the saved page from the save queue (step Sb13), and sets the saved flag corresponding to the page ID in the access management table 71 to “1” (step Sb14). For example, in the save queue shown in FIG. 5, in step Sb12, the CPU 10 saves the page indicated by the memory address “1A80” in which the page A2 is stored in the flash memory 40. When the saving is completed, the CPU 10 deletes the page ID “page A2” from the saving queue in step Sb13, and sets the saved flag corresponding to the page ID “page A2” in the access management table to “1” in step Sb14. To.

Next, the CPU 10 determines whether or not the save queue is empty (step Sb15). If the save queue is not empty (step Sb15; NO), the CPU 10 determines whether or not there is an interrupt process (step Sb16). The interrupt process here is a process different from the save process, and includes, for example, a process according to some user operation. If there is no interrupt process (step Sb16; NO), the CPU 10 refers to the above-described save queue and continues the data save process (step Sb12). On the other hand, when the save queue is empty (step Sb15; YES), and when there is an interrupt process (step Sb16; YES), the CPU 10 interrupts the data save process and shifts to a processing wait state, or interrupts. Transition to execution of processing.
By performing such a saving process, the CPU 10 can read out the processing data stored in the RAM 30 for each page included in the processing data at different reading timings and store them in the flash memory 40.

[B-3: State transition processing]
Next, the state transition process by the CPU 10 will be described with reference to FIG. FIG. 6 is a flowchart for explaining the flow of processing for shifting from a power supply state to a power non-supply state.
The CPU 10 determines whether or not an instruction to shift to the power supply non-supply state is given by a predetermined interrupt process (step Sc11). Here, there are various modes for the instruction to shift to the power supply non-supply state. For example, when the CPU 10 receives a migration instruction from the user via the operation unit 50, or when the CPU 10 itself generates the above-described migration instruction when a predetermined condition is automatically detected. Examples of the latter predetermined condition include a case where the CPU 10 has been in an idle state for a predetermined time or more after the above-described saving process is completed. When the above transition is not instructed (step Sc11; NO), the CPU 10 continues this determination (step Sc11).

  On the other hand, when the above migration is instructed (step Sc11; YES), the CPU 10 refers to the access management table 71 and determines whether all pages on the RAM 30 have been saved (step Sc12). ). If at least one of the saved flags in the access management table 71 is “0”, the CPU 10 determines that there is one or more pages that have not been saved (step Sc12; NO), as shown in FIG. Execute the process. On the other hand, if all the saved flags in the access management table 71 are “1”, the CPU 10 determines that all pages have been saved (step Sc12; YES), and instructs the memory access monitoring device 70. The access management table 71 is saved in the flash memory 40 (step Sc13). Then, the CPU 10 calculates a hash value of the access management table 71 and stores it in the flash memory 40 (step Sc14). This is for confirming the reliability of the access management table 71 stored in the flash memory 40 at the time of data restoration processing described later. Following the above processing, the CPU 10 stops the power supply of the power supply unit 80 and shifts to the power supply non-supply state (step Sc15).

Here, a specific example of the state transition instruction will be described, and a specific example of the above-described saving process and state transition process will be described. FIG. 7 is a time chart when a shift instruction is received from the user via the operation unit 50. The upper part of FIG. 7 represents an interrupt process, the middle part represents a general task, and the lower part represents a save process.
First, the CPU 10 executes a certain task A from time t1 to time t2. During this time, the memory access monitoring device 70 determines whether or not a memory access of the CPU 10 has occurred (step Sa11 in FIG. 3), and whenever a memory access occurs in the task A (step Sa11 in FIG. 3; YES) ), The saved flag corresponding to the accessed page is set to “0” (step Sa12 in FIG. 3), the access frequency is increased by 1 (step Sa13 in FIG. 3), and the total access frequency is further increased by 1 (FIG. 3). Step Sa14). Next, the memory access monitoring device 70 compares the total access frequency with a predetermined threshold value Lim1, and determines whether or not the total access frequency is equal to or greater than the threshold value Lim1 (step Sa15 in FIG. 3). Here, it is assumed that the total access frequency does not exceed Lim1 (for example, 1000 times) between time t1 and time t2. Therefore, the saving process is not started at time t2.

  Subsequently, the CPU 10 executes another task B from time t3 to time t5. Similarly to the above, the CPU 10 determines the occurrence of memory access even during the period in which the task B is being executed, and performs the processes of steps Sa12 to Sa14 in FIG. Here, it is assumed that the total access frequency becomes equal to or higher than Lim1 at a certain time t4 between time t3 and time t5. When detecting this at time t4 (step Sa15 in FIG. 3; YES), the memory access monitoring device 70 determines whether the CPU 10 is in an idle state (step Sa16 in FIG. 3). Since CPU 10 is executing task B until time t5 and is not in an idle state, memory access monitoring device 70 determines that CPU 10 is not in an idle state from time t4 to time t5 (FIG. 3). Step Sa16; NO), it is determined whether or not the total access frequency is equal to or greater than the threshold value Lim2 (Step Sa17 in FIG. 3). Here, if the total access frequency does not become the threshold value Lim2 or more by the time t5, the memory access monitoring device 70 has the CPU 10 in the idle state (step Sa16 in FIG. 3; YES) at the time t5. Then, the CPU 10 is instructed to start the data saving process (step Sa18 in FIG. 3). This save process is completed at time t6 when the save queue becomes empty.

  Subsequently, the CPU 10 executes another task C from time t7 to time t10. Similarly to the above, the CPU 10 determines the occurrence of memory access even during the period in which the task C is being executed, and performs the processes of steps Sa12 to Sa14 in FIG. Here, it is assumed that the total access frequency becomes Lim2 or more at a certain time t8 between time t7 and time t10. When detecting this at time t8 (step Sa17 in FIG. 3; YES), the memory access monitoring device 70 immediately suspends the task C and starts the data saving process even though the CPU 10 is not in the idle state. The CPU 10 is instructed (step Sa18 in FIG. 3). In response to this instruction, the CPU 10 immediately suspends the task C and proceeds to the saving process. When the CPU 10 completes the save process between time t8 and time t9, it resumes the suspended task C. When task C ends at time t10, CPU 10 starts saving processing for the memory access generated in task C between time t9 and time t10, and completes this at time t11.

  Then, it is assumed that at time t <b> 12, the user instructs to shift from the power supply state to the power non-supply state via the operation unit 50. Since the CPU 10 determines whether or not an instruction to shift from the power supply state to the power supply non-supply state is given (step Sc11 in FIG. 6), when the instruction is received at time t12 (step Sc11 in FIG. 6; YES), referring to the access management table 71, it is determined whether or not all pages have been saved (step Sc12 in FIG. 6). In this case, all the saving processes are completed at time t11, and no task for generating memory access is performed until time t12. Therefore, the CPU 10 saves the access management table 71 in the flash memory 40 (step Sc13 in FIG. 6). Then, the CPU 10 calculates a hash value of the access management table 71 and stores it in the flash memory 40 (step Sc14 in FIG. 6). Finally, the CPU 10 stops the power supply of the power supply unit 80 and shifts to a power supply non-supply state (step Sc15 in FIG. 6).

Thus, since the CPU 10 evacuates and saves the processing data stored in the RAM 30 in portions, the processing data stored in the RAM 30 is shifted to the power non-supply state. It is possible to keep at least a part of the evacuated. Therefore, the amount of data to be saved when shifting to the power non-supply state can be reduced, and the time required for the state transition can be shortened.
If all the data stored in the RAM 30 cannot be saved in the flash memory 40 before the instruction to shift from the power supply state to the power non-supply state is received, the CPU 10 receives the instruction. After that, data that has not yet been saved may be read from the RAM 30 and saved in the flash memory 40.

Next, FIG. 8 is a time chart showing another example of the transition to the power non-supply state. The CPU 10 executes a certain task D between time t14 and time t15. As in the case of task B and task C described above, the CPU 10 starts the save process from time t15 when the task D ends, and completes the save process at time t16. Then, the CPU 10 measures the elapsed time from the time t16, and when detecting that the time has exceeded a predetermined time Δt (for example, 1 minute), the CPU 10 saves the access management table 71 (step Sc12 in FIG. 6). , Step Sc13, and Step Sc14). Then, similarly to the above, the CPU 10 finally stops the power supply of the power supply unit 80 and shifts to the power non-supply state (step Sc15).
As described above, the CPU 10 saves the processing data stored in the RAM 30 by the time it shifts to the power non-supply state, so that the amount of data to be saved when it shifts to the power non-supply state. Can be reduced. Therefore, it is possible to shorten the time required for state transition.

[B-4: Data restoration processing]
Subsequently, referring to FIG. 9, a data restoration process for restoring the data saved in the flash memory 40 when the activation state of the display device 1 is returned from the “off state” to the “on state”. explain. The restoration of the activated state here means that after the activated state of the display device 1 is shifted from the “power supply state” to the “power non-supply state”, the “power supply state” again from the “power non-supply state”. It means to be transferred to. The data restoration is to store the data saved in the flash memory 40 from the RAM 30 again in the RAM 30 as described above.

  When the power button of the operation unit 50 is turned on by the user (step Sd11), the CPU 10 executes the control program stored in the ROM 20 and activates the display device 1 (step Sd12). As a result, the activation state of the display device 1 is shifted from the “off state” to the “on state”. When the display device 1 is in the “on state”, the user operates the operation unit 50 to specify a desired program and instruct to execute it.

  The CPU 10 reads the access management table 71 stored in the flash memory 40 and stores it in the volatile memory of the memory access monitoring device 70 (step Sd13). This is called restoration of the access management table 71. Then, the CPU 10 calculates a hash value from the restored access management table 71 (step Sd14) and compares it with the hash value stored in the flash memory 40 (step Sd15). If the hash values are not equal (step Sd15; NO), the CPU 10 performs a warning process to alert the user (step Sd16). In such a case, there is a possibility that some failure has occurred between step Sc13 and step Sc14 in the data saving process described in FIG. 6, and the access management table 71 may not have been saved correctly. .

  On the other hand, if the compared hash values are equal (step Sd15; YES), the CPU 10 sets all the restored flags of the restored access management table 71 to “0” (step Sd17). FIG. 10 is a diagram illustrating an example of the restored access management table 71. As shown in the figure, the access management table 71 stores a saved flag, a restored flag, a memory address, and an access frequency for each page storing “data B3”, “data B4”, and “data B5”. Yes. In this data restoration process, data other than the restored flag, memory address, and page ID are not used. Hereinafter, the description will be continued on the assumption that the access management table 71 shown in FIG.

  Returning to the description of FIG. When the user instructs processing via the operation unit 50, the CPU 10 starts a task of the instructed processing (step Sd18). When the task is started, the memory access monitoring device 70 determines whether or not a memory access of the CPU 10 has occurred (step Sd19). While the memory access of the CPU 10 has not occurred (step Sd19; NO), the memory access monitoring device 70 continues this determination (step Sd19).

  On the other hand, when the memory access of the CPU 10 occurs, the memory access monitoring device 70 determines whether or not the restored flag corresponding to the accessed page is “0” in the access management table (step Sd20). Here, when the restored flag is not “0”, that is, “1” (step Sd20; NO), the page in which the access has occurred is already restored. Monitoring of the occurrence of memory access by the CPU 10 is continued (step Sd19).

  On the other hand, if the restored flag is “0” (step Sd20; YES), the memory access monitoring device 70 generates a page fault signal (step Sd21). In response to this signal, the CPU 10 refers to the access management table 71, identifies the memory address of the page where the access has occurred, and restores the page from the flash memory 40 to the RAM 30 (step Sd22). Then, the memory access monitoring device 70 rewrites the corresponding restored flag in the access management table 71 to “1” (step Sd23), and is stored in the restoration queue, which will be described later, around the page where the access has occurred. The page ID of the page is added (step Sd24).

  For example, it is assumed that a memory access has occurred for the page B4 shown in FIG. 10 when the CPU 10 executes a task. Then, the CPU 10 determines whether or not the restored flag corresponding to the page B4 is “0” (step Sd20). Since the restored flag corresponding to page B4 is “0” (step Sd20; YES), the memory access monitoring device 70 generates a page fault signal (step Sd21). Then, the CPU 10 reads the page in which the page B4 is stored from the flash memory 40 and restores the page to the memory address “2A80” of the RAM 30 corresponding to the page B4 (step Sd22).

Then, the memory access monitoring device 70 rewrites the restored flag corresponding to the page B4 to “1” (step Sd23), and is the page stored in the memory addresses before and after the memory address of the page B4. The page IDs of “page B3” and “page B5” are added to the restoration queue stored at a predetermined position on the RAM 30 (step Sd24). FIG. 11 is a diagram showing the restoration queue created in this way. The restoration queue has a higher restoration priority in the left side of the figure. A page with a high priority is restored before a page with a low priority. Therefore, in the restoration queue shown in FIG. 11, “page B3” is restored before “page B5”.
The only page required on the RAM 30 at the moment when the page fault signal is generated is “page B4”. However, since “page B4” is requested, “page B3” and “page B5” are also requested thereafter. There is a high possibility. This is because the position of data used by the user tends to concentrate on a specific location. In this way, these pages can be restored in advance without generating a page fault signal for requesting “page B3” or “page B5”. A return can be made. Note that which of “page B3” and “page B5” should be preferentially restored can be arbitrarily determined, but may be determined based on the access frequency of the access management table 71, for example. . In this case, as shown in FIG. 10, the access frequency of “page B3” is “12”, and the access frequency of “page B5” is “3”, so that “page B3” is “page B5”. More frequently accessed. The CPU 10 may determine this and create a restoration queue so that the priority of “page B3” is higher than that of “page B5”. This is because a page that has been frequently accessed before evacuation is likely to be frequently accessed even after restoration, and should be restored preferentially.

Here, FIG. 12 is a flowchart showing a processing procedure when the CPU 10 executes the data restoration processing. With reference to this FIG. 12, the data restoration process which CPU10 interrupts and performs a general process with a predetermined period is demonstrated.
The CPU 10 executes data restoration processing based on the restoration queue as shown in FIG. 11 at a predetermined cycle during the idle period. Specifically, the CPU 10 restores the data indicated by the top data ID of the restoration queue (step Se11), and deletes the data ID from the restoration queue (step Se12). In this case, since the top is “page B3”, the page in which “page B3” is stored in the memory address “2A00” of the RAM 30 is restored from the flash memory 40. Next, the CPU 10 sets the restored flag corresponding to “page B3” in the access management table to “1” (step Se13). Then, the CPU 10 determines whether or not the restoration queue created in the predetermined area of the RAM 30 is empty (step Se14). If the restoration queue is not empty (step Se14; NO), the CPU 10 determines whether or not interrupt processing exists (step Se15). If no interrupt process exists (step Se15; NO), the data restoration process is repeated (step Se11). On the other hand, when the restoration queue is empty (step Se14; YES) and when there is an interrupt process (step Se15; YES), the CPU 10 ends this data restoration process.

As described above, the display device 1 according to the embodiment has already performed a part of the evacuation process before shifting to the power non-supply state, so the load caused by the evacuation process when shifting to the power non-supply state is reduced. It is possible to reduce the time required for shifting to the non-power supply state.
Further, since the priority of saving can be determined from the access frequency to the page (the number of times partial data is used), more efficient saving processing can be performed. Then, it is possible to determine which of the tasks other than the save process and the save process should be prioritized from the total access frequency.
In addition, when shifting to the power supply state, the data that needs to be restored next is inferred based on the restored data, and this is preferentially restored, so that the data restoration process can be efficiently distributed. Can do.

[C: Modification]
The above is the description of the embodiment, but the contents of this embodiment can be modified as follows. Further, the following modifications may be combined as appropriate.
(Modification 1)
In the embodiment described above, the CPU 10 and the memory access monitoring device 70 are separate processors, and the memory access monitoring is realized by hardware separate from the CPU 10. This memory access monitoring may be performed by the CPU 10. That is, the above-described memory access monitoring procedure may be described in a program read into the CPU 10 and executed by the CPU 10.

(Modification 2)
In the above-described embodiment, the processing data stored in the RAM 30 is divided and saved in units called pages. Thus, the unit of processing data exchanged between the RAM 30 and the flash memory 40 is not limited to what is called a page, and may be a data unit handled by one task of the CPU 10 or smaller. It may be a unit, for example, a process unit or a function unit of a processing program for realizing processing. In short, any partial data may be used as long as the processing data is divided into a plurality of pieces.

(Modification 3)
In the embodiment described above, the saving process is not performed unless the total access frequency stored in the access management table 71 is equal to or greater than the threshold value Lim1, but such a threshold value may not be provided. That is, the CPU 10 may start the save process every time the task is completed.

(Modification 4)
In the above-described embodiment, the hash value is calculated and it is confirmed whether or not the access management table 71 before saving matches the access management table 71 after restoration. For this confirmation, the hash value is not calculated. The above method (parity bit, checksum, etc.) may be used. Further, this confirmation need not be performed.

(Modification 5)
In the above-described embodiment, when the page that generated this is restored in accordance with the page fault signal, one page stored in the memory address before and after the page is added to the restoration queue as a related page. did. However, the number of pages added to the restoration queue as related pages is not limited to this. For example, two, three, etc. may be used. Further, the number of related pages may be determined in accordance with the task executed by the CPU 10 when the page fault signal is generated. In this case, the number of pages to be added to the restoration queue as related pages for each task is determined in advance, and a table describing this number may be read from the flash memory 40 to determine the number.

FIG. 13 is a diagram showing an example of a table describing the number of related pages for each task in this modification. As shown in the figure, the OS read from the ROM 20 includes a table in which the number of related pages (that is, the data size of related data) is previously determined for each task, and when this OS is read into the RAM 30, This table is stored on the RAM 30. Here, “front” means the direction in which the memory address of the page is smaller, and “rear” means the direction in which the memory address of the page is larger. Therefore, for example, in the case of task A, one page with a smaller memory address than that page and four pages with a larger direction are related pages. When the page fault signal is generated, the CPU 10 refers to the number of related pages corresponding to the task requested when the page fault signal is generated in this table, and should be added to the above restoration queue based on the number of related pages. What is necessary is just to specify a related page.
FIG. 13 shows an example in which the number of related pages is defined for each task. However, the number of related pages may be defined for each program that can be said to be a set of procedures of these tasks. In this case, when the page fault signal is generated, the CPU 10 refers to the number of related pages corresponding to the program being executed when the page fault signal is generated in this table, and based on the number of related pages, the restoration queue described above. Identify related pages that should be added to.
Regardless of the task or the program, the data size of the related data only needs to be determined for each process executed by the CPU.

  In the embodiment, since the page is a unit, the related page is the page before and after the page. In short, since data related to the restored data is likely to be accessed after the restored data, the CPU 10 sets the restoration order of the related data that seems to be related to the restored data according to some rule. You can memorize it.

(Modification 6)
In the above-described embodiment, the RAM 30 is exemplified as the first storage unit that maintains the state where the data is stored by receiving the power supply, and the second storage unit maintains the state where the data is stored without receiving the power supply. Although the flash memory 40 has been illustrated, specific examples of these storage means are not limited to the illustration of the embodiment.

(Modification 7)
In the above-described embodiment, the display device 1 has only one type of nonvolatile memory, the flash memory 40, but the display device 1 may include two or more types of nonvolatile memory. Further, in these two or more types of nonvolatile memories, when there is a difference in the reading / writing speed of the stored contents, the save destination of the processing data on the RAM 30 may be different. For example, out of the pages stored in the access management table 71, pages with low access frequency are stored in a nonvolatile memory with low read / write speed, and pages with high access frequency are stored in non-volatile memory with high read / write speed. Also good. In this way, frequently accessed pages are stored in the non-volatile memory having a faster read / write speed, so that save processing and restoration processing can be performed quickly. In order to determine whether the access frequency is high or low, a threshold value may be set in advance, or compared with the average value of the access frequency (arithmetic average, geometric average, mode value), etc. Also good.

(Modification 8)
In the above embodiment, all the fields of the access management table 71 are saved, but only the memory address and the page ID may be saved. This is because the saved flag is used only at the time of saving, the restored flag is initialized at the time of restoration, and the access frequency and the total access frequency are not used at the time of restoration.

(Modification 9)
In the embodiment, the save process is started when the CPU 10 is idle, but the start timing is not limited to the timing when the CPU 10 is idle. In short, the save process may be performed during a period when the CPU 10 is idle, and the timing of the save start may be delayed from the timing when the CPU 10 is idle.

(Modification 10)
The program executed by the CPU 10 of the display device 1 described above is a recording such as a magnetic tape, a magnetic disk, a flexible disk, an optical recording medium, a magneto-optical recording medium, a CD (Compact Disk), a DVD (Digital Versatile Disk), and a RAM. It can be provided as recorded on the medium. Moreover, it is also possible to make the display device 1 download via a network such as the Internet. That is, the present invention can be realized as a program.

It is a figure which shows the structure of the display apparatus which concerns on this embodiment. It is the figure which showed an example of the access management table. It is a flowchart which shows the flow of an access frequency total process. It is a flowchart which shows the flow of a data saving process. It is a figure which shows an example of an evacuation queue. It is a flowchart for demonstrating the flow of the process which transfers to a power supply non-supply state from a power supply state. It is a time chart when the instruction | indication of transfer is received from the user via the operation part. It is a time chart which shows another example of transfer to a power supply non-supply state. It is a flowchart which shows the flow of the data restoration process which restores the data evacuated to the flash memory when the display device is restored. It is a figure which shows an example of the restored access management table. It is a figure which shows a decompression | restoration queue. It is a flowchart which shows the flow of the data restoration process which CPU interrupts and performs a general process with a predetermined period. It is a figure which shows an example of the table which described the related page number for every task in a modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 10 ... CPU, 20 ... ROM, 30 ... RAM, 40 ... Flash memory, 50 ... Operation part, 60 ... Display part, 70 ... Memory access monitoring apparatus, 71 ... Access management table, 80 ... Power supply part, 90 ... Bus

Claims (13)

First storage means for receiving a power supply and maintaining a state of storing data;
Second storage means for maintaining a state of storing data without receiving power supply;
State transition means for shifting to either a power supply state for supplying power to the first storage means or a power non-supply state for not supplying power to the first storage means;
Processing execution means for executing processing using data stored in the first storage means in the power supply state;
Until there is an instruction to shift from the power supply state to the power non-supply state, the data stored in the first storage unit is read out in portions at different times and stored in the second storage unit. Evacuation means for performing evacuation processing,
The state transition unit shifts the data stored in the first storage unit from the power supply state to the power non-supply state after the save process by the save unit is performed. Data management device. The data management apparatus according to claim 1, wherein the save unit starts the save process every time processing that is a unit of execution by the process execution unit is completed. The data management apparatus according to claim 2, wherein the save unit performs the save process during a period when the process is not executed by the process execution unit. The process execution means temporarily suspends execution of the process from the start of the process as a unit of execution until completion.
The data management apparatus according to claim 1, wherein the save unit performs the save process during a period in which the process execution unit temporarily suspends execution of the process. The process execution means is a CPU that executes a process according to a procedure described in a program,
5. The process as a unit of execution by the process execution unit is a task as a unit of a process executed by the CPU according to a procedure described in the program. 6. Data management device. When the data is divided into a plurality of partial data, a number of times storage means for storing the number of times the processing execution means uses the partial data stored in the first storage means for each partial data Prepared,
2. The data according to claim 1, wherein the saving unit performs the saving process on partial data stored in the frequency storage unit before the partial data having a high number of times. Management device. The data management apparatus according to claim 6, wherein the save unit performs the save process when the total number of times stored by the number storage unit is equal to or greater than a first threshold value. The saving unit performs the saving process in a period in which the process is not executed by the process execution unit when the total number of times stored by the number storage unit is equal to or greater than a first threshold, When the total number of times stored by the number storage unit is equal to or greater than a second threshold value that is greater than the first threshold value, the save processing is performed even during a period in which the process is being executed by the process execution unit. The data management device according to claim 6, wherein: If the save means cannot save all the data stored in the first storage means until there is an instruction to shift from the power supply state to the power non-supply state, The data management apparatus according to claim 1, wherein after being instructed, unsaved data is read from the first storage unit and stored in the second storage unit. In the power supply state, when the data used for the process executed by the process execution unit is not stored in the first storage unit, the data stored in the second storage unit is read, and the second storage unit Performing a restoration process to be stored in one storage unit, and storing a restoration order of related data related to the data in the second storage unit;
Based on the restoration order stored by the first restoration unit, the related data stored in the second storage unit is read out during the period when the process is not performed by the process execution unit, and the first storage The data management apparatus according to claim 1, further comprising: a second restoration unit that is stored in the unit. The data management apparatus according to claim 10, wherein the data size of the related data is determined for each process executed by the process execution unit. A data management device according to any one of claims 1 to 11,
An information processing apparatus comprising: output means for outputting a result processed by the process execution means. A computer comprising first storage means for maintaining a state in which data is stored upon receiving power supply, and second storage means for maintaining a state in which data is stored without receiving power supply,
State transition means for shifting to either a power supply state for supplying power to the first storage means or a power non-supply state for not supplying power to the first storage means;
Processing execution means for executing processing using data stored in the first storage means in the power supply state;
In the power supply state, the data stored in the first storage unit is functioned as a saving unit that performs a saving process of reading data in portions at different times and storing them in the second storage unit,
Furthermore, the state transition unit is a program for shifting from the power supply state to the power non-supply state after the save process by the save unit is performed on the data stored in the first storage unit.

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