JP2004214410A - Multi-layer wiring substrate and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a multi-layer wiring substrate capable of maintaining the high quality of a high density multi-layer wiring substrate whose via hole periphery can be used as a land, reducing labor in the manufacturing process, and especially reducing the labor of the grinding treatment of electroplating raised from the surface of a laminate. <P>SOLUTION: This method for manufacturing a multi-layer wiring substrate is provided to form an anti-plating resist on the surfaces of a surface layer and a back layer from which the periphery of the openings of blind via holes 6a and 6b and the periphery of the opening of a through-hole 7 are excluded for masking, to fill the blind via holes 6a and 6b with electroplating, to deposit the electroplating on the internal peripheral face of the through-hall 7, to peel the anti-plating resist, to remove the electroplating raised from the surface of the surface layer and the back layer by mechanical grinding, and to flatten surfaces of the surface layer and the back layer. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to the manufacture of BVH, IVH and build-up type multilayer wiring boards which are formed on a base material with a plurality of wiring layers and insulating layers interposed therebetween.
[0002]
[Prior art]
As represented by portable electronic devices, electronic devices are required to be lighter, thinner and smaller, and a printed wiring board with a high mounting density is being demanded. ing. This multilayer wiring board is provided with via holes such as blind via holes and through holes for electrical conduction between upper and lower wiring layers. However, ordinary via holes cannot be used as lands for connecting and fixing components, and thus dead spaces are required. It was.
[0003]
For this reason, there is an increasing need to improve the packaging density by effectively utilizing via holes to mount components by the demand for further reduction in size and size.
[0004]
Therefore, in order to use the via hole and the periphery of the via hole as lands for mounting components, reduce the hole diameter of the via hole or fill the via hole after electroplating the inner wall with resin and smooth the surface, For example, lands for connecting and fixing parts are formed by plating a lid.
[0005]
In addition, the via holes are filled with electroplating.
[0006]
[Patent Document 1] JP-A-10-65340
Problems to be solved by the present invention
However, in the case where the inner wall of the via hole is subjected to electroplating and then filled with a resin and further subjected to lid plating, the thickness of the conductor located on the surface is increased, and there is a difficulty in forming a fine circuit.
[0008]
Explaining while showing specific numerical values, the thickness of the material copper foil on the surface is 12 μm, and the thickness of plating deposited on the substrate surface by performing through-hole plating is about 20 μm, so that the total thickness is about 32 μm. However, when the cover plating is applied, the thickness of the cover plating is added to this, and since the thickness of the cover plating is about 10 μm, the total thickness is about 42 μm.
[0009]
Here, in the pattern formation, a protective coating is formed on the surface because a corrosive solution for dissolving copper is sprayed and dissolved from the surface, but when the corrosive solution is sprayed, the side surfaces are also etched, and the pattern becomes thinner. I will.
[0010]
For this reason, when the total thickness of the entire surface layer on which the pattern is formed, that is, the total thickness of the plating copper deposited on the substrate surface by the through-hole plating and the thickness of the lid plating is increased, that is, from the side, There has been a problem that the precision of fine pattern formation deteriorates because the amount of dissolution increases.
[0011]
On the other hand, even when the via holes are filled with electroplating and the surface is flattened, it is difficult to maintain the quality of a large-sized product having a large number of holes such as a printed wiring board.
[0012]
When plating is performed on a substrate, the plating starts to adhere from the peripheral portion of the substrate and the plating proceeds toward the center. The thickness of the plating near the center becomes thinner.
[0013]
Here, a substrate of 340 mm × 410 mm or 510 mm × 410 mm may be used as a general work size. However, if the hole near the center of the substrate is to be filled with plating, the thickness of the plating at the peripheral portion of the substrate is large. In extreme cases, it may be in a raised state. It is necessary to remove the swelling by polishing using a buff, a belt, or the like, but such polishing cannot selectively polish only the swelled portion, and the buff, the belt, or the like hits the entire surface of the substrate and is polished. Therefore, the thin portion becomes even thinner, and when the thick raised portion has an appropriate film thickness, the thin portion does not have a necessary conductor thickness, which may cause a problem.
[0014]
In order to planarize the entire surface of the substrate on which the plating process has been performed by polishing, considerable labor is required, and many man-hours are required. Further, there is a problem that it is difficult to maintain quality as much as the processing area and labor increase.
[0015]
[Means for Solving the Problems]
Therefore, the present invention performs electroplating on a via hole in order to reduce the flattening process of the swelling caused by the plating process and to avoid the deterioration of the pattern quality due to the dissolution of the plating from the side surface of the plating layer when forming the fine pattern. Previously, the electroplating treatment was performed only on the minimum necessary portion by forming a plating-resistant resist in a portion where the adhesion of the electroplating was unnecessary.
[0016]
That is, the method for manufacturing a multilayer wiring board according to the present invention is directed to a multilayer wiring in which blind via holes and through through holes are formed in a multilayer substrate formed by alternately laminating wiring layers and insulating layers and laminating metal foils as wiring layers. A method for manufacturing a substrate, comprising: (1) a step of alternately laminating wiring layers and insulating layers, and laminating metal foils as front and back layers to form a multilayer substrate; (2) a multilayer substrate (3) forming an electroless plating layer on the surface of the metal foil forming the surface layer and the back surface layer, the blind via hole and the through hole, and (4) blind. Forming a plating-resistant resist on the surface of the surface layer and the back surface layer except for the peripheral portion of the via hole opening and the peripheral portion of the through-hole opening; and (5) blind plating by electroplating. Filling the holes and depositing electroplating on the inner peripheral surface of the through-hole; and (6) stripping the plating-resistant resist and removing the electroplating raised from the surface of the surface layer and the back surface layer by mechanical grinding. And (7) a step of forming an outer layer pattern on the surface layer and the back surface layer having the flattened surface, and manufacturing a multilayer wiring board. Is the way.
[0017]
The step (1) of alternately laminating the wiring layer and the insulating layer, laminating a metal foil as the wiring layer to form a multilayer base material includes using the metal foil constituting the core material as the wiring layer and forming the insulating layer as the insulating layer. Using a prepreg obtained by impregnating and drying an insulating resin in a glass cloth, these are sequentially laminated, and an insulating layer and a wiring layer can be built up in the order of heating and pressure molding by a laminating press. Note that a copper foil can be used as the metal foil as the wiring layer.
[0018]
Further, the insulating resin forming the prepreg can be appropriately selected from any of an epoxy resin, a non-halogen epoxy resin, a polyimide resin, and a fluororesin.
[0019]
The step (2) of forming a blind via hole and a through-hole in a multilayer substrate can be performed by a conventional method. For example, it can be performed by drilling, laser processing, or the like.
[0020]
The material used for the electroless plating layer in the step (3) and the electroplating in the step (5) can be appropriately selected from any of copper, nickel, gold, silver, palladium, tin, and rhodium.
[0021]
As a material for the plating resist in the step (4), a dry film or a printing ink can be selected. The plating-resistant resist is formed at a place where electroplating is not required at the time of completion, and plays a role of masking.
[0022]
By forming the plating-resistant resist in this manner, the electroplating process is performed only on the minute portion around the via hole, so that the variation in the amount of electricity during plating can be reduced, and the quality can be improved. .
[0023]
In addition, since the grinding process needs to be performed only on the minute portion, the labor can be reduced and the quality can be improved.
[0024]
In the step (5), the blind via hole is filled by electroplating, and the electroplating is deposited on the inner peripheral surface of the through-hole. In this step, a plating resist is formed in the step (4). Electroplating swells on the surface portion of the unexposed multilayer base material, that is, on the surfaces of the surface layer and the back surface layer except for the periphery of the blind via hole opening and the periphery of the through-hole opening.
[0025]
The plating resist in the step of removing the plating resist in the step (6), removing the electroplating raised from the surface of the surface layer and the back layer by mechanical grinding, and flattening the surface of the surface layer and the back layer. Can be removed by spraying a sodium hydroxide solution onto the plating resist. Further, as described above, the mechanical grinding of electroplating raised from the surface of the surface layer and the back surface layer in the step (5) can employ a commonly used means for flattening the substrate surface. It can be performed by belt polishing or buff polishing.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of the present invention will be described along each step with reference to the drawings.
[0027]
1. (Laminated board manufacturing process)
The multi-layer substrate 1 is formed by attaching an inner layer metal foil 2 having an inner layer pattern formed on one surface side, and thereafter attaching outer layer metal foils 5 and 5 on which an outer layer pattern is formed to another surface side. Of the core materials 3 and 3 are arranged to face each other with the prepreg 4 interposed therebetween. At this time, the inner metal foil 2 on which the inner layer pattern is formed is arranged such that the side to which the inner metal foil 2 is adhered is located inside.
[0028]
In such a state, the multilayer substrate 1 is formed by pressing with a lamination press (not shown) (FIG. 1).
[0029]
Here, copper foil was used for the inner metal foils 2 and 2 and the outer metal foils 5 and 5. The prepreg 4 serving as an insulating layer was obtained by impregnating and coating an epoxy resin as an insulating material on a glass cloth 4a.
[0030]
The laminated plate 1 configured as described above is cut into a work size of 340 × 510 mm.
[0031]
2. [Drilling process] (Drilling of through through holes and blind via holes)
Next, blind via holes 6a and 6b and through-holes 7 are formed at predetermined positions of the multilayer substrate 1 using an NC drilling machine (not shown) (FIG. 2).
[0032]
Here, the blind via hole 6a is formed from the outer metal foil 5 of the upper core material 3 to the inner metal foil 2 in FIG. On the other hand, the blind via hole 6b is formed from the outer metal foil 5 of the lower core material 3 to the inner metal foil 2 in FIG.
[0033]
The through-hole 7 is formed so as to penetrate from the upper surface to the lower surface of the multilayer substrate 1.
[0034]
3. [Chemical copper plating process]
Next, electroless plating for conduction between upper and lower wiring layers is performed on the surfaces of the outer metal foils (copper foils) 5, 5 forming the outer layer pattern, the inner peripheral surfaces of the blind via holes 6a, 6b, and the inner peripheral surfaces of the through-holes 7. The layer 8 is formed (FIG. 3).
[0035]
Here, chemical copper plating is adopted as the electroless plating. Although the electroless plating layer 8 in FIG. 3 is slightly thicker for the sake of explanation, the chemical copper plating actually used is for thinning, and the thickness is about 0.2 to 0.5 μm. is there.
[0036]
4. [Plating resist forming process]
Next, on the surfaces of the outer layer metal foils 5 forming the outer layer pattern, plating resistant resists 11 are applied to portions except for the blind via hole opening peripheral portions 9a and 9b and the through through hole opening peripheral portions 9c and 9c. (FIG. 4).
[0037]
That is, the portions other than the portions of the outer metal foils 5 and 5 where the electroplating is to be deposited in the next step (the peripheral portions 9a and 9b around the openings of the blind via holes and the peripheral portions 9c and 9c around the openings of the through-holes) are masked.
[0038]
The plating-resistant resist is formed by printing with a gauze plate using an ink applicable to the plating-resistant resist, but a portion where the ink is not printed is filled with a resin (emulsion), and a peripheral portion 9a of the blind via hole opening is formed. , 9b and the peripheral portions 9c, 9c around the through-hole opening.
[0039]
When the plating resists 11, 11 are formed on the surfaces of the outer metal foils 5, 5, the contact portions 10, 10 for energizing electroplating necessary for performing the electroplating process in the next step are secured. deep.
[0040]
5. [Electroplating process]
Next, an electroplating process is performed to obtain electrical continuity between the blind via holes 6a and 6b and the through-hole 7 (FIG. 5). That is, the blind via holes 6 a and 6 b are filled with the electroplating 12, and the electroplating 12 is deposited on the inner peripheral surface of the through-hole 7.
[0041]
At this time, the electroplating is performed by using a copper sulfate bath as a bath composition, arranging electrodes at the contact portions 10 and 10, and passing a current having a current density of 1 A / dm ² .
[0042]
When the electroplating process is performed, as shown in FIG. 5, the peripheral portions 9a and 9b around the blind via hole openings and the peripheral portions 9c and 9c surrounded by the plating resists 11 and 11 are also electroplated 12a and 12a. It is filled.
[0043]
6. [Plating resist stripping process]
Next, the plating resists 11, 11 are peeled off (FIG. 6).
[0044]
Here, the plating resists 11 are removed by spraying a sodium hydroxide solution onto the plating resists 11 inside an apparatus called an etching line.
[0045]
7. [Electroplating flattening process]
Next, the electroplating 12a, 12a (FIG. 6) raised on the surface of the laminated material 1 is removed by mechanical grinding, and the surface of the outer metal foils 5, 5 of the laminated material 1 is flattened (FIG. 7). The mechanical grinding was polished using a tool such as a belt sander and flattened.
[0046]
8. (Outer layer pattern forming step)
As a final step, a fine pattern is formed on the outer metal foils 5, 5 (FIG. 8). The formation of the fine pattern may be performed by an ordinary method.
[0047]
Through the above steps, the multilayer wiring board 13 is formed. The multilayer wiring board 13 formed as described above can be energized in the blind via holes 6a and 6b and the through through hole 7, and can be connected to the blind via hole opening peripheral portions 9a and 9b and the through through hole opening peripheral portions 9c and 9c. Since the lands A, B, and C are formed, components can be mounted on the lands A, B, and C.
[0048]
As an abnormality of the multilayer wiring board, it is conceivable that a conduction failure or the like due to the destruction of the through-hole plating is considered. However, the multilayer wiring board 13 was dipped for 20 seconds at a solder temperature of 260 ° C., but no such abnormality was found. Was.
[0049]
As described above, the preferred embodiments of the present invention have been described with reference to the accompanying drawings. However, the present invention is not limited to such embodiments, and various modifications may be made within the technical scope understood from the claims. It can be changed to a different form.
[0050]
For example, a dry film can be used as the plating resist in place of the ink. For example, a copper pyrophosphate bath may be used instead of a copper sulfate bath.
[0051]
【The invention's effect】
According to the method for manufacturing a multilayer wiring board of the present invention, a plating-resistant resist is formed on the surfaces of the surface layer and the back layer except for the peripheral portion of the blind via hole opening and the peripheral portion of the through-hole opening. Filling the via hole and depositing electroplating on the inner peripheral surface of the through-hole can deposit electroplating only at the place where a land is to be formed. Variations in the amount of electricity can be reduced, and quality improvement can be achieved.
[0052]
In addition, since it is only necessary to perform the grinding process on only the minute portion, there is an effect that the labor can be reduced and the quality can be improved.
[0053]
That is, without difficult management, a high density multilayer wiring board can be manufactured by filling a blind via hole by electroplating and flattening the surface by mechanical polishing.
[Brief description of the drawings]
FIG. 1 is an explanatory sectional view of a multilayer base material formed by a lamination press.
FIG. 2 is an explanatory cross-sectional view showing a state where a blind via hole and a through through hole are formed in the state shown in FIG. 1;
FIG. 3 is an explanatory cross-sectional view showing a state where chemical copper plating is applied from the state shown in FIG. 2;
FIG. 4 is an explanatory sectional view of a state where a plating resist is formed from the state shown in FIG. 3;
FIG. 5 is an explanatory cross-sectional view showing a state in which electroplating is applied from the state shown in FIG. 4 to fill a blind via hole and electroplating is deposited on an inner peripheral surface of a through-hole;
FIG. 6 is an explanatory cross-sectional view showing a state where a plating-resistant resist is removed from the state shown in FIG. 5;
FIG. 7 is an explanatory sectional view showing a state in which electroplating raised on the surface of the multilayer base material is removed by grinding from the state shown in FIG. 6;
FIG. 8 is an explanatory cross-sectional view of a multilayer wiring board completed by forming a fine pattern on an outer metal foil from the state shown in FIG. 7;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Multilayer base material 2 Inner layer metal foil 3 Core material 4 Prepreg 5 Outer layer metal foil 6a, 6b Blind via hole 7 Through-hole 8 Electroless plating layer 11 Plating resist 12 Electroplating 13 Multilayer wiring board

Claims (7)

A method for manufacturing a multilayer wiring board in which blind via holes and through-holes are formed in a multilayer base material formed by laminating wiring layers and insulating layers alternately and laminating a metal foil as a wiring layer,
A step of alternately laminating wiring layers and insulating layers, laminating a metal foil as a surface layer and a back layer to form a multilayer base material,
Forming blind via holes and through-holes in the multilayer substrate,
A step of forming an electroless plating layer on the surface of the metal foil forming the surface layer and the back layer, the surface of the blind via hole and the through-hole,
A step of forming a plating-resistant resist on the surface of the surface layer and the back layer excluding the peripheral portion of the blind via hole opening and the peripheral portion of the through-hole opening,
Filling the blind via hole with electroplating and depositing electroplating on the inner peripheral surface of the through-hole,
Removing the plating-resistant resist, removing the electroplating raised from the surface of the surface layer and the back surface layer by mechanical grinding, and flattening the surface of the surface layer and the back surface layer;
Forming an outer layer pattern on the surface layer and the back surface layer whose surfaces have been flattened. The multi-layer substrate is formed by sequentially laminating a prepreg obtained by impregnating and drying a glass cloth with an insulating resin and a core material to which a copper foil is adhered, heating and press-molding with a laminating press to build an insulating layer and a wiring layer. 2. The method for manufacturing a multilayer wiring board according to claim 1, wherein the process is performed. 3. The method according to claim 2, wherein the insulating resin is selected from an epoxy resin, a halogen-free epoxy resin, a polyimide resin, and a fluororesin. The method of manufacturing a multilayer wiring board according to any one of claims 1 to 3, wherein the step of forming the blind via hole and the through-hole in the multilayer base material is performed by drilling. The multilayer wiring board according to any one of claims 1 to 4, wherein a material of the electroless plating layer and the electroplating is selected from one of copper, nickel, gold, silver, palladium, tin, and rhodium. Manufacturing method. The method according to any one of claims 1 to 5, wherein the mechanical grinding of the electroplating raised from the surface of the front surface layer and the back surface layer is performed by belt polishing or buff polishing. A multilayer wiring board manufactured by the manufacturing method according to claim 1.

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