WO2011148491A1 - Process for production of semiconductor device - Google Patents
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- WO2011148491A1 WO2011148491A1 PCT/JP2010/059031 JP2010059031W WO2011148491A1 WO 2011148491 A1 WO2011148491 A1 WO 2011148491A1 JP 2010059031 W JP2010059031 W JP 2010059031W WO 2011148491 A1 WO2011148491 A1 WO 2011148491A1
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- wiring board
- semiconductor device
- side electrode
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- polishing
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/09181—Notches in edge pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0346—Deburring, rounding, bevelling or smoothing conductor edges
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
Abstract
In the production of a wiring board (2) having a semiconductor element mounted thereon, a side electrode (4) for the wiring board (2) can be produced through the steps of: forming a through-hole electrode on a material that can act as the wiring board (2); cutting the through-hole electrode so as to divide the through-hole electrode into two parts by a mechanical processing; and polishing the cut surface of the wiring board. In this manner, burrs on the side electrode (4), which are formed in the cutting step, can be removed.
Description
本発明は、半導体装置の製造方法に関するものである。
The present invention relates to a method for manufacturing a semiconductor device.
従来、はんだ接合部の観察が容易で、マザーボードへの実装面積を小さくできる半導体装置として、半導体素子などの電子部品を実装した配線板の側面にマザーボードとのはんだ接合用の電極を形成したものがよく用いられてきた。
Conventionally, as a semiconductor device in which the solder joint portion can be easily observed and the mounting area on the mother board can be reduced, an electrode for solder joining with the mother board is formed on the side surface of the wiring board on which electronic components such as semiconductor elements are mounted. It has been used frequently.
側面に電極を有する半導体装置は、配線板の側面で直にはんだ接合しているために、マザーボードとの熱膨張差の影響を受けやすい。そのため、配線板はマザーボードと同じ材料で構成される。通常はエポキシ樹脂とガラス繊維で構成されるガラスエポキシプリント配線板が用いられる。
半導体 Semiconductor devices having electrodes on the side surfaces are easily soldered on the side surfaces of the wiring board, and thus are susceptible to thermal expansion differences from the motherboard. Therefore, the wiring board is made of the same material as the mother board. Usually, a glass epoxy printed wiring board composed of epoxy resin and glass fiber is used.
配線板の側面にある電極を製造する方法としては、両面銅張り積層板にドリルなどで機械的に穴あけを行い、穴に銅めっきを行い、スルーホールを形成する。次に、スルーホールが半分になるように、位置決めして、スルーホールを半円になるように分割する。
As a method of manufacturing the electrode on the side surface of the wiring board, a double-sided copper-clad laminate is mechanically drilled with a drill or the like, and copper is plated in the hole to form a through hole. Next, positioning is performed so that the through hole is halved, and the through hole is divided into a semicircle.
分割する方法として、打ち抜き加工、ルーター加工、ダイシング加工、の機械加工があるが、小さい穴径を精度よく加工する方法として、ダイシング加工を用いる。ダイシング加工は、ダイヤモンド粒子などの砥粒を付着したブレードを回転させて加工を行う方法であるため、ダイヤモンド粒子間に削りカスがつまった状態の「目つまり」がおこると、効率よく削れなくなり、金属バリが発生する。
There are mechanical processing such as punching, router processing, and dicing as a method for dividing, but dicing is used as a method for accurately processing a small hole diameter. Dicing is a method in which a blade with diamond grains or other abrasive particles attached is rotated to perform machining. Metal burrs are generated.
金属バリは、マザーボードとのはんだ付け時にはんだの中に突起として残るために、温度サイクル試験でのクラック発生の起点となり、はんだ接合信頼性を損なうことが懸念される。また、脱落したバリはゴミとなり、電極間のショート不良をまねく恐れがある。
Since metal burrs remain as protrusions in the solder when soldering to the motherboard, there is a concern that cracking will occur in the temperature cycle test and solder joint reliability will be impaired. Also, the burrs that fall off become dust and may cause a short circuit between the electrodes.
そこで、金属バリを発生させない製造方法が既にいくつか提案されている。例えば、穴内に銅めっきを形成し、スルーホールを形成した後、側面電極の端面にあたる位置の銅めっき領域のみをレジストパターニングによって露出された後、銅を除去し、切断時に銅を加工しないようにする手法が提案されている（例えば、特許文献１参照。）。
Therefore, several manufacturing methods that do not generate metal burrs have already been proposed. For example, after forming copper plating in the hole and forming the through hole, only the copper plating region at the position corresponding to the end face of the side electrode is exposed by resist patterning, and then the copper is removed so that the copper is not processed during cutting. A technique has been proposed (see, for example, Patent Document 1).
また、穴内に銅めっきを形成し、スルーホールを形成した後、側面電極の端面にあたる位置の銅めっきを、スルーホール軸方向に向かって除去し、ルーターによる切断加工の際に、ルーターが銅めっきを加工しないようにする手法が提案されている（例えば、特許文献２参照。）。
Also, after forming copper plating in the hole and forming the through hole, the copper plating at the position corresponding to the end face of the side electrode is removed in the direction of the through hole axis, and when the router cuts the copper plating There has been proposed a technique for preventing the processing of the material (for example, see Patent Document 2).
さらに、貫通穴を形成した後に、貫通穴が半円状の溝になるように、スリットを形成し、スリットに凸治具を挿入して、半円部のみに銅めっきを析出することで、切断時の銅の加工を避ける方法も提案されている（例えば、特許文献３参照。）。
Furthermore, after forming the through hole, forming a slit so that the through hole becomes a semicircular groove, inserting a convex jig into the slit, and depositing copper plating only on the semicircular part, A method for avoiding the processing of copper at the time of cutting has also been proposed (see, for example, Patent Document 3).
従来の半導体装置の製造方法として、特許文献１においては、スルーホール電極を形成した後、側面電極の端面にあたる位置の銅めっきをレジストパターニングで露出した後、銅めっき除去の工程を実施することが提案されている。
As a conventional method of manufacturing a semiconductor device, in Patent Document 1, after forming a through-hole electrode, a copper plating at a position corresponding to an end surface of a side electrode is exposed by resist patterning, and then a copper plating removing process is performed. Proposed.
この方法ではスルーホール径が小さい場合に、より精度の高いレジストパターニングが要求される上、銅めっき除去が困難になってくるため、コストアップになるという問題があった。
In this method, when the through-hole diameter is small, more accurate resist patterning is required, and copper plating removal becomes difficult, resulting in an increase in cost.
また、同じく切断前に、スルーホール電極の銅めっきを除去する方法として、特許文献２においては、スルーホール電極の側面電極の端面にあたる位置の銅めっきを機械的にドリルで除去する方法が提案されている。この方法においても、スルーホール電極径が小さい場合に、精度よく銅めっきを除去することが困難になるという問題があった。
Similarly, as a method of removing the copper plating of the through-hole electrode before cutting, Patent Document 2 proposes a method of mechanically removing the copper plating at the position corresponding to the end surface of the side electrode of the through-hole electrode with a drill. ing. This method also has a problem that it is difficult to accurately remove copper plating when the through-hole electrode diameter is small.
上記の２つの方法はともに、スルーホール電極を切断する前に、側面電極の端面にあたる位置の銅めっきをあらかじめ除去し、切断時には銅めっきを切断することを避けることによって、金属バリの発生を防止するという考えに基づくものである。
Both of the above two methods prevent the occurrence of metal burrs by removing the copper plating at the position corresponding to the end face of the side electrode in advance before cutting the through-hole electrode and avoiding cutting the copper plating at the time of cutting. It is based on the idea of doing.
配線板の切断時に銅めっきを切断しないようにするためには、銅めっきの除去幅は切断の幅よりも大きくする必要があるため、側面電極形成後は、側面電極の端面にまで、銅めっきはない状態になる。そのため、側面電極の幅は小さくなることにより、はんだ接合面積が小さくなるため、はんだ接合強度が低下することが懸念される。
In order not to cut the copper plating at the time of cutting the wiring board, it is necessary to make the removal width of the copper plating larger than the cutting width. Therefore, after the side electrode is formed, the copper plating is applied to the end face of the side electrode. There is no state. For this reason, since the solder joint area is reduced by reducing the width of the side electrode, there is a concern that the solder joint strength is reduced.
従来の半導体装置の製造方法として、特許文献３においては、貫通穴が半円になるようにスリットを形成し、スリットに凸形状の治具を挿入した状態で銅めっきをすることによって、側面電極の半円形状の部分のみに銅めっきを形成し、切断部に銅めっきが付かないようにする方法を提案している。
As a conventional method for manufacturing a semiconductor device, in Patent Document 3, a slit is formed so that a through hole is a semicircle, and copper plating is performed in a state where a convex jig is inserted into the slit. A method has been proposed in which copper plating is formed only on the semicircular portion of the steel plate, and the copper plating is not applied to the cut portion.
切断部に銅めっきが付かないようにするには、スリットと治具の隙間をかなり小さくする必要があるので、治具の加工費が高くなるという問題があった。また、配線板ごとに治具を作製する必要があるため、さらにコストが高くなるという問題があった。
In order to prevent the copper plating from being attached to the cut portion, it is necessary to make the gap between the slit and the jig considerably small, resulting in a problem that the processing cost of the jig becomes high. Moreover, since it is necessary to produce a jig for each wiring board, there is a problem that the cost is further increased.
本発明は、上記に鑑みてなされたものであって、低コストで配線板の側面電極の接合信頼性が向上した半導体装置の製造方法を得ることを目的とする。
The present invention has been made in view of the above, and an object of the present invention is to obtain a method for manufacturing a semiconductor device with improved bonding reliability of side electrodes of a wiring board at low cost.
上述した課題を解決し、目的を達成するために、本発明は、半導体素子を搭載する配線板の製造において、前記配線板となる材料にスルーホール電極を形成する工程と、機械加工によってスルーホール電極を半分に切断する工程と、前記切断面を研磨する工程を具備することにより、前記切断する工程で形成されたバリを除去することで、前記配線板の側面電極を形成することを特徴とする。
In order to solve the above-described problems and achieve the object, the present invention provides a process for forming a through-hole electrode in a material to be a wiring board in manufacturing a wiring board on which a semiconductor element is mounted, and a through-hole by machining. A side electrode of the wiring board is formed by removing a burr formed in the cutting step by providing a step of cutting the electrode in half and a step of polishing the cut surface. To do.
通常の研磨は、加工物（ここでは配線板２）よりも大きく平坦な研磨板に砥粒を含有した水溶液などの研磨液を供給しながら、研磨板と加工物を擦り合わせることで、表面を加工する方法を用いる。
In normal polishing, a polishing plate such as an aqueous solution containing abrasive grains is supplied to a polishing plate that is larger and flatter than the workpiece (here, the wiring board 2), and the surface of the polishing plate is rubbed with the workpiece. Use the processing method.
これにより、加工物と研磨板の間に入った砥粒（固定されていないから遊離砥粒とよぶ）は自由に転がりながら、加工物の表面を削りとる。
This allows the abrasive grains that have entered between the workpiece and the polishing plate (referred to as free abrasive grains because they are not fixed) to roll freely while scraping the surface of the workpiece.
図７は通常の研磨方法を用いて、配線板２の端面８を研磨している状態を示す。配線板２の端面８に通常の研磨方法を適用すると、研磨板２３が矢印２５方向に動くに従い、遊離した砥粒２０が側面電極４の銅よりも軟らかい樹脂で構成される部分を削りとるため、端面８に凹部８１が生じ、平坦に研磨することができない問題がある。
FIG. 7 shows a state where the end face 8 of the wiring board 2 is being polished using a normal polishing method. When a normal polishing method is applied to the end face 8 of the wiring board 2, as the polishing plate 23 moves in the direction of the arrow 25, the portion of the side electrode 4 made of a resin softer than copper is scraped off. There is a problem in that a recess 81 is formed on the end face 8 and the surface cannot be polished flat.
そこで、配線板２よりも面積が大きく、平坦な表面に微細な砥粒２１を樹脂などのバインダー２２で固定した研磨板２３に配線板２を押し当てて、研磨板２３を矢印２５方向に動かし、研磨している状態を図８に示す。配線板２と研磨板２３間には切りくずの排出と摩擦による温度上昇を防ぐため、潤滑液（水でもよい）を供給しながら研磨する。
Therefore, the wiring board 2 is pressed against a polishing board 23 having a larger area than the wiring board 2 and having fine abrasive grains 21 fixed on a flat surface with a binder 22 such as a resin, and the polishing board 23 is moved in the direction of the arrow 25. FIG. 8 shows the state of polishing. In order to prevent temperature rise due to chip discharge and friction between the wiring board 2 and the polishing board 23, polishing is performed while supplying a lubricating liquid (or water).
砥粒２１が研磨板２３に固定されているため、通常の研磨で生じたような樹脂部分がよく削れて凹部８１を形成することもなく、表面を平坦に研磨することができる。しかし、図にあるように、大きな砥粒３０があると、側面電極４の端部２４に引っかかり、側面電極４の配線板２への密着力が小さいため、側面電極４の端部２４が剥離することが観察された。
Since the abrasive grains 21 are fixed to the polishing plate 23, the surface of the resin can be polished flat without causing the resin portion to be scraped well and forming the concave portion 81 as generated by normal polishing. However, as shown in the figure, when there is a large abrasive grain 30, the end 24 of the side electrode 4 is peeled off because it is caught by the end 24 of the side electrode 4 and the adhesion of the side electrode 4 to the wiring board 2 is small. To be observed.
そこで、側面電極４の端部２４の剥離を防止するために、２つの方法をとる。第１の方法は、側面電極４の端部２４に引き剥がしの力が作用しないような方向に研磨する。図９は側面電極４の側面図を示す。図において、研磨を矢印２６方向に実施することで、側面電極４の端部２４に大きな砥粒３０が引っかかることはなくなる。
Therefore, in order to prevent peeling of the end 24 of the side electrode 4, two methods are taken. In the first method, polishing is performed in such a direction that the peeling force does not act on the end portion 24 of the side electrode 4. FIG. 9 shows a side view of the side electrode 4. In the figure, by carrying out the polishing in the direction of the arrow 26, the large abrasive grains 30 are not caught on the end 24 of the side electrode 4.
ただ、配線板２の表面に形成したランド１５に引っかかることがあるが、ランド１５は配線板２との密着力がスルーホール電極よりも大きいため、引き剥がす力が作用しても剥離することはない。
However, the land 15 formed on the surface of the wiring board 2 may be caught. However, since the land 15 has a larger adhesion force with the wiring board 2 than the through-hole electrode, it does not peel off even if a peeling force is applied. Absent.
図１０は貫通していないスルーホール電極を分割して形成した側面電極４の側面図を示す。研磨を矢印２６方向に実施することで、大きな砥粒３０が作用しても側面電極４の端部２４に引っかかることはなく、側面電極４の端部２４の剥離を防止することができる。
FIG. 10 shows a side view of the side electrode 4 formed by dividing a through-hole electrode that does not penetrate. By carrying out the polishing in the direction of the arrow 26, even if large abrasive grains 30 act, the end 24 of the side electrode 4 is not caught, and the end 24 of the side electrode 4 can be prevented from peeling off.
第２の方法は、配線板２の内層にランド１６を設け、ランド１６と側面電極４を接続した構造をとり、側面電極を剥離しにくくする方法である。図１１は側面電極４の側面図を示す。内層に設けたランド１６は側面電極４と接続している状態を示す。
The second method is a method in which a land 16 is provided in the inner layer of the wiring board 2 and the land 16 and the side electrode 4 are connected to make it difficult to peel off the side electrode. FIG. 11 shows a side view of the side electrode 4. The land 16 provided in the inner layer shows a state where it is connected to the side electrode 4.
側面電極４がランド１６に接続されていることで、側面電極４の端部２４に砥粒３０が作用しても、側面電極４は剥離することがない。このように内層に設けたランド１６と側面電極４を接続することで、研磨方向を図９と１０にある矢印２６に限定する必要はない。
Since the side electrode 4 is connected to the land 16, the side electrode 4 does not peel even if the abrasive grains 30 act on the end 24 of the side electrode 4. By connecting the lands 16 and the side electrodes 4 provided in the inner layer in this way, it is not necessary to limit the polishing direction to the arrow 26 in FIGS.
この発明によれば、切断時の側面電極の金属バリが除去されているため、側面電極のはんだ接合信頼性が向上するという効果を奏する。
According to the present invention, since the metal burrs of the side electrode at the time of cutting are removed, there is an effect that the solder joint reliability of the side electrode is improved.
以下に、本発明にかかる半導体装置の製造方法の実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。
Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.
実施の形態１．
図１は、本実施の形態にかかる配線板２の側面に電極を有する半導体装置１の一例の斜視図を示す。半導体装置１は、側面（端面）に断面が凹面形状の側面電極４を有する配線板２上に半導体素子３などの電子部品が実装された構造をとる。側面電極４は、はんだ接合用の電極である。半導体素子３および電子部品と配線板２はワイヤおよびはんだなどのよく知られた方法で配線板２と電気的に接続された構造を有する。Embodiment 1 FIG.
FIG. 1 shows a perspective view of an example of asemiconductor device 1 having electrodes on the side surfaces of a wiring board 2 according to the present embodiment. The semiconductor device 1 has a structure in which an electronic component such as a semiconductor element 3 is mounted on a wiring board 2 having a side electrode 4 having a concave cross section on a side surface (end surface). The side electrode 4 is an electrode for solder joining. The semiconductor element 3 and the electronic component and the wiring board 2 have a structure that is electrically connected to the wiring board 2 by a well-known method such as a wire and solder.
図１は、本実施の形態にかかる配線板２の側面に電極を有する半導体装置１の一例の斜視図を示す。半導体装置１は、側面（端面）に断面が凹面形状の側面電極４を有する配線板２上に半導体素子３などの電子部品が実装された構造をとる。側面電極４は、はんだ接合用の電極である。半導体素子３および電子部品と配線板２はワイヤおよびはんだなどのよく知られた方法で配線板２と電気的に接続された構造を有する。
FIG. 1 shows a perspective view of an example of a
図２は、半導体装置１をマザーボード１０にはんだ９にて実装した状態を示す断面図である。半導体素子３は凹部を設けた配線板２上に接合され、配線板２の側面に側面電極４が設けられている。なお、半導体装置１の配線板２は凹部を有した例を示しているが、凹部がなくてもよい。配線板２は、例えばマザーボード１０と同じ材料で構成される。通常はエポキシ樹脂とガラス繊維で構成されるガラスエポキシプリント配線板等が用いられる。
FIG. 2 is a cross-sectional view showing a state in which the semiconductor device 1 is mounted on the mother board 10 with solder 9. The semiconductor element 3 is bonded onto the wiring board 2 provided with a recess, and a side electrode 4 is provided on the side surface of the wiring board 2. In addition, although the wiring board 2 of the semiconductor device 1 has shown the example which has a recessed part, it does not need to have a recessed part. For example, the wiring board 2 is made of the same material as the mother board 10. Usually, a glass epoxy printed wiring board composed of epoxy resin and glass fiber is used.
図３－１～図３－３は、本実施の形態にかかる半導体装置の製造方法を順に示す平面図であり、図３－１～図３－３にそれぞれ対応して、図３－４は断面図、図３－５と図３－６は側面図である。図３－１～図３－６は、図１及び図２に示した配線板２の側面電極４を製造する方法を、側面電極４の一部を配線板２のマザーボード（裏側）からみた平面図とそれに対応する断面図と側面図を示している。
FIGS. 3-1 to 3-3 are plan views sequentially illustrating the method for manufacturing the semiconductor device according to the present embodiment. FIGS. 3-4 correspond to FIGS. 3-1 to 3-3, respectively. Sectional views, FIGS. 3-5 and 3-6 are side views. FIGS. 3-1 to 3-6 show a method of manufacturing the side electrode 4 of the wiring board 2 shown in FIGS. 1 and 2, and a plan view of a part of the side electrode 4 viewed from the mother board (back side) of the wiring board 2. FIGS. The figure and the corresponding sectional view and side view are shown.
図３－１及び図３－４は、配線板２となる材料５に、写真製版とめっきおよびエッチングにて、スルーホール電極６を形成した状態を示す。図において、スルーホール電極６の断面は円であるが、これに限定されず、長円などでもかまわない。
FIGS. 3-1 and 3-4 show a state in which the through-hole electrode 6 is formed on the material 5 to be the wiring board 2 by photolithography, plating and etching. In the drawing, the cross-section of the through-hole electrode 6 is a circle, but is not limited to this, and may be an ellipse.
図３－２及び図３－５は、断面が半円（凹部形状）形状の側面電極４を形成するために、ダイシングソーによる機械加工（ダイシング）にて、配線板２となる材料５を切断した状態を示す。配線板２となる材料５の切断面に沿って、側面電極４の内側にむかって、金属バリ７が発生している。
3-2 and FIG. 3-5, the material 5 to be the wiring board 2 is cut by machining (dicing) with a dicing saw in order to form the side electrode 4 having a semicircular (concave shape) cross section. Shows the state. A metal burr 7 is generated toward the inside of the side electrode 4 along the cut surface of the material 5 to be the wiring board 2.
図３－３及び図３－６は、配線板２の端面８、つまり切断面を研磨（研削）した状態を示す。金属バリ７を除去した側面電極４を形成することができる。
FIGS. 3-3 and 3-6 show a state where the end face 8, that is, the cut surface of the wiring board 2 is polished (ground). The side electrode 4 from which the metal burr 7 is removed can be formed.
以上の工程を経ることにより、側面電極４形成時の金属バリをなくすことができるため、はんだ接合部の信頼性を向上させることが可能となる。
By passing through the above process, the metal burr | flash at the time of side electrode 4 formation can be eliminated, Therefore It becomes possible to improve the reliability of a solder joint part.
具体的には銅めっき１１の厚みは２０μｍ、砥粒としてアルミナが樹脂バインダーで固定された研磨板を用いたが、これに限定されることはなく、砥粒として、ＳｉＣ、ダイヤモンドを用いてもよい。また、配線板２として、ガラスエポキシプリント配線板を用いたがこれに限定されるものではない。
Specifically, the thickness of the copper plating 11 was 20 μm, and an abrasive plate in which alumina was fixed as an abrasive grain with a resin binder was used. However, the present invention is not limited to this, and SiC or diamond may be used as an abrasive grain. Good. Moreover, although the glass epoxy printed wiring board was used as the wiring board 2, it is not limited to this.
以上説明したように、本実施の形態によって、配線板ごとに治具を作製する必要なく低コストで側面電極の接合信頼性を向上させることが可能となる。
As described above, according to the present embodiment, it is possible to improve the bonding reliability of the side electrodes at a low cost without the need to prepare a jig for each wiring board.
実施の形態２．
本実施の形態にかかる半導体装置の製造方法は、めっきの工程以外は、実施の形態１と基本的には同様である。Embodiment 2. FIG.
The manufacturing method of the semiconductor device according to the present embodiment is basically the same as that of the first embodiment except for the plating step.
本実施の形態にかかる半導体装置の製造方法は、めっきの工程以外は、実施の形態１と基本的には同様である。
The manufacturing method of the semiconductor device according to the present embodiment is basically the same as that of the first embodiment except for the plating step.
即ち、図４に示すように、銅めっき１１のみを用いるのではなく、銅１１上にニッケル１２と金１３をめっきして側面電極４を形成する。最後に、はんだに濡れやすい金属である金１３で表面をめっきすることによって、側面電極４の表面のはんだ濡れ性をよくすることができる。
That is, as shown in FIG. 4, the side electrode 4 is formed by plating nickel 12 and gold 13 on the copper 11 instead of using only the copper plating 11. Finally, the surface of the side electrode 4 can be improved in solder wettability by plating the surface with gold 13 which is a metal that easily wets the solder.
その結果、はんだの接合面積を大きくすることができるので、側面電極４のはんだ接合信頼性をさらに向上することができる。
As a result, since the solder joint area can be increased, the solder joint reliability of the side electrode 4 can be further improved.
次に、側面電極４が、銅１１、ニッケル１２、金１３の３層構成である時に、機械加工（ダイシング）による切断後の様子を図５に示す。このとき発生する金属バリ７を詳細に分析したところ、バリ７は主にニッケル１２で構成されることが明らかになった。
Next, FIG. 5 shows a state after cutting by machining (dicing) when the side electrode 4 has a three-layer structure of copper 11, nickel 12, and gold 13. Detailed analysis of the metal burrs 7 generated at this time revealed that the burrs 7 were mainly composed of nickel 12.
そこで、ニッケル１２を無電解めっきで形成する。無電解ニッケルめっきはＰを含有しており、電解ニッケルよりも硬い。図６は、無電解ニッケルめっき１４を用いた場合の、切断後の状態を示す。Ｎｉが硬いので、バリが延びず、バリ７の長さを短くすることができる。そのため、研磨する工程において、研磨加工量を少なくすることが可能となり、生産性が向上する。
Therefore, nickel 12 is formed by electroless plating. Electroless nickel plating contains P and is harder than electrolytic nickel. FIG. 6 shows a state after cutting when the electroless nickel plating 14 is used. Since Ni is hard, the burr does not extend and the length of the burr 7 can be shortened. Therefore, it is possible to reduce the amount of polishing processing in the polishing step, and productivity is improved.
さらに、本願発明は上記実施の形態に限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で種々に変形することが可能である。また、上記実施の形態には種々の段階の発明が含まれており、開示される複数の構成要件における適宜な組み合わせにより種々の発明が抽出されうる。例えば、実施の形態に示される全構成要件からいくつかの構成要件が削除されても、発明が解決しようとする課題の欄で述べた課題が解決でき、発明の効果の欄で述べられている効果が得られる場合には、この構成要件が削除された構成が発明として抽出されうる。更に、異なる実施の形態にわたる構成要素を適宜組み合わせてもよい。
Furthermore, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent requirements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When an effect is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention. Furthermore, the constituent elements over different embodiments may be appropriately combined.
以上のように、本発明にかかる半導体装置の製造方法は、側面電極を有する配線板の製造に有用であり、特に、はんだ接合用の側面電極を有する配線板に適している。
As described above, the method for manufacturing a semiconductor device according to the present invention is useful for manufacturing a wiring board having side electrodes, and is particularly suitable for a wiring board having side electrodes for solder bonding.
１ 半導体装置
２ 配線板
３ 半導体素子
４ 側面電極
５ 配線板となる材料
６ スルーホール電極
７ 金属バリ
８ 配線板の端面
９ はんだ
１０ マザーボード
１１ 銅めっき
１２ ニッケルめっき
１３ 金めっき
１４ 無電解ニッケルめっき
１５ ランド
１６ 内層に設けたランド
２０ 遊離した砥粒
２１ 固定された砥粒
２２ バインダー
２３ 研磨板（工具）
２４ 側面電極の端部
２５ スルーホール電極に垂直な研磨方向
２６ スルーホール電極に平行な研磨方向
３０ 大きな砥粒
８１ 端部に形成された凹部 DESCRIPTION OFSYMBOLS 1 Semiconductor device 2 Wiring board 3 Semiconductor element 4 Side electrode 5 Material used as a wiring board 6 Through-hole electrode 7 Metal burr 8 End face of wiring board 9 Solder 10 Mother board 11 Copper plating 12 Nickel plating 13 Gold plating 14 Electroless nickel plating 15 Land 16 Lands provided in the inner layer 20 Abrasive grains 21 Fixed abrasive grains 22 Binder 23 Polishing plate (tool)
24 End ofside electrode 25 Polishing direction perpendicular to through-hole electrode 26 Polishing direction parallel to through-hole electrode 30 Large abrasive grains 81 Concavity formed at end
２ 配線板
３ 半導体素子
４ 側面電極
５ 配線板となる材料
６ スルーホール電極
７ 金属バリ
８ 配線板の端面
９ はんだ
１０ マザーボード
１１ 銅めっき
１２ ニッケルめっき
１３ 金めっき
１４ 無電解ニッケルめっき
１５ ランド
１６ 内層に設けたランド
２０ 遊離した砥粒
２１ 固定された砥粒
２２ バインダー
２３ 研磨板（工具）
２４ 側面電極の端部
２５ スルーホール電極に垂直な研磨方向
２６ スルーホール電極に平行な研磨方向
３０ 大きな砥粒
８１ 端部に形成された凹部 DESCRIPTION OF
24 End of
Claims (5)
- 半導体素子を搭載する配線板の製造において、
前記配線板となる材料にスルーホール電極を形成する工程と、機械加工によって前記スルーホールを分割するように切断する工程と、前記切断面を研磨（研削）する工程とを具備することにより、前記配線板の側面電極を形成することを特徴とする半導体装置の製造方法。 In manufacturing a wiring board on which a semiconductor element is mounted,
Comprising a step of forming a through-hole electrode in the material to be the wiring board, a step of cutting so as to divide the through-hole by machining, and a step of polishing (grinding) the cut surface. A method of manufacturing a semiconductor device, comprising forming a side electrode of a wiring board. - 前記研磨は、前記配線板よりも大きく平坦な表面上に微細な砥粒を固定した研磨板を用いることを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the polishing uses a polishing plate in which fine abrasive grains are fixed on a flat surface larger than the wiring board.
- 前記研磨は、前記配線板のスルーホール電極にそって、厚み方向に研磨する
ことを特徴とする請求項１または２に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein the polishing is performed in a thickness direction along the through-hole electrode of the wiring board. - 前記配線板は複数の配線層が積層された多層配線層で構成され、前記多層配線層の配線が前記スルーホールに接続されていることを特徴とする請求項１または２に記載の半導体装置の製造方法。 3. The semiconductor device according to claim 1, wherein the wiring board is formed of a multilayer wiring layer in which a plurality of wiring layers are stacked, and the wiring of the multilayer wiring layer is connected to the through hole. Production method.
- 前記スルーホール電極のめっき工程において、無電解めっきでニッケルのめっきを行う
ことを特徴とする請求項１に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein in the plating process of the through-hole electrode, nickel is plated by electroless plating.
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|---|---|---|---|
| PCT/JP2010/059031 WO2011148491A1 (en) | 2010-05-27 | 2010-05-27 | Process for production of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2010/059031 WO2011148491A1 (en) | 2010-05-27 | 2010-05-27 | Process for production of semiconductor device |
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| JPH06196857A (en) * | 1992-12-25 | 1994-07-15 | Tanaka Kikinzoku Kogyo Kk | Working method of half-divided through hole in printed-wiring board |
| JPH09186458A (en) * | 1995-12-28 | 1997-07-15 | Kyocera Corp | Ceramic board, manufacture thereof and split circuit board |
| JP2000114715A (en) * | 1998-09-24 | 2000-04-21 | Lucent Technol Inc | Manufacture of low contamination interconnection having low-inductance periphery |
| JP2004214410A (en) * | 2002-12-27 | 2004-07-29 | Ykc:Kk | Multi-layer wiring substrate and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5383079A (en) * | 1976-12-28 | 1978-07-22 | Fujitsu Ltd | Method of producing printed board |
| JPH06196857A (en) * | 1992-12-25 | 1994-07-15 | Tanaka Kikinzoku Kogyo Kk | Working method of half-divided through hole in printed-wiring board |
| JPH09186458A (en) * | 1995-12-28 | 1997-07-15 | Kyocera Corp | Ceramic board, manufacture thereof and split circuit board |
| JP2000114715A (en) * | 1998-09-24 | 2000-04-21 | Lucent Technol Inc | Manufacture of low contamination interconnection having low-inductance periphery |
| JP2004214410A (en) * | 2002-12-27 | 2004-07-29 | Ykc:Kk | Multi-layer wiring substrate and method for manufacturing the same |
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