JP2004200527A

JP2004200527A - Method for processing semiconductor wafer

Info

Publication number: JP2004200527A
Application number: JP2002369116A
Authority: JP
Inventors: Takeshi Ikeda; 健池田; Shoji Masuyama; 尚司増山
Original assignee: Hitachi Cable Ltd
Current assignee: Hitachi Cable Ltd
Priority date: 2002-12-20
Filing date: 2002-12-20
Publication date: 2004-07-15

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for processing a semiconductor wafer, capable of preventing the occurrence of chipping which is likely to occur, at a portion where a cleavage surface and a front and back surface intersect with each other, when the front and back surface of the semiconductor wafer having the cleavage surface are lapped. <P>SOLUTION: In the method for processing the semiconductor wafer, a cleavage surface 1c is formed on the outer periphery of a semiconductor wafer 1; chamfering is performed to at least either of a front surface 1a side or a back surface 1b side of the semiconductor wafer 1 of the cleavage surface 1c; at least one of the front surface 1a and the back surface 1b of the chamfered semiconductor wafer 1 is lapped. At least either of a front surface side angular part or a back surface side angular part, at a portion where the cleavage surface 1c formed in the outer periphery of the semiconductor wafer 1 and the front and back surfaces 1a, 1b of the semiconductor wafer 1 intersect with each other, is chamfered down to a lapping depth or to the final polishing depth of the front surface 1a or the back surface 1b of the semiconductor wafer 1. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体ウェハの加工方法に係り、特に、オリエンテーションフラット用の劈開面が形成されたものに関する。
【０００２】
【従来の技術】
従来の半導体ウェハには、結晶方位の判別や正確な位置合わせのためにオリエンテーションフラットが形成されたものが知られている（例えば、特許文献１参照）。オリエンテーションフラットとは、半導体ウェハに劈開面を形成することにより形成することができる。劈開面は、半導体レーザーにおける光の増幅を行わせるための反射鏡としても利用される。
【０００３】
【特許文献１】
特開２００２−５２４４８号公報（図３）
【０００４】
【発明が解決しようとする課題】
しかしながら、従来の半導体ウェハの加工方法では、劈開面を有する半導体ウェハのラッピングにおいては、半導体ウェハの劈開面と半導体ウェハの表裏面とが交差する部分にチッピング（欠損）が生じ易く、このチッピングは後工程である一次研磨や最終研磨等で除去しきれない場合が多く、半導体素子の歩留まりが低下するという問題があった。
【０００５】
本発明は、上記事情を考慮し、劈開面を有する半導体ウェハの表裏面のラッピングにおいて、劈開面と表裏面とが交差する部分に生じ易いチッピングの発生を防止できる半導体ウェハの加工方法を提供することを目的とする。
【０００６】
【課題を解決するための手段】
請求項１に記載の半導体ウェハの加工方法は、半導体ウェハの外周に劈開面を形成し、この劈開面の前記半導体ウェハの表面側と裏面側とのうち少なくとも一方に面取りを行い、この面取りされた前記半導体ウェハの表面と裏面とのうち少なくとも一方にラッピングを施す半導体ウェハの加工方法であって、前記半導体ウェハの外周に形成された前記劈開面と前記半導体ウェハの表裏面とが交差する部分である表面側角部と裏面側角部とのうち少なくとも一方を、前記半導体ウェハの表面又は裏面のラッピング深さまで面取りすることを特徴とする。
【０００７】
請求項１に記載の発明によれば、半導体ウェハの外周に形成された劈開面と半導体ウェハの表裏面とが交差する部分である表面側角部や裏面側角部に面取りが施されるので、半導体ウェハの表裏面をラッピングするときに劈開面と表裏面とが交差する部分にチッピングが発生するのを抑止することができる。ひいては、半導体ウェハの結晶方位の判別や位置合わせを高精度に行うことができる。
【０００８】
また、面取りの深さは表裏面のラッピングの深さとされるので、面取りが小さすぎて劈開面と表裏面とが交差する部分にチッピングが発生するのを防止することができる。また、反対に面取りが大きすぎて劈開面の平坦度が狂い半導体ウェハの位置合わせの精度が低下するのを防止することができる。
【０００９】
請求項２に記載の半導体ウェハの加工方法は、半導体ウェハの外周に劈開面を形成し、この劈開面の前記半導体ウェハの表面側と裏面側とのうち少なくとも一方に面取りを行い、この面取りされた前記半導体ウェハの表面と裏面とのうち少なくとも一方にラッピングを施し、更に最終研磨を施す半導体ウェハの加工方法であって、前記半導体ウェハの外周に形成された前記劈開面と前記半導体ウェハの表裏面とが交差する部分である表面側角部と裏面側角部とのうち少なくとも一方を、前記半導体ウェハの表面又は裏面の最終研磨深さまで面取りすることを特徴とする。
【００１０】
請求項２に記載の発明によれば、半導体ウェハの外周に形成された劈開面と半導体ウェハの表裏面とが交差する部分である表面側角部や裏面側角部に面取りが施されるので、半導体ウェハの表裏面をラッピングするときに劈開面と表裏面とが交差する部分にチッピングが発生するのを抑止することができる。ひいては、半導体ウェハの結晶方位の判別や位置合わせを高精度に行うことができる。
【００１１】
また、面取りの深さは最終研磨深さとされるので、最終研磨後は面取りがなくなり、面取りがチッピングの発生の抑止にのみ有効に利用される。また、最終研磨後に面取りがなくなることにより、平坦度の高い劈開面が得られ、半導体ウェハの結晶方位の判別や位置合わせの精度を向上させることができる。
【００１２】
請求項３に記載の半導体ウェハの加工方法は、半導体ウェハの表面と裏面とのうち少なくとも一方にラッピングを施し、このラッピングされた半導体ウェハの外周に劈開面を形成し、この劈開面と前記半導体ウェハの表裏面とが交差する部分である表面側角部と裏面側角部とのうち前記ラッピングを施した側の角部に面取りを行い、更に前記半導体ウェハのラッピング面に最終研磨を施す半導体ウェハの加工方法であって、前記面取りは、前記半導体ウェハの表面又は裏面の最終研磨深さまで行うことを特徴とする。
【００１３】
請求項３に記載の発明によれば、半導体ウェハの表裏面をラッピングした後に劈開面を形成するので、劈開面と表裏面とにより形成される角部にチッピングが発生するのを防止することができる。ひいては、半導体ウェハの結晶方位の判別や位置合わせを高精度に行うことができる。
【００１４】
また、劈開面と表裏面とが交差する部分である表面側角部や裏面側角部に面取りがなされてから表裏面に最終研磨がなされるが、最終研磨はラッピングよりも加工量が少なく、また研削抵抗が小さいため、チッピングの発生を抑止することができる。
【００１５】
【発明の実施の形態】
以下、本発明の実施形態を図面に基づいて説明する。
【００１６】
［第１実施形態］
図１のフローチャートを用いて、本発明の半導体ウェハの加工方法の第１実施形態を説明する。
【００１７】
先ず、ステップＳ１において、ＧａＡｓ単結晶をスライスして図２（ａ）及び図２（ｂ）に示すような半導体ウェハ１を作成する。例えば、直径は３インチ、厚さは５５０μｍの円板状にする。
【００１８】
次いで、ステップＳ２において、半導体ウェハ１の表面１ａ又は裏面１ｂにダイヤモンドペンで傷を付けることにより、図３（ａ）及び図３（ｂ）に示すような劈開面１ｃを形成する。この劈開面１ｃは、オリエンテーションフラットとしての役割を果たす。
【００１９】
次いで、ステップＳ３において、面取りフライスを用いて、劈開面１ｃ以外の半導体ウェハ１の外周部の表面側角部や裏面側角部を丸める面取りを行い、その後、半導体ウェハ１の表裏面１ａ，１ｂと劈開面１ｃとが交差する部分である表面側角部や裏面側角部について、劈開面１ｃ以外の半導体ウェハ１の外周部の面取りよりも小さな丸みで面取りを行う。そして、図４（ａ）及び図４（ｂ）に示すような面取り部１ｄ，１ｅが形成された半導体ウェハ１を得る。なお、図４（ｂ）に示す二点鎖線はラッピング代を示している。
【００２０】
次いで、ステップＳ４において、半導体ウェハ１をエッチング液に浸しエッチングを施し、ＧａＡｓ単結晶のスライス時及び面取り時の加工変質層を除去する。
【００２１】
次いで、ステップＳ５において、半導体ウェハ１を両面ラッピング機にセットし、面取り部１ｄ，１ｅがなくなるまで表裏面１ａ，１ｂにラッピングを施す。なお、ラッピング後、２０枚の半導体ウェハ１の劈開面１ｃを顕微鏡により５０倍に拡大して検査したところ、全ての半導体ウェハ１について、チッピングが確認されなかった。
【００２２】
次いで、ステップＳ６において、半導体ウェハ１をエッチング液に浸しエッチングを施し、ラッピング時の加工変質層を除去する。
【００２３】
最後に、ステップＳ７において、高精度に仕上げられた平坦面を有する貼付プレートにワックスが全面に塗布された半導体ウェハ１を貼付し、一次研磨及び最終研磨を施し、更に半導体ウェハ１を貼付プレートから離隔し、ワックス除去洗浄を行う。ここでワックスは、半導体ウェハ１の表裏面１ａ，１ｂを保護する役割を果たすとともに、貼付プレートと半導体ウェハ１とを貼り付ける役割も果たす。また、ワックス除去洗浄は、有機アルカリ洗浄液にウェハを浸すことにより行う。
【００２４】
なお、ワックス除去洗浄後、２０枚の半導体ウェハ１の劈開面１ｃを顕微鏡により５０倍に拡大して検査したところ、チッピングが確認されなかった。また、レーザー顕微鏡を用い、２０枚の半導体ウェハ１の劈開面１ｃと表裏面１ａ，１ｂとが交差する部分の両端及び中心について３箇所の面ダレを調べたところ劈開面１ｃに面取りを行わなかった半導体ウェハ１と同様の形状であり、面取り部１ｄ，１ｅは完全に除去されていた。
【００２５】
以上述べたように本発明の第１実施形態によれば、半導体ウェハ１の外周に形成された劈開面１ｃと半導体ウェハ１の表裏面１ａ，１ｂとが交差する部分である表面側角部や裏面側角部に面取りが施されるので、半導体ウェハ１の表裏面１ａ，１ｂをラッピングするときに劈開面１ｃと表裏面１ａ，１ｂとが交差する部分にチッピングが発生するのを抑止することができる。ひいては、半導体ウェハ１の結晶方位の判別や位置合わせを高精度に行うことができる。
【００２６】
また、面取りの深さは表裏面１ａ，１ｂのラッピングの深さとされるので、面取りが小さすぎて劈開面１ｃと表裏面１ａ，１ｂとが交差する部分にチッピングが発生するのを防止することができる。また、反対に面取りが大きすぎて劈開面１ｃの平坦度が狂い半導体ウェハ１の位置合わせの精度が低下するのを防止することができる。
【００２７】
なお、上述した第１実施形態では、ラッピングの深さまで面取り部１ｄ，１ｅを形成した例について説明したが、一次研磨の深さや最終研磨の深さまで面取り部１ｄ，１ｅを形成しても良い。
【００２８】
［第２実施形態］
図５のフローチャートを用いて、本発明の半導体ウェハの加工方法の第２実施形態を説明する。
【００２９】
先ず、ステップＳ８において、ＧａＡｓ単結晶をスライスして図６（ａ）及び図６（ｂ）に示すような半導体ウェハ３を作成する。なお、図６（ｂ）に示す二点鎖線はラッピング代を示している。
【００３０】
次いで、ステップＳ９において、半導体ウェハ３をエッチング液に浸しエッチングを施し、ＧａＡｓ単結晶のスライス時の加工変質層を除去する。
【００３１】
次いで、ステップＳ１０において、半導体ウェハ３を両面ラッピング機にセットし、所定の深さまで表裏面３ａ，３ｂにラッピングを施す。
【００３２】
次いで、ステップＳ１１において、半導体ウェハ３の表面３ａ又は裏面３ｂにダイヤモンドペンで傷を付けることにより、図７（ａ）及び図７（ｂ）に示すような劈開面３ｃを形成する。
【００３３】
次いで、ステップＳ１２において、面取りフライスを用いて、劈開面３ｃ以外の半導体ウェハ３の外周部の表面側角部や裏面側角部に丸め形状の面取りを行い、その後、半導体ウェハ３の表裏面３ａ，３ｂと劈開面３ｃとが交差する部分である表面側角部や裏面側角部について、劈開面３ｃ以外の半導体ウェハ３の外周部の面取りよりも小さな丸みで面取りを行う。そして、図８（ａ）及び図８（ｂ）に示すような面取り部３ｄ，３ｅが形成された半導体ウェハ３を得る。
【００３４】
次いで、ステップＳ１３において、半導体ウェハ３をエッチング液に浸しエッチングを施し、面取り時の加工変質層を除去する。
【００３５】
最後に、ステップＳ１４において、高精度に仕上げられた平坦面を有する貼付プレートにワックスが全面に塗布された半導体ウェハ３を貼付し、一次研磨及び最終研磨を施し、更に半導体ウェハ３を貼付プレートから離隔し、ワックス除去洗浄を行う。
【００３６】
以上述べたように本発明の第２実施形態によれば、半導体ウェハ３の表裏面３ａ，３ｂをラッピングした後に劈開面３ｃを形成するので、半導体ウェハ３の劈開面３ｃと半導体ウェハ３の表裏面３ａ，３ｂとにより形成される角部にチッピングが発生するのを防止することができる。ひいては、半導体ウェハ３の結晶方位の判別や位置合わせを高精度に行うことができる。
【００３７】
また、劈開面３ｃと表裏面３ａ，３ｂとが交差する部分である表面側角部や裏面側角部に面取りがなされてから表裏面３ａ，３ｂに最終研磨がなされるが、最終研磨はラッピングよりも加工量が少なく、また研削抵抗が小さいため、チッピングの発生を抑止することができる。
【００３８】
なお、上述した第２実施形態では、最終研磨深さまで面取り部３ｄ，３ｅを形成した例について説明したが、一次研磨の深さまで面取り部３ｄ，３ｅを形成しても良い。
【００３９】
また、上述した第１及び第２実施形態では、面取り部１ｄ，１ｅ，３ｄ，３ｅを丸め形状にした例について説明したが、Ｃ面取りにしても良い。要するに、チッピングの発生を抑止することができる形状であれば良い。
【００４０】
【発明の効果】
以上説明したように、本発明によれば、半導体ウェハの外周に形成された劈開面と半導体ウェハの表裏面とが交差する部分である表面側角部や裏面側角部に面取りが施されるので、半導体ウェハの表裏面をラッピングするときに劈開面と表裏面とが交差する部分にチッピングが発生するのを抑止することができる。ひいては、半導体ウェハの結晶方位の判別や位置合わせを高精度に行うことができる。また、面取りの深さは表裏面のラッピングの深さ又は最終研磨深さまでとされるので、面取りが小さすぎて劈開面と表裏面とが交差する部分にチッピングが発生するのを防止することができる。また、反対に面取りが大きすぎて劈開面の平坦度が狂い半導体ウェハの位置合わせの精度が低下するのを防止することができる。
【図面の簡単な説明】
【図１】本発明の半導体ウェハの加工方法の第１実施形態を示すフローチャートである。
【図２】ＧａＡｓ単結晶をスライスした後の半導体ウェハを示す説明図であり、（ａ）及び（ｂ）はそれぞれ半導体ウェハの上面図及び側面図である。
【図３】図２の半導体ウェハの劈開後の状態を示す説明図であり、（ａ）及び（ｂ）はそれぞれ半導体ウェハの上面図及び側面図である。
【図４】図３の半導体ウェハの面取り後の状態を示す説明図であり、（ａ）及び（ｂ）はそれぞれ半導体ウェハの上面図及び側面図である。
【図５】本発明の半導体ウェハの加工方法の第２実施形態を示すフローチャートである。
【図６】ＧａＡｓ単結晶をスライスした後の半導体ウェハを示す説明図であり、（ａ）及び（ｂ）はそれぞれス半導体ウェハの上面図及び側面図である。
【図７】図６の半導体ウェハのラッピング及び劈開後の状態を示す説明図であり、（ａ）及び（ｂ）はそれぞれ半導体ウェハの上面図及び側面図である。
【図８】図７の半導体ウェハの面取り後の状態を示す説明図であり、（ａ）及び（ｂ）はそれぞれ半導体ウェハの上面図及び側面図である。
【符号の説明】
１，３半導体ウェハ
１ａ，３ａ表面
１ｂ，３ｂ裏面
１ｃ，３ｃ劈開面
１ｄ，１ｅ，３ｄ，３ｅ面取り部[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for processing a semiconductor wafer, and more particularly, to a method for forming a cleavage plane for an orientation flat.
[0002]
[Prior art]
2. Description of the Related Art A conventional semiconductor wafer is known in which an orientation flat is formed for discriminating crystal orientation and accurate alignment (for example, see Patent Document 1). The orientation flat can be formed by forming a cleavage plane on a semiconductor wafer. The cleavage plane is also used as a reflector for amplifying light in a semiconductor laser.
[0003]
[Patent Document 1]
JP-A-2002-52448 (FIG. 3)
[0004]
[Problems to be solved by the invention]
However, in the conventional semiconductor wafer processing method, when lapping a semiconductor wafer having a cleavage plane, chipping (deletion) is likely to occur at a portion where the cleavage plane of the semiconductor wafer intersects with the front and back surfaces of the semiconductor wafer. In many cases, it cannot be completely removed by primary polishing or final polishing, which is a post-process, and there has been a problem that the yield of semiconductor elements is reduced.
[0005]
In view of the above circumstances, the present invention provides a semiconductor wafer processing method capable of preventing the occurrence of chipping, which is likely to occur at a portion where the cleavage plane and the front and back surfaces intersect, in wrapping the front and back surfaces of a semiconductor wafer having a cleavage plane. The purpose is to:
[0006]
[Means for Solving the Problems]
The method for processing a semiconductor wafer according to claim 1, wherein a cleavage plane is formed on an outer periphery of the semiconductor wafer, and at least one of the cleavage plane on the front side and the back side of the semiconductor wafer is chamfered. A method of processing a semiconductor wafer, wherein at least one of a front surface and a back surface of the semiconductor wafer is wrapped, wherein the cleavage plane formed on the outer periphery of the semiconductor wafer intersects the front and back surfaces of the semiconductor wafer. At least one of the front side corner and the back side corner is chamfered to the lapping depth of the front or back surface of the semiconductor wafer.
[0007]
According to the first aspect of the present invention, chamfering is performed on the front side corner and the back side corner, which are portions where the cleavage surface formed on the outer periphery of the semiconductor wafer and the front and back surfaces of the semiconductor wafer intersect. In addition, when lapping the front and back surfaces of the semiconductor wafer, it is possible to suppress occurrence of chipping at a portion where the cleavage plane and the front and back surfaces intersect. As a result, the determination of the crystal orientation of the semiconductor wafer and the alignment can be performed with high accuracy.
[0008]
Further, since the chamfering depth is set to the lapping depth of the front and back surfaces, it is possible to prevent chipping from occurring at a portion where the cleavage surface and the front and back surfaces intersect due to the chamfering being too small. On the other hand, it is possible to prevent the chamfering from being too large and the flatness of the cleavage plane from being out of order, thereby lowering the accuracy of alignment of the semiconductor wafer.
[0009]
In the method for processing a semiconductor wafer according to claim 2, a cleavage plane is formed on the outer periphery of the semiconductor wafer, and at least one of the cleavage plane on the front side and the back side of the semiconductor wafer is chamfered. A lapping process for at least one of a front surface and a back surface of the semiconductor wafer, and further performing final polishing, wherein the cleaved surface formed on the outer periphery of the semiconductor wafer and the surface of the semiconductor wafer are formed. At least one of a front side corner and a back side corner, which is a portion where the back surface intersects, is chamfered to a final polishing depth of the front surface or the back surface of the semiconductor wafer.
[0010]
According to the second aspect of the present invention, chamfering is performed on the front side corner and the back side corner, which are portions where the cleavage plane formed on the outer periphery of the semiconductor wafer and the front and back surfaces of the semiconductor wafer intersect. In addition, when lapping the front and back surfaces of the semiconductor wafer, it is possible to suppress occurrence of chipping at a portion where the cleavage plane and the front and back surfaces intersect. As a result, the determination of the crystal orientation of the semiconductor wafer and the alignment can be performed with high accuracy.
[0011]
Further, since the chamfering depth is the final polishing depth, the chamfering is eliminated after the final polishing, and the chamfering is effectively used only for suppressing the occurrence of chipping. In addition, since there is no chamfer after the final polishing, a cleaved surface with high flatness can be obtained, and the accuracy of the determination of the crystal orientation of the semiconductor wafer and the alignment can be improved.
[0012]
4. The method for processing a semiconductor wafer according to claim 3, wherein at least one of the front surface and the back surface of the semiconductor wafer is wrapped, and a cleaved surface is formed on an outer periphery of the wrapped semiconductor wafer. A semiconductor in which chamfering is performed on the wrapped side of the front side corner and the back side corner which are portions where the front and back surfaces of the wafer intersect, and the final polishing is performed on the lapping surface of the semiconductor wafer. In a wafer processing method, the chamfering is performed up to a final polishing depth of a front surface or a back surface of the semiconductor wafer.
[0013]
According to the third aspect of the present invention, since the cleavage surface is formed after lapping the front and back surfaces of the semiconductor wafer, it is possible to prevent chipping from occurring at the corner formed by the cleavage surface and the front and back surfaces. it can. As a result, the determination of the crystal orientation of the semiconductor wafer and the alignment can be performed with high accuracy.
[0014]
In addition, after the chamfer is made on the front side corner and the back side corner, which is the portion where the cleavage plane and the front and back intersect, the front and back are finally polished, but the final polishing requires less processing than lapping, Further, since the grinding resistance is small, occurrence of chipping can be suppressed.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
[First Embodiment]
The first embodiment of the method for processing a semiconductor wafer according to the present invention will be described with reference to the flowchart of FIG.
[0017]
First, in step S1, a GaAs single crystal is sliced to form a semiconductor wafer 1 as shown in FIGS. 2 (a) and 2 (b). For example, the disk is 3 inches in diameter and 550 μm in thickness.
[0018]
Next, in step S2, the front surface 1a or the back surface 1b of the semiconductor wafer 1 is scratched with a diamond pen to form a cleavage plane 1c as shown in FIGS. 3 (a) and 3 (b). This cleavage plane 1c plays a role as an orientation flat.
[0019]
Next, in step S3, chamfering is performed by using a chamfering mill to round the front side corner and the back side corner of the outer peripheral portion of the semiconductor wafer 1 other than the cleavage plane 1c, and thereafter, the front and back surfaces 1a and 1b of the semiconductor wafer 1 are performed. The corners on the front surface side and the back surface side, which are the intersections of the cleavage plane 1c and the cleavage plane 1c, are chamfered with smaller roundness than the chamfer of the outer peripheral part of the semiconductor wafer 1 other than the cleavage plane 1c. Then, a semiconductor wafer 1 having chamfered portions 1d and 1e as shown in FIGS. 4A and 4B is obtained. Note that the two-dot chain line shown in FIG. 4B indicates a wrapping margin.
[0020]
Next, in step S4, the semiconductor wafer 1 is immersed in an etchant and etched to remove the work-affected layer during slicing and chamfering of the GaAs single crystal.
[0021]
Next, in step S5, the semiconductor wafer 1 is set in a double-sided lapping machine, and lapping is performed on the front and back surfaces 1a and 1b until the chamfered portions 1d and 1e disappear. After lapping, when the cleaved surfaces 1c of the 20 semiconductor wafers 1 were inspected with a microscope at a magnification of 50 times, chipping was not confirmed for all the semiconductor wafers 1.
[0022]
Next, in step S6, the semiconductor wafer 1 is immersed in an etchant and etched to remove a damaged layer during lapping.
[0023]
Finally, in step S7, the semiconductor wafer 1 on which wax is applied over the entire surface is attached to an attaching plate having a flat surface that has been finished with high precision, primary polishing and final polishing are performed, and the semiconductor wafer 1 is further removed from the attaching plate. Separate and perform wax removal cleaning. Here, the wax plays a role of protecting the front and back surfaces 1a and 1b of the semiconductor wafer 1, and also plays a role of attaching the attaching plate to the semiconductor wafer 1. The wax removal cleaning is performed by immersing the wafer in an organic alkali cleaning liquid.
[0024]
After the wax removal cleaning, the cleaved surfaces 1c of the 20 semiconductor wafers 1 were inspected under a microscope at a magnification of 50 times, and no chipping was observed. In addition, using a laser microscope, three plane sags were examined at both ends and the center of a portion where the cleavage plane 1c and the front and back surfaces 1a and 1b of the 20 semiconductor wafers 1 intersected. As a result, the cleavage plane 1c was not chamfered. The semiconductor wafer 1 has the same shape as that of the semiconductor wafer 1, and the chamfered portions 1d and 1e have been completely removed.
[0025]
As described above, according to the first embodiment of the present invention, the front side corner portion where the cleavage plane 1c formed on the outer periphery of the semiconductor wafer 1 and the front and back surfaces 1a and 1b of the semiconductor wafer 1 intersect, Since the chamfer is applied to the back side corners, it is possible to prevent chipping from occurring at a portion where the cleavage plane 1c intersects the front and back surfaces 1a and 1b when the front and back surfaces 1a and 1b of the semiconductor wafer 1 are wrapped. Can be. As a result, it is possible to determine the crystal orientation of the semiconductor wafer 1 and perform the alignment with high accuracy.
[0026]
Further, since the chamfering depth is set to the lapping depth of the front and back surfaces 1a and 1b, it is possible to prevent chipping from occurring at a portion where the cleavage surface 1c intersects with the front and back surfaces 1a and 1b due to too small chamfering. Can be. Conversely, it is possible to prevent a situation where the chamfering is too large and the flatness of the cleavage plane 1c is out of order, thereby lowering the accuracy of alignment of the semiconductor wafer 1.
[0027]
In the first embodiment described above, the example in which the chamfered portions 1d and 1e are formed up to the lapping depth has been described. However, the chamfered portions 1d and 1e may be formed up to the primary polishing depth and the final polishing depth.
[0028]
[Second embodiment]
A second embodiment of the method for processing a semiconductor wafer according to the present invention will be described with reference to the flowchart of FIG.
[0029]
First, in step S8, a GaAs single crystal is sliced to form a semiconductor wafer 3 as shown in FIGS. 6 (a) and 6 (b). Note that the two-dot chain line shown in FIG. 6B indicates a wrapping margin.
[0030]
Next, in step S9, the semiconductor wafer 3 is immersed in an etchant and etched to remove a work-affected layer during slicing of the GaAs single crystal.
[0031]
Next, in step S10, the semiconductor wafer 3 is set in a double-sided lapping machine, and the front and back surfaces 3a and 3b are wrapped to a predetermined depth.
[0032]
Next, in step S11, the front surface 3a or the back surface 3b of the semiconductor wafer 3 is scratched with a diamond pen to form a cleavage plane 3c as shown in FIGS. 7A and 7B.
[0033]
Next, in step S12, using a chamfering mill, rounding chamfering is performed on the front side corner and the back side corner of the outer peripheral portion of the semiconductor wafer 3 other than the cleavage plane 3c. , 3b and the cleaved surface 3c are chamfered with smaller roundness than the chamfer of the outer peripheral portion of the semiconductor wafer 3 other than the cleaved surface 3c. Then, a semiconductor wafer 3 having chamfered portions 3d and 3e as shown in FIGS. 8A and 8B is obtained.
[0034]
Next, in step S13, the semiconductor wafer 3 is immersed in an etchant and etched to remove a damaged layer during chamfering.
[0035]
Finally, in step S14, the semiconductor wafer 3 coated with wax is applied on the entire surface of the attaching plate having a flat surface which is finished with high precision, and the semiconductor wafer 3 is subjected to primary polishing and final polishing. Separate and perform wax removal cleaning.
[0036]
As described above, according to the second embodiment of the present invention, since the cleavage plane 3c is formed after lapping the front and back surfaces 3a and 3b of the semiconductor wafer 3, the cleavage plane 3c of the semiconductor wafer 3 and the surface of the semiconductor wafer 3 Chipping can be prevented from occurring at the corner formed by the back surfaces 3a and 3b. As a result, it is possible to determine the crystal orientation of the semiconductor wafer 3 and perform alignment with high accuracy.
[0037]
Further, after the chamfering is performed on the front side corners and the back side corners, which are portions where the cleavage plane 3c intersects the front and back surfaces 3a and 3b, the front and back surfaces 3a and 3b are finally polished. Since the processing amount is smaller and the grinding resistance is smaller than that, the occurrence of chipping can be suppressed.
[0038]
In the above-described second embodiment, an example has been described in which the chamfered portions 3d and 3e are formed up to the final polishing depth. However, the chamfered portions 3d and 3e may be formed up to the primary polishing depth.
[0039]
Further, in the first and second embodiments described above, the example in which the chamfered portions 1d, 1e, 3d, and 3e are rounded has been described. In short, any shape that can suppress the occurrence of chipping may be used.
[0040]
【The invention's effect】
As described above, according to the present invention, chamfering is performed on the front side corner and the back side corner, which are portions where the cleavage plane formed on the outer periphery of the semiconductor wafer and the front and back surfaces of the semiconductor wafer intersect. Therefore, when lapping the front and back surfaces of the semiconductor wafer, it is possible to suppress the occurrence of chipping at the intersection of the cleavage plane and the front and back surfaces. As a result, the determination of the crystal orientation of the semiconductor wafer and the alignment can be performed with high accuracy. Also, since the chamfering depth is taken to be the lapping depth of the front and back surfaces or the final polishing depth, it is possible to prevent the occurrence of chipping at a portion where the cleavage surface and the front and back surfaces intersect because the chamfer is too small. it can. On the other hand, it is possible to prevent the chamfering from being too large and the flatness of the cleavage plane from being out of order, thereby lowering the accuracy of alignment of the semiconductor wafer.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a first embodiment of a method for processing a semiconductor wafer according to the present invention.
FIGS. 2A and 2B are explanatory views showing a semiconductor wafer after slicing a GaAs single crystal, and FIGS. 2A and 2B are a top view and a side view of the semiconductor wafer, respectively.
3A and 3B are explanatory views showing a state after cleavage of the semiconductor wafer of FIG. 2, and FIGS. 3A and 3B are a top view and a side view of the semiconductor wafer, respectively.
FIGS. 4A and 4B are explanatory views showing a state after chamfering of the semiconductor wafer of FIG. 3, and FIGS. 4A and 4B are a top view and a side view of the semiconductor wafer, respectively.
FIG. 5 is a flowchart showing a second embodiment of the method for processing a semiconductor wafer according to the present invention.
FIGS. 6A and 6B are explanatory views showing a semiconductor wafer after slicing a GaAs single crystal, and FIGS. 6A and 6B are a top view and a side view of the semiconductor wafer, respectively.
7A and 7B are explanatory views showing a state after lapping and cleavage of the semiconductor wafer of FIG. 6, and FIGS. 7A and 7B are a top view and a side view of the semiconductor wafer, respectively.
8 is an explanatory view showing a state after chamfering of the semiconductor wafer of FIG. 7, and (a) and (b) are a top view and a side view of the semiconductor wafer, respectively.
[Explanation of symbols]
1,3 Semiconductor wafer 1a, 3a Front surface 1b, 3b Back surface 1c, 3c Cleaved surface 1d, 1e, 3d, 3e Chamfered portion

Claims

Forming a cleavage plane on the outer periphery of the semiconductor wafer, chamfering at least one of a front side and a back side of the cleavage plane of the semiconductor wafer, and at least one of a front side and a back side of the chamfered semiconductor wafer; A method of processing a semiconductor wafer that wraps a semiconductor wafer,
At least one of a front side corner and a back side corner, which is a portion where the cleavage plane formed on the outer periphery of the semiconductor wafer and the front and back surfaces of the semiconductor wafer intersect, the front surface or the back surface of the semiconductor wafer. A method for processing a semiconductor wafer, comprising chamfering to a lapping depth.

Forming a cleavage plane on the outer periphery of the semiconductor wafer, chamfering at least one of a front side and a back side of the cleavage plane of the semiconductor wafer, and at least one of a front side and a back side of the chamfered semiconductor wafer; A method of processing a semiconductor wafer, which is subjected to lapping and further subjected to final polishing,
At least one of a front side corner and a back side corner, which is a portion where the cleavage plane formed on the outer periphery of the semiconductor wafer and the front and back surfaces of the semiconductor wafer intersect, the front surface or the back surface of the semiconductor wafer. A method for processing a semiconductor wafer, comprising chamfering to a final polishing depth.

At least one of the front surface and the back surface of the semiconductor wafer is wrapped, and a cleavage surface is formed on the outer periphery of the wrapped semiconductor wafer, and the front surface side is a portion where the cleavage surface intersects the front and back surfaces of the semiconductor wafer. A method of processing a semiconductor wafer, comprising chamfering the wrapped side of the corner and the back side corner, and further performing final polishing on the wrapped surface of the semiconductor wafer,
The method for processing a semiconductor wafer, wherein the chamfering is performed to a final polishing depth of a front surface or a back surface of the semiconductor wafer.