JP2004199082A - Active matrix substrate, liquid crystal device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To establish inspection technique for an active matrix substrate mounted with a digital driver. <P>SOLUTION: Provided are a digital driver (330) which has a function of placing an output end in a high impedance state and drives a data line and an inspecting circuit (340) which is provided at an end of the data line on the opposite side from the digital driver. The inspecting circuit (340) has two-way switches provided by a plurality of data lines and a control means of controlling opening and closure of the switches. In addition to inspection of breaking of a data line and a digital data driver output, it can be decided whether a spot defect is caused by using the inspecting circuit provided on the opposite side of the data line. Further, the circuit is dedicated to the inspection and can be made small-sized, so that inspecting circuit is arranged in a dead space. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to an active matrix substrate, a liquid crystal device, and an electronic apparatus, and more particularly, to a digital data line driver (inputting a digital signal, performing D / A conversion and outputting an analog signal, (Hereinafter, referred to as a digital driver).

  In recent years, active research has been actively conducted on a driver built-in type active matrix substrate in which a driving circuit (driver) for scanning lines and data lines is formed on a substrate and a liquid crystal display device using the same. Such an active matrix substrate is manufactured using, for example, low-temperature polysilicon technology.

  In order to put a product using the above-described active matrix substrate into the market, it is necessary to accurately inspect non-defective / defective products after forming the substrate and before assembling the panel from the viewpoint of reliability assurance. .

  According to the study of the present inventor, the above-mentioned inspections are roughly classified into basic inspections such as output capability check of a driver itself and detection of disconnection of a data line, characteristics of switching elements (TFT, MIM, etc.) constituting a pixel, and the like. Inspection of a point defect in the active matrix portion such as a leak characteristic of a storage capacitor is required.

  In the case of a digital driver for driving a data line (that is, a digital data line driver), a method of collectively driving at a predetermined timing by paying attention to the easiness of storing (storing) digital data (line sequential driving method) Has been adopted.

  A display device incorporating such a driver for digital line-sequential driving has not been put into practical use at present, and it is unclear how to perform the above-described highly reliable inspection.

  Therefore, one of the objects of the present invention is to establish an inspection technique for an active matrix substrate on which a digital driver is mounted, so that a highly reliable substrate or display device can be put on the market.

An active matrix substrate according to one embodiment of the present invention includes:
Board and
Scanning lines on the substrate,
A data line on the substrate,
Pixels provided corresponding to the intersection of the scanning line and the data line,
An inspection circuit for inspecting the pixel through the data line,
At least a part of the inspection circuit is arranged at a sealing position.

  In the panel process, a position to be sealed by the sealing material is a dead space inevitably generated in the active matrix substrate. An inspection circuit is arranged in this space to effectively use the space.

  In addition, the meaning of the “inspection circuit” is a circuit used for the main purpose of the inspection and does not have a function of driving the data line like a data line driver, and is used for a purpose other than the inspection. It does not exclude the use or use of configurations that can be used for purposes other than inspection.

  In another aspect of the present invention, the transistor of the inspection circuit can be arranged at a sealing position.

  In still another aspect of the present invention, at least a part of the inspection circuit can be arranged in a dead space. No liquid crystal layer is arranged in this dead space.

  In still another embodiment of the present invention, the active matrix substrate can be arranged in a space that does not contribute to realizing essential functions such as image display, that is, a so-called dead space. Therefore, an increase in the size of the active matrix substrate or the liquid crystal display device can be suppressed.

  According to still another aspect of the present invention, the transistor included in the inspection circuit is covered with an insulating film, and a sealing material is disposed on the insulating film.

An active matrix substrate according to still another aspect of the present invention,
Board and
Scanning lines on the substrate,
A data line on the substrate,
A circuit arranged on the substrate, for supplying a signal through at least one of the data line and the scanning line,
The transistor included in the circuit is arranged at a sealing position.

  According to still another aspect of the present invention, the transistor included in the circuit is covered with an insulating film, and a sealing material is provided on the insulating film.

  According to still another aspect of the present invention, the transistor included in the circuit is arranged at a sealing position.

An active matrix substrate according to still another aspect of the present invention,
Board and
A counter substrate facing the substrate,
Scanning lines between the substrate and the counter substrate,
A data line between the substrate and the counter substrate,
Pixels provided corresponding to the intersection of the scanning line and the data line,
An inspection circuit for inspecting the pixel through the data line,
The transistor included in the inspection circuit is covered with an insulating film, and a sealing material for bonding the substrate and the counter substrate is disposed on the insulating film. Here, a liquid crystal layer can be disposed between the substrate and the counter substrate.

An active matrix substrate according to still another aspect of the present invention,
Board and
A counter substrate facing the substrate,
Scanning lines between the substrate and the counter substrate,
A data line between the substrate and the counter substrate,
A circuit for supplying a signal through at least one of the data line and the scanning line,
The transistor included in the circuit is covered with an insulating film, and a sealing material for bonding the substrate and the counter substrate is provided over the insulating film. Here, a liquid crystal layer can be disposed between the substrate and the counter substrate.

  A liquid crystal device and an electronic apparatus according to still another embodiment of the present invention include any one of the above-described active matrix substrates.

  Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment)
(1) Outline of Inspection System and Its Operation FIG. 1 is a diagram showing an entire configuration of an apparatus for executing an active matrix substrate inspection method of the present invention.

  In this embodiment mode, a case where an active matrix substrate (hereinafter, referred to as a TFT substrate) in which a switching element in a pixel portion is formed of a thin film transistor (TFT) is described.

  In FIG. 1, a TFT substrate tester 100 includes a test system controller 10 for overall control of an inspection operation, a timing generator 20 for generating various timing signals, a data generator 30 for outputting inspection data, and a high-speed It has an amplifier and an A / D converter 50, and a data analyzer 50 that performs predetermined analysis by using data output from the A / D converter as an input.

  The fully automatic prober 200 has a prober controller 210 and a DUT board 220 serving as an interface for various signals.

  In addition, the TFT substrate 300 includes an active matrix unit, a scanning line driver 320, a digital data line driver with an output off function (hereinafter, simply referred to as a digital data line driver) 330, and an inspection circuit 340. Note that the output off function is a function that can force the output to a high impedance state. At the time of inspection, a probe (inspection terminal, not shown in FIG. 1) of the fully automatic prober is connected to a predetermined exposed terminal (not shown in FIG. 1) of the TFT substrate 300.

  Then, under the overall control of the test system controller 10, a timing signal and inspection data are output from the timing generator 20 and the data generator 30 in the TFT substrate tester 100. These are sent to the TFT substrate 300 via the DUT board 220 of the fully automatic prober 200.

  The timing signal is input to the scanning line driver 320, the digital data line driver 330, and the inspection circuit 340 in the TFT substrate 300, respectively, and the inspection data is input to the digital data line driver 330.

  After a predetermined inspection process (the details of the inspection operation will be described later), the inspection circuit 340 outputs an obtained analog signal (hereinafter, referred to as a basic signal) which is a basis of the inspection. Is sent to the TFT tester 100 via the DUT board 220 in the full auto prober 200. Then, the data is amplified and A / D-converted by a high-speed amplifier and A / D converter 50 in the TFT tester 10, and the converted data is input to the data analyzer 50, where a predetermined analysis is performed.

(2) Outline of Circuit Configured on TFT Substrate 300 FIG. 2 shows a specific configuration example of the TFT substrate 300 shown in FIG. In order to enable the inspection using the inspection system shown in FIG. 1, the TFT substrate 300 also needs to have some requirements.

  That is, it is an essential requirement that the digital data line driver has an output off function (a function of setting an output to a high impedance state) and that each pixel portion has a capacitance in a substrate state.

  As shown in FIG. 2, the digital data line driver 330 built in the TFT substrate 300 includes an m-bit shift register 400, u-bit data input terminals (D1 to Du, and u × m switches SW1 to SW1). SWum, u × m-bit latch A (reference number 410) and latch B (reference number 420), and an m-bit D / A converter 430. In the present embodiment, the D / A converter 430 outputs It has an off function.

  Further, the scanning line driver 320 includes an n-bit shift register 322.

The active matrix section includes a plurality of data lines X1 to Xm, a plurality of scanning lines Y1 to Yn, a TFT (M1) disposed at an intersection of each scanning line and each data line, and a storage capacitor ( (Storage capacity) C _S1 . The presence of the storage capacitor _CS1 enables measurement of point defects in the substrate state.

In a state of the TFT substrate is not present liquid crystal capacitance C _LC, for convenience and for ease of understanding, FIG. 2, are described the liquid crystal capacitance C _LC. The other end of the storage capacitor _CS1 opposite to the connection end with the TFT (M1) is held at the common potential _VCOM .

(3) Specific Configuration Example (3-1) Configuration of Storage Capacitance Unit FIGS. 9A and 9B show a configuration of one pixel of the active matrix unit of FIG.
FIG. 9A shows a layout configuration, and FIG. 9B shows an equivalent circuit thereof. FIG. 30A shows a cross-sectional structure of the device along the line AA in FIG. 9A.

  In FIG. 9A, reference numbers 5000 and 5100 indicate scanning lines, and reference numbers 5200 and 5300 indicate data lines. Reference numeral 5400 is a capacitance line, and reference numeral 5500 is a pixel electrode.

As is clear from FIG. 30A, the gate insulating film 5510 is formed between the extension 5505 of the drain of the TFT and the capacitor line 5400 formed simultaneously by using the process of forming the scanning line (gate electrode) 5000. The same insulating film 5520 is formed, and an interlayer insulating film 5530 is formed between the capacitor line 5400 and the pixel electrode 5500, and these constitute a storage capacitor (C _S1 ) 5410. Reference numeral 5600 denotes an opening (a region through which light passes), and K1 and K2 denote contact regions.

Note that the storage capacitor (C _S1 ) can also be formed by a configuration as shown in FIGS. FIG. 30 (b) shows a cross-sectional structure of the device along the line AA in FIG. 10 (a).

  In FIG. 9, the capacitor line is provided separately, but in FIG. 10, the storage capacitor is formed by overlapping the extension of the drain of the TFT with the adjacent scanning line (gate electrode).

  That is, as shown in FIGS. 10A and 30B, the same insulating film 5130 as the gate insulating film 5120 is provided between the drain extension portion 5700 made of polysilicon and the adjacent scanning line (gate electrode) 5100. Are formed, and an interlayer insulating film 5140 is formed between the adjacent scanning line 5100 and the pixel electrode 5500, thereby forming a storage capacitor 5420. In FIG. 10A, the same parts as those in FIG. 9A are denoted by the same reference numerals.

(3-2) Configuration of D / A Converter As the m-bit D / A converter 430 in FIG. 2, those having the configuration shown in FIGS. 11 to 14 can be used.

  When performing a point defect inspection, it is necessary to turn off the output of the D / A converter after writing a signal to the capacitance of the pixel portion. Therefore, each of the D / A converters in FIGS. It has an output off function (a function of setting the output to a high impedance state). Hereinafter, a specific description will be given.

D / A Converter of Capacity Division Method The D / A converter 430 in FIG. 11 is a D / A converter of the capacity division method with an output off function. This converter stores charges in weighted capacitances (binary load capacitances) C1 to C8, and when the 8-bit input data D1 to D8 is "1", the corresponding switches (SW20 to SW28) To cause a charge transfer between each weighted capacitance (C1 to C8) and the coupling capacitance C30, and generate a conversion voltage corresponding to the 8-bit input data D1 to D8 at the output terminal _VOUT . It is to let. In FIG. 11, switches (SW1 to SW8) are reset switches for the capacitors C1 to C8, and V0 is a reset voltage. The switch C40 is a reset switch for the coupling capacitance C30.

The switch control circuit 6000 is provided for forcibly opening the switches SW20 to SW28 to bring the output terminal _VOUT into a floating state (high impedance state).

  FIG. 12 shows a specific configuration of the switch SW20. The switch SW20 includes a transfer gate including an nMOS transistor M10, a pMOS transistor M20, and an inverter INV1, and an nMOS transistor M30 connected in series to the transfer gate. The switch control circuit 6000 turns the output corresponding to the input data D1 into a high impedance state by turning off the nMOS transistor M30. Similarly, other switches corresponding to other input data can be set to the high impedance state.

  11 and 12, the switch control circuit 6000 is provided independently, and in FIG. 12, a dedicated transistor (M30) for providing high impedance is provided. However, the present invention is not limited to this. For example, in FIGS. 11 and 12, the input data D1 to D8 are forcibly fixed to “0” using a reset signal or the like, so that the switch (SW20) in FIG. 11 and the transfer gates (M10 and M20) in FIG. ) Can be turned off to bring the output into a high impedance state.

D / A Converter of Resistance Dividing Method The D / A converter 430 shown in FIG. 13 selects a divided voltage obtained from each common connection point of the serially connected resistors R1 to R8 by controlling the opening and closing of the switches SW100 to SW108. Then, the converted output V _OUT is obtained.

  Opening / closing of the switches SW100 to SW108 is determined by the output of the decoder 7000. The switches SW100 to SW108 (switch group 7100) are collectively opened under the control of the switch control circuit 7200, so that the output can be brought into a high impedance state.

PWM D / A Converter The D / A converter 430 shown in FIG. 14 generates a pulse signal having a pulse width corresponding to the input data value by the PWM circuit 7502, and uses the pulse width to turn on (close) the switch 7506. (The time it takes to be in a state) to obtain a converted output _VOUT . Reference numeral 7504 denotes a ramp wave power supply, and reference numeral 7400 denotes a latch circuit for temporarily storing image data. Further, under the control of the switch control circuit 7508, the switch 7506 can be forcibly opened and the output can be set to a high impedance state.

(3-3) Configuration of Inspection Circuit As the inspection circuit 340 in FIG. 2, those shown in FIGS. 15A, 15B and 16 can be used. The term “inspection circuit” means that it is used for inspection and is not intended to drive the data lines unlike a data line driver, and includes a configuration used for other purposes and the entire circuit. It does not exclude the use of for other purposes.

The test circuit 342 of FIG. 15A is provided with analog switches SW _{X1 to} SW _Xm using MOS transistors corresponding to the data lines _{X1 to Xm} , respectively. The analog switches SW _{X1 to} SW _Xm are connected to the shift register 7600. Are scanned in a dot-sequential manner by the output of the above, and basic signals serving as a basis of the inspection are sequentially obtained from an output terminal _TOUT . The base signal is sent to the DUT board 220 in the fully automatic prober 200.

In FIG. 15B, two analog switches (SW _{X1 to} SW _Xm ) are driven by one output of the shift register 7602, and a point-sequential scanning method is basically employed. This is common with FIG. Since the two analog switches are simultaneously driven, the number of bits (the number of stages) of the shift register can be m / 2 bits. The basic signal is obtained from two terminals T _OUT1 and T _OUT2 .

The inspection circuit 342 in FIG. 16 employs a method different from the point sequential scanning. That is, when driving the m analog switches SW _{X1 to} SW _Xm , the p analog switches are collectively driven and the driving is repeated q times, so that a total of m switches (m = p × q) This is a method for driving the analog switch.

  The switch control circuit 7300 sequentially turns on the control lines G1 to Gq, and obtains a basic signal from each of the output lines L1 to Lp simultaneously each time each control line is turned on once.

  Each of the inspection circuits described above does not require the driving capability of the data line and does not require a high-speed drive for image display, so that the transistor size may be small, and basically, it can operate. All you need is the minimum ability. Therefore, the occupied area can be made extremely small, and it can be formed on the TFT substrate.

  FIG. 3 shows the size of the MOS transistor in the output stage of the D / A converter and the size of the MOS transistor forming the inspection circuit 342 when the D / A converter 430 is a driver that can also perform point-sequential driving. It is a figure shown in comparison.

That is, the channel width (W) of the MOS transistor M ₂₀₀ forming the D / A converter 430 that can also perform the dot sequential driving needs to be at least 1000 μm or more, whereas the channel width of the MOS transistor M ₃₀₀ forming the inspection circuit 342 is required. The width (W) may be 100 μm or less. That is, the size of the transistor of the inspection circuit may be 1/10 or less.

  As described above, since the size of the transistor is small and the occupied area is small, at least a part of the inspection circuit 342 is provided in a space that does not contribute to realization of an essential function such as image display of the TFT substrate, that is, a so-called dead space. It is also possible to arrange them. Accordingly, the size of the TFT substrate or the liquid crystal display device can be suppressed from increasing.

  For example, as shown in FIG. 4, the inspection circuit 342 can be disposed at a sealing position by a sealing material (sealant) in a TFT substrate panel process. FIG. 4 illustrates a cross-sectional configuration of a completed liquid crystal display device for easy understanding.

In FIG. 4, reference numeral 500 denotes a glass substrate, reference numeral 510 denotes an SiO ₂ film, reference numeral 520 denotes a gate insulating film, reference numerals 530 and 540 denote interlayer insulating films, and reference numerals 522 and 524. Is a source / drain layer, and reference numeral 526 is a gate electrode.

The MOS transistor M ₃₀₀ that forms the inspection circuit is disposed in a sealing area A <b> 1 with a sealing material (sealant) 550. The sealing position by the sealing material is a dead space inevitably generated in the active matrix substrate. By arranging the inspection circuit in this space, the space can be effectively utilized.

  In FIG. 4, reference numeral 560 indicates an opposite substrate, reference numerals 570 and 572 indicate alignment films, and reference numeral 574 indicates liquid crystal.

(4) Inspection Procedure of TFT Substrate (4-1) Outline As shown in FIG. 5, the inspection of the TFT substrate is roughly divided into a signal line disconnection detection and a D / A converter output inspection step (preliminary inspection step). , Step 600) and a point defect inspection process (step 610).

  The detection of the disconnection of the signal line and the inspection of the output of the D / A converter (Step 600) are basically the same as those of the active matrix substrate (FIGS. 1 and 2) in that an inspection circuit is provided to face the digital data line driver. This is a test that can be performed by a typical configuration. By turning on all outputs of the digital data line driver 330 shown in FIGS. 1 and 2 and receiving the output by the test circuit 340, in principle, it is possible to perform one scan. It can be easily inspected.

  For example, if no output signal of the data line driver is transmitted via the data line, the data line is disconnected or the data line driver itself is defective. The point defect inspection process (step 610) will be described later.

(4-2) Specific Inspection Procedure FIG. 6 shows an example of a specific inspection procedure.

  In the flowchart of FIG. 6, a method is adopted in which inspection is performed in ascending order of inspection time, and all necessary steps are inspected. However, the present invention is not limited to this, and the subsequent inspection can be stopped when a defect is found.

  Hereinafter, the inspection procedure of FIG. 6 will be described in order.

  First, the presence or absence of an uninspected TFT substrate is checked (step 700). If there is an uninspected TFT substrate, the substrate is aligned (attached) to the system of FIG. 1 (step 710), and the full auto prober 220 of FIG. Probing is performed (step 720).

  Then, first, the driver current consumption is measured (step 730). In this step, it is determined whether or not the current consumption flowing through the power supply of the data line and the scanning line driver (and the inspection circuit) is within a normal range. If there is a short circuit between the power supplies, an excessive current flows, so that the determination can be made.

  Next, the end pulse of the scanning line driver is measured (step 740). That is, a pulse is input to the first stage of the shift register, and it is determined whether the pulse is output from the last stage at a predetermined timing. Since it is a digital signal, it can be determined instantaneously.

  Next, the end pulse of the data line driver is measured as in the case of the scanning line driver (step 750).

  Next, a short circuit inspection of the data lines (signal lines) and the scanning lines is performed (step 760).

  That is, all the outputs of the scanning driver are set to the high level, and the switches of the inspection circuit are also turned on, and the current flowing from the scanning line driver to the inspection circuit is measured. If there is a short circuit between the wires, an excessive current will flow.

  Next, disconnection inspection of data lines (signal lines) and scanning lines is performed (step 770).

  That is, all outputs of the digital driver are set to a high level, and switches of the inspection circuit are closed in order to detect a change in current. If there is a disconnection, the flowing current decreases, so that it is possible to make a determination.

  Next, the output of the D / A converter is measured (step 780).

  Before inspecting a point defect, an inspection is performed on all outputs of the D / A converter. In this inspection, in order to increase the accuracy, it is desirable to check whether or not the output levels of signals of a plurality of gradations such as white, black, and halftone are appropriate.

  Specifically, a voltage of a set level is output to all data lines (signal lines), and after a certain period of time, the output of the D / A converter is set to a high impedance state. The voltage of is detected.

  Next, a point defect is measured (step 790).

  More specifically, the measurement of the point defect is performed by a procedure as shown in FIG. That is, first, all outputs of the digital data line driver are turned on, a voltage of a set level is output to all data lines (signal lines), and a signal is written to the storage capacitor of the pixel portion (step 900). Next, the output of the D / A converter of the digital data line driver is set to a high impedance state (step 910). Next, scanning lines are selected one by one while the switch of the inspection circuit is closed, and the amount of change in potential for each pixel is detected (step 920). Then, if necessary, a plurality of detections (step 930) and detections with different writing conditions (step 940) are executed.

  If an abnormality (defective) is found in each of the above steps, a defective address is detected as necessary and used as basic data for quality determination (step 800 in FIG. 6).

  Since the basic data serving as the basis of the inspection has been obtained by the above steps, finally, the pass / fail judgment is comprehensively performed based on the basic data (step 810 in FIG. 6).

  For example, as shown in FIG. 8, the pass / fail judgment is made by examining the two-dimensional distribution of the basic data on the TFT substrate surface and examining whether there is a location (singular point) showing an extremely different numerical value with respect to the surroundings. (Step 960), an abnormality is examined by comparing with the sample data (Step 970), and the like is comprehensively determined.

  Then, the above-described inspection process is sequentially performed on the other untested chips (steps 820 and 830 in FIG. 6).

  As described above, according to the present embodiment, a non-defective inspection of an active matrix substrate on which a digital data line driver is mounted can be performed with high accuracy in a short time.

(Second embodiment)
A second embodiment of the present invention will be described with reference to FIG.

  The feature of the present embodiment is that the digital data line driver and the inspection circuit are arranged vertically in two parts, and furthermore, the vertically divided circuits are arranged so as to be intricate with each other, resulting in a compact configuration. is there.

  That is, as clearly shown in FIG. 17, the digital data line driver is divided into a first driver 8000A and a second driver 8000B. The configuration of the data line driver itself is the same as that of FIG. 2, but the number of bits of each driver is と な っ that of FIG.

  The inspection circuit is also divided into a first circuit 8100A and a second circuit 8100B. The first circuit 8100A is connected to even-numbered data lines (X2, X4... Xm), and the second circuit 8100B is connected to odd-numbered data lines (X1, X3. 1) is connected. In FIG. 17, reference numerals S1, S2, S3, S4, Sm, and Sm-1 indicate analog switches, and reference numerals 8102 and 8104 indicate the configuration of one stage of the shift register.

  By dividing the driver and the test circuit as in the present embodiment, the following various effects can be obtained.

  That is, by dividing the driver and the test circuit, the number of elements constituting each circuit is reduced to 、, so that the occupied area is reduced and the elements can be arranged with a margin.

  Further, the operating frequency can be reduced to half by halving the number of stages of the shift register, which is advantageous in circuit design.

  Further, the division of the circuit leads to the fact that the circuit can be arranged evenly around the pixel portion, thereby making it possible to effectively use the dead space. For example, it is advantageous when utilizing the dead space immediately below the sealing material (sealing material) described in FIG.

  That is, the sealing material (sealant) is provided so as to contact the periphery of the substrate with a uniform width so as not to apply extra stress to the substrate. This is because the reduction in the number of elements helps to increase the efficiency of using the dead space immediately below the sealing material.

  In particular, since the element size of the inspection circuit is smaller than the element size of the driver, the division of the inspection circuit further saves space, which is advantageous in layout design.

  FIG. 19 shows an arrangement example of an inspection circuit and the like on an active matrix substrate (on a TFT substrate). FIG. 19 shows not only the layout of the driver and the like on the active matrix substrate but also a vertical section and a horizontal section of a liquid crystal panel manufactured using the TFT substrate.

  In FIG. 19, reference numeral 9100 is an active matrix substrate (TFT substrate), reference numerals 8000A and 8000B are digital data line drivers and inspection circuits, and reference numeral 320 is a scanning line driver. Reference numeral 8300 denotes a light-shielding pattern, and the inside of the pattern is an active matrix portion (pixel portion). Reference numeral 8400 denotes a mounting terminal portion, reference numeral 9200 denotes a sealing material (sealant), reference numeral 574 denotes a liquid crystal, and reference numeral 9000 denotes a counter substrate (color filter substrate).

  As is apparent from FIG. 19, the scanning line driver, the data line driver, and the inspection circuit are all arranged by effectively utilizing the dead space around the active matrix substrate. Therefore, it is suitable for effectively utilizing the dead space at the sealing position by the sealing material.

  The liquid crystal panel (active matrix substrate 9100) shown in FIG. 19 is manufactured through, for example, a cutting process as shown in FIG.

  That is, in FIG. 18, six panels are manufactured by bonding an active matrix substrate (TFT substrate) 9100 and a counter substrate (color filter substrate) 9000 by a large-size bonding method and then cutting. In FIG. 18, cutting lines (L10, L11, L30, L31, L32, L33) indicated by alternate long and short dash lines are lines for simultaneously cutting the active matrix substrate and the counter substrate. In addition, cutting lines (L20, L21, shown by dotted lines) are lines that cut only the opposing substrate.

(Third embodiment)
In this embodiment, a method for manufacturing a thin film transistor (TFT) on an active matrix substrate (a manufacturing method using low-temperature polysilicon technology) will be described with reference to FIGS.

  In the manufacturing process shown in FIGS. 20 to 26, the capacitance (capacitor) is also manufactured. Therefore, this process can be used not only for manufacturing the inspection circuit and the shift register of the driver, but also for manufacturing the D / A converter of the capacitance division type shown in FIG.

Step 1
First, as shown in FIG. 20, a buffer layer 4100 is provided over a substrate 4000, and an amorphous silicon layer 4200 is formed over the buffer layer 4100.

Step 2
Next, as shown in FIG. 21, the entire surface of the amorphous silicon layer 4200 is irradiated with laser light and annealed to polycrystallize the amorphous silicon to form a polycrystalline silicon layer 4220.

Step 3
Next, as shown in FIG. 22, the polycrystalline silicon layer 4220 is patterned to form island regions 4230, 4240, and 4250. The island regions 4230 and 4240 are layers in which active regions (source and drain) of the MOS transistor are formed. The island region 4250 is a layer that becomes one pole of the thin film capacitor.

Step 4
Next, as shown in FIG. 23, a mask layer 4300 is formed, and phosphorus (P) ions are implanted only into the island region 4250 to reduce the resistance.

Step 5
Next, as shown in FIG. 24, a gate insulating film 4400 is formed, and TaN layers 4500, 4510, and 4520 are formed on the gate insulating film. The TaN layers 4500 and 4510 are layers serving as gates of the MOS transistors, and the TaN layer 4520 is a layer serving as the other pole of the thin film capacitor. After that, a mask layer 4600 is formed, and phosphorus (P) is ion-implanted by self-alignment using the gate TaN layer 4500 as a mask to form an n-type source layer 4231 and a drain layer 4232.

Step 6
Next, as shown in FIG. 25, mask layers 4700a and 4700b are formed, and using the gate TaN layer 4510 as a mask, boron (B) is ion-implanted in a self-aligned manner to form a p-type source layer 4241 and a drain layer 4242. Form.

Step 7
Thereafter, as shown in FIG. 26, an interlayer insulating film 4800 is formed, a contact hole is formed in the interlayer insulating film, and then electrode layers 4900, 4910, 4920, and 4930 made of ITO or Al are formed. Although not shown in FIG. 26, electrodes are also connected to the TaN layers 4500, 4510, 4520 and the polycrystalline silicon layer 4250 via contact holes. Thus, an n-channel TFT, a p-channel TFT and a MOS capacitor are completed.

  By using the above-described manufacturing process in which the steps are made common, the manufacturing is facilitated and the cost is advantageous. Polysilicon has much higher carrier mobility than amorphous silicon, so high-speed operation is possible, which is advantageous in terms of speeding up circuits.

  Then, since the non-defective product is reliably determined using the above-described inspection method, the reliability of the completed product can be extremely high, and therefore, a high-quality product can be put on the market.

  Although the low-temperature polysilicon TFT technology is used in the above-described manufacturing process, the manufacturing method is not necessarily limited to this. For example, if a predetermined operation speed of the circuit is guaranteed, a process using amorphous silicon can be used. Further, as a switching element in the pixel portion, a two-terminal element such as an MIM can be used in addition to the TFT.

(Fourth embodiment)
In this embodiment, examples of a liquid crystal panel manufactured using the active matrix substrate of the present invention and an electronic device using the panel and the like will be described. All are high quality devices.

(1) Liquid crystal display device (FIG. 27)
The liquid crystal display device includes, for example, a backlight 2000, a polarizing plate 2200, a TFT substrate 2300, a liquid crystal 2400, a counter substrate (color filter substrate) 2500, and a polarizing plate 2600, as shown in FIG. In this embodiment, as described above, the driver circuit 2310 (and the inspection circuit) is formed over the TFT substrate 1300.

(2) Personal computer (Fig. 28)
A personal computer 1200 illustrated in FIG. 28 includes a main body 1204 having a keyboard 1202, and a liquid crystal display screen 1206.

(3) Liquid crystal projector (Fig. 29)
A liquid crystal projector 1100 shown in FIG. 29 is a projection type projector using a transmissive liquid crystal panel as a light valve, and uses, for example, a three-plate prism type optical system.

  Referring to FIG. 29, in a projector 1100, projection light emitted from a lamp unit 1102 of a white light source is divided into three primary colors of R, G, and B by a plurality of mirrors 1106 and two dichroic mirrors 1108 inside a light guide 1104. Then, the liquid crystal is guided to three liquid crystal panels 1110R, 1110G, and 1110B that display images of the respective colors. The light modulated by the respective liquid crystal panels 1110R, 1110G, and 1110B is incident on the dichroic prism 1112 from three directions. In the dichroic prism 1112, the red R and blue B lights are bent by 90 ° and the green G light goes straight, so that the images of the respective colors are synthesized, and a color image is projected on a screen or the like through the projection lens 1114.

  Other electronic devices to which the present invention can be applied include an engineering workstation (EWS), a pager or a mobile phone, a word processor, a television, a viewfinder type or a monitor direct view type video tape recorder, an electronic organizer, an electronic desk calculator, and a car. Examples include a navigation device, a POS terminal, and a device having a touch panel.

FIG. 1 is a diagram showing an entire configuration of an apparatus for executing an example of an active matrix substrate inspection method of the present invention. FIG. 2 is a diagram illustrating a configuration example of a circuit mounted on an active matrix substrate of the present invention. FIG. 3 is a diagram schematically illustrating a size of a transistor forming a D / A converter in FIG. 2 and a size of a transistor forming a test circuit; FIG. 4 is a cross-sectional view of a main part of a liquid crystal display device, showing an example in which an inspection circuit is arranged below a sealing material. 1 is a flowchart showing an outline of an embodiment of an active matrix substrate inspection method according to the present invention. 4 is a flowchart for explaining more specific contents of an embodiment of the active matrix substrate inspection method of the present invention. 7 is a flowchart more specifically showing the details of point defect measurement in FIG. 6. 7 is a flowchart more specifically showing the content of the necessity determination in FIG. 6. (A) is a plan view showing an example of a configuration of one pixel of the active matrix section, and (b) is an equivalent circuit diagram of (a). (A) is a plan view showing another example of the configuration of one pixel of the active matrix section, and (b) is an equivalent circuit diagram of (a). FIG. 2 is a diagram for explaining an outline of a configuration example of a capacity division D / A converter usable in the present invention. FIG. 12 is a diagram illustrating a circuit configuration example of a main part of the D / A converter of the capacitance division type in FIG. 11. FIG. 2 is a diagram for describing an outline of a configuration example of a resistance division type D / A converter that can be used in the present invention. FIG. 2 is a diagram for describing an outline of a configuration example of a PWM type D / A converter that can be used in the present invention. (A), (b) is a figure for each explaining the outline | summary of an example of the test circuit shown in FIG. 1, FIG. FIG. 3 is a diagram for describing an outline of another example of the configuration of the test circuit illustrated in FIGS. 1 and 2. FIG. 11 is a diagram illustrating another configuration example of a circuit mounted on the active matrix substrate of the present invention. It is a figure showing a position at the time of cutting a glass substrate for manufacture of an active matrix substrate. FIG. 3 is a diagram illustrating an example of a layout of a scanning line driving circuit, a data line driving circuit, an inspection circuit, and the like. It is a figure showing the 1st process of an example of the manufacturing method of the active matrix substrate of the present invention. It is a figure showing the 2nd process of an example of the manufacturing method of the active matrix substrate of the present invention. It is a figure showing the 3rd process of an example of the manufacturing method of the active matrix substrate of the present invention. It is a figure showing the 4th process of an example of the manufacturing method of the active matrix substrate of the present invention. It is a figure showing the 5th process of an example of the manufacturing method of the active matrix substrate of the present invention. It is a figure showing the 6th process of an example of the manufacturing method of the active matrix substrate of the present invention. It is a figure showing the 7th process of an example of the manufacturing method of the active matrix substrate of the present invention. FIG. 2 is a diagram illustrating a configuration of a liquid crystal display device using the active matrix substrate of the present invention. 1 is a diagram illustrating a configuration of an example of an electronic device (laptop computer) using an active matrix substrate of the present invention. FIG. 14 is a diagram illustrating a configuration of another example (a liquid crystal projector) of an electronic device using the active matrix substrate of the present invention. 10A is a diagram showing a cross-sectional structure of the device shown in FIG. 9A along line AA, and FIG. 10B is a cross-sectional structure of the device shown in FIG. 10A along line AA. FIG.

Explanation of reference numerals

10 test system controller, 20 timing generator,
30 data generator, 40 high-speed amplifier, A / D converter,
100 active matrix substrate tester, 200 full auto prober,
210 prober controller, 220 DUT board,
300 active matrix substrate, 310 active matrix section,
320 scanning line driver, 330 digital data line driver with output off function,
340 inspection circuit

Claims (15)

Board and
Scanning lines on the substrate,
A data line on the substrate,
Pixels provided corresponding to the intersection of the scanning line and the data line,
An inspection circuit for inspecting the pixel through the data line,
An active matrix substrate, wherein at least a part of the inspection circuit is arranged at a sealing position. Board and
Scanning lines on the substrate,
A data line on the substrate,
Pixels provided corresponding to the intersection of the scanning line and the data line,
An inspection circuit for inspecting the pixel through the data line,
An active matrix substrate, wherein the transistor of the inspection circuit is arranged at a sealing position. Board and
Scanning lines on the substrate,
A data line on the substrate,
Pixels provided corresponding to the intersection of the scanning line and the data line,
An inspection circuit for inspecting the pixel through the data line,
An active matrix substrate, wherein at least a part of the inspection circuit is arranged in a dead space. The active matrix substrate according to claim 3,
An active matrix substrate, wherein a liquid crystal layer is not disposed in the dead space. Board and
Scanning lines on the substrate,
A data line on the substrate,
Pixels provided corresponding to the intersection of the scanning line and the data line,
An inspection circuit for inspecting the pixel through the data line,
An active matrix substrate, wherein at least a part of the inspection circuit is arranged in a dead space that does not contribute to image display. Board and
Scanning lines on the substrate,
A data line on the substrate,
Pixels provided corresponding to the intersection of the scanning line and the data line,
An inspection circuit for inspecting the pixel through the data line,
An active matrix substrate, wherein a transistor included in the inspection circuit is covered with an insulating film, and a sealing material is provided on the insulating film. Board and
Scanning lines on the substrate,
A data line on the substrate,
A circuit arranged on the substrate, for supplying a signal through at least one of the data line and the scanning line,
An active matrix substrate, wherein a transistor included in the circuit is arranged at a sealing position. Board and
Scanning lines on the substrate,
A data line on the substrate,
A circuit arranged on the substrate, for supplying a signal through at least one of the data line and the scanning line,
An active matrix substrate, wherein a transistor included in the circuit is covered with an insulating film, and a sealing material is provided over the insulating film. Board and
Scanning lines on the substrate,
A data line on the substrate,
Pixels provided corresponding to the intersection of the scanning line and the data line,
A circuit arranged on the substrate, for supplying a signal to the pixel through at least one of the data line and the scanning line,
An active matrix substrate, wherein a transistor included in the circuit is arranged at a sealing position. Board and
A counter substrate facing the substrate,
Scanning lines between the substrate and the counter substrate,
A data line between the substrate and the counter substrate,
Pixels provided corresponding to the intersection of the scanning line and the data line,
An inspection circuit for inspecting the pixel through the data line,
An active matrix substrate, wherein a transistor included in the inspection circuit is covered with an insulating film, and a sealing material for bonding the substrate and the counter substrate is disposed on the insulating film. The active matrix substrate according to claim 10,
An active matrix substrate, wherein a liquid crystal layer is disposed between the substrate and the counter substrate. Board and
A counter substrate facing the substrate,
Scanning lines between the substrate and the counter substrate,
A data line between the substrate and the counter substrate,
A circuit for supplying a signal through at least one of the data line and the scanning line,
An active matrix substrate, wherein a transistor included in the circuit is covered with an insulating film, and a sealing material for bonding the substrate and the counter substrate is provided over the insulating film. The active matrix substrate according to claim 12,
An active matrix substrate, wherein a liquid crystal layer is disposed between the substrate and the counter substrate.   A liquid crystal device comprising the active matrix substrate according to claim 1.   An electronic apparatus comprising the liquid crystal device according to claim 14.

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