JP7347614B2 - Electro-optical equipment, electronic equipment - Google Patents

Description

The present invention relates to an electro-optical device and an electronic device.

An example of an electro-optical device is an active drive type liquid crystal device in which a pixel is provided with a transistor as a switching element. In an active drive type liquid crystal device, one substrate on which the above-mentioned transistor is provided and the other substrate, which has a light shielding part called a black matrix (BM) that defines the aperture of the pixel, are placed facing each other with high positional accuracy and bonded together. Therefore, a photocurable sealant is sometimes used instead of a thermosetting sealant. In order to sufficiently cure the photocurable sealant, it is desirable to irradiate the pair of substrates with light from both sides. However, in the sealing area where the sealing material of one of the substrates is placed, there is a light-shielding film for wiring related to driving the transistor, and the incident light is blocked by the light-shielding film, which inhibits the curing of the sealing material. There is a risk.

Therefore, for example, Patent Document 1 proposes a liquid crystal display element that allows light to pass through by providing a slit in a light-shielding film located either directly above or directly below a photocurable sealing material sandwiched between two substrates. ing. According to the above-mentioned Patent Document 1, from the viewpoint of photocuring the sealing material reliably, it is preferable that the width of the light shielding film is 150 μm or less and the opening width is 5 μm or more.

Further, for example, Patent Document 2 discloses that a drive circuit section is provided in a peripheral area located around the image display area of the first substrate and supplies various signals to the pixel section, and a drive circuit section that extends so as to overlap the seal area. a drive power supply line that includes a portion and supplies a power supply potential to the drive circuit portion; a counter electrode potential line that includes a wiring portion that overlaps with the extension portion via an interlayer insulating film and supplies a predetermined potential to the counter electrode; An electro-optical device is disclosed. According to Patent Document 2, a photocurable resin is disposed in the sealing area to form a sealing part, and in order to irradiate the photocuring resin with light from the first substrate side, the extending part and It is shown that gaps are provided in each of the wiring sections.

Japanese Patent Application Publication No. 2000-89235 Japanese Patent Application Publication No. 2007-41346

In Patent Document 1 and Patent Document 2, no specific numerical values are given for the width of the sealing area where the photocurable sealing material is placed, but the reliability of the liquid crystal display element as an electro-optical device is The width of the seal area is an important factor when discussing quality. If the width of the sealing area where the sealing material is placed becomes narrower, this will affect the adhesive strength between the pair of substrates and will also make it easier for moisture etc. to infiltrate from the outside into the liquid crystal layer surrounded by the sealing material. Therefore, it becomes necessary to ensure a predetermined width for the seal area. On the other hand, as shown in Patent Document 2, since not only the sealing material but also the drive circuit section and the like are arranged in the peripheral area outside the image display area, it is necessary to keep the sealing area of a predetermined width. There is a problem in that if the peripheral area is secured to include the electro-optical device, it becomes difficult to miniaturize the electro-optical device.

The electro-optical device of the present application is an electro-optical device in which an electro-optic element is provided between a first substrate and a second substrate that are arranged to face each other with a photocurable sealing material interposed therebetween, and at least a second substrate. The substrate is translucent and has a plurality of light shielding patterns arranged at intervals in a sealing area of the first substrate where the sealing material is arranged, and drives an electro-optical element on the first substrate. The semiconductor layer of the transistor included in the drive circuit for the invention is characterized in that it is arranged to overlap with at least one light-shielding pattern among the plurality of light-shielding patterns in a plan view.

In the above electro-optical device, the first substrate and the second substrate are translucent, and the semiconductor layer includes a light-shielding layer provided in an island shape on the first substrate and one of the plurality of light-shielding patterns. It is preferable that the light shielding pattern is arranged between the light shielding pattern and the light shielding pattern.

In the electro-optical device described above, the transistor may include two transistors in which semiconductor layers are connected in parallel.

Further, in the above electro-optical device, the semiconductor layer of one of the two transistors connected in parallel overlaps one of two adjacent light-shielding patterns among the plurality of light-shielding patterns in a plan view on the first substrate. The other semiconductor layer of the two transistors arranged in parallel and connected in parallel is preferably arranged so as to overlap the other of the two adjacent light shielding patterns in a plan view on the first substrate.

The electro-optical device described above is characterized in that at least one of the plurality of light shielding patterns is a power supply wiring.

In the electro-optical device described above, the electro-optical element is a liquid crystal element, and includes a pixel electrode provided for each pixel on the first substrate, and a common electrode provided on the second substrate to which a common potential is applied. However, at least one of the plurality of light shielding patterns may be a common potential wiring.

An electronic device of the present application is characterized by including the electro-optical device described above.

FIG. 1 is a schematic plan view showing the configuration of a liquid crystal device according to a first embodiment. 2 is a schematic cross-sectional view showing the structure of the liquid crystal device of the first embodiment along the line H-H' shown in FIG. 1. FIG. FIG. 1 is a circuit diagram showing an electrical configuration of a liquid crystal device according to a first embodiment. FIG. 2 is an equivalent circuit diagram showing the configuration of a pixel circuit in the liquid crystal device of the first embodiment. FIG. 3 is a circuit diagram showing the configuration of a first latch circuit. FIG. 3 is a plan view showing the arrangement of each component of the first latch circuit in the seal area. 7 is a cross-sectional view showing the structure of the first latch circuit taken along line A-A' in FIG. 6. FIG. FIG. 2 is a circuit diagram showing the configuration of a shift register. FIG. 3 is a plan view showing the arrangement of each component of the shift register in the seal area. 10 is a cross-sectional view showing the structure of the shift register taken along line B-B' in FIG. 9. FIG. FIG. 3 is a schematic cross-sectional view showing a process of curing a sealing material placed between an element substrate and a counter substrate. FIG. 7 is a plan view showing the arrangement of each component of the first latch circuit in the seal area of the second embodiment. 13 is a cross-sectional view showing the structure of the first latch circuit taken along line CC' in FIG. 12. FIG. FIG. 7 is a schematic diagram showing the configuration of a projection display device as an electronic device according to a third embodiment.

Embodiments of the present invention will be described below with reference to the drawings. Note that in each of the following figures, the portions to be explained are enlarged or reduced as appropriate so that they can be recognized.

(First embodiment)
<Electro-optical device>
The electro-optical device of this embodiment will be described using as an example an active matrix liquid crystal device that includes thin film transistors (TFTs) as switching elements of pixels. This liquid crystal device can be suitably used, for example, as a light modulation means (light valve) of a projection type display device (projector) to be described later.

First, the basic configuration of a liquid crystal device as an electro-optical device of this embodiment will be explained with reference to FIGS. 1 to 4. FIG. 1 is a schematic plan view showing the structure of the liquid crystal device of the first embodiment, FIG. 2 is a schematic cross-sectional view showing the structure of the liquid crystal device of the first embodiment along line HH' shown in FIG. 1, and FIG. A circuit diagram showing the electrical configuration of the liquid crystal device according to the first embodiment. FIG. 4 is an equivalent circuit diagram showing the configuration of a pixel circuit in the liquid crystal device according to the first embodiment.

As shown in FIGS. 1 and 2, the liquid crystal device 100 of this embodiment includes an element substrate 10 and a counter substrate 20 that are arranged to face each other, and a liquid crystal layer 50 sandwiched between these pair of substrates.
The base material 10s of the element substrate 10 and the base material 20s of the counter substrate 20 are each made of a transparent substrate such as a quartz substrate or a glass substrate. The liquid crystal layer 50 is a liquid crystal element that is an example of an electro-optical element in the present invention.

The element substrate 10 is larger than the counter substrate 20, and both substrates are bonded to each other with a gap interposed therebetween via a sealing material 40 disposed along the outer edge of the counter substrate 20. As a method for constructing the liquid crystal layer 50 in the space sealed by the sealing material 40, for example, liquid crystal is dropped inside the sealing material 40 arranged in a frame shape, and the element substrate 10 and the counter substrate 20 are separated under reduced pressure. An example of this is the ODF (One Drop Fill) method in which the two are bonded together.

In this embodiment, the sealing material 40 is an adhesive such as a light (ultraviolet) curing type epoxy resin. A spacer (not shown) is mixed into the sealing material 40 to keep the above-mentioned distance between the pair of substrates constant.

A display area E1 including a plurality of pixels P arranged in a matrix is provided inside the sealing material 40. Further, a parting portion 21 is provided in a peripheral area E2 between the sealing material 40 and the display area E1, surrounding the display area E1. The parting portion 21 is made of, for example, a light-shielding metal or metal oxide. A region surrounding the peripheral region E2 where the parting portion 21 is arranged and in which the sealing material 40 is arranged in terms of design is called a sealing region E3. Note that the display area E1 may include a plurality of dummy pixels in addition to the pixels P that contribute to display. Similarly, the peripheral region E2 may include a plurality of dummy pixels.

A terminal portion 10a in which a plurality of external connection terminals 104 are arranged is provided in a portion of the element substrate 10 that protrudes outward from the counter substrate 20. A flexible circuit board (not shown) for electrical connection with an external drive circuit is mounted on the terminal portion 10a.

Hereinafter, the direction in which the external connection terminals 104 are arranged in the terminal portion 10a of the element substrate 10 will be referred to as the X direction, and the direction orthogonal to the X direction within the same plane will be referred to as the Y direction. Further, the direction perpendicular to the X direction and the Y direction and going from the element substrate 10 side to the counter substrate 20 side is defined as the Z direction. Furthermore, viewing in the opposite direction to the Z direction, that is, from the counter substrate 20 side toward the element substrate 10 side, is referred to as "planar view" or "planar view". In this embodiment, the pixels P are arranged in a matrix in the X direction and the Y direction in the display area E1.

As shown in FIG. 2, on the surface of the element substrate 10 on the liquid crystal layer 50 side, a transparent pixel electrode 15 provided for each pixel P and a thin film transistor (hereinafter referred to as TFT) 30 which is a switching element are provided. , signal wiring, and an alignment film 18 covering these are formed. Further, a light shielding structure is employed to prevent light from entering the semiconductor layer of the TFT 30 and making the switching operation unstable. The element substrate 10 includes a transparent base material 10s, and a pixel electrode 15, a TFT 30, a signal wiring, and an alignment film 18 formed on the base material 10s. Note that the base material 10s is an example of the first substrate in the present invention.

The counter substrate 20 arranged opposite to the element substrate 10 includes a transparent base material 20s, a parting part 21 formed on the base material 20s, and a flattening layer 22 formed to cover this part. It includes a counter electrode 23 that covers the planarization layer 22 and is provided over at least the display area E1 and functions as a common electrode, and an alignment film 24 that covers the counter electrode 23. Note that the base material 20s is an example of the second substrate in the present invention.

The parting section 21 is provided to surround the display area E1, as shown in FIG. This blocks unnecessary stray light from entering the display area E1 from the counter substrate 20 side, ensuring high contrast in the display of the display area E1.

The planarizing layer 22 is made of an inorganic material such as silicon oxide, has optical transparency, and is provided so as to cover the parting portion 21 . A method for forming such a planarization layer 22 includes, for example, a method of forming a film using a plasma CVD method or the like.

The counter electrode 23 is made of a transparent conductive film such as ITO (Indium Tin Oxide), covers the planarization layer 22, and is electrically connected to the upper and lower conductive portions 106 provided at the four corners of the counter substrate 20 as shown in FIG. It is connected to the. The vertical conduction portion 106 is electrically connected to the wiring on the element substrate 10 side.

The alignment film 18 covering the pixel electrode 15 and the alignment film 24 covering the counter electrode 23 are selected based on the optical design of the liquid crystal device 100. The alignment films 18 and 24 are, for example, organic alignment films that align liquid crystal molecules having positive dielectric anisotropy substantially horizontally in a predetermined direction by forming a film of an organic material such as polyimide and rubbing the surface thereof. Also, there are inorganic alignment films in which liquid crystal molecules with negative dielectric anisotropy are aligned approximately perpendicular to the film surface by forming a film of an inorganic material such as SiOx (silicon oxide) using a vapor phase growth method. .

Such a liquid crystal device 100 is a transmissive type, and has a normally white mode in which the transmittance of the pixel P is maximum when no voltage is applied, and a normally black mode in which the transmittance of the pixel P is minimum when no voltage is applied. Mode optical design is adopted. Depending on the optical design, polarizing elements are arranged and used on the light incident side and the light exit side of the liquid crystal panel 110 including the element substrate 10 and the counter substrate 20, respectively. Note that, of the element substrate 10 and the counter substrate 20, an optical element such as a microlens may be provided on the substrate on the side into which light enters to effectively utilize the incident light and guide it to the pixel P. good.

As shown in FIG. 3, the liquid crystal device 100 of this embodiment is, for example, of full high-definition (FHD) standard, and in the display area E1, there are at least 1920 pixels in the horizontal direction (X direction) and 1920 pixels in the vertical direction (Y direction). has at least 1080 pixels P. As shown in FIG. 4, the pixel P is arranged corresponding to the intersection of the scanning line 3 extending in the X direction and the data line 6 and capacitor line 7 extending in the Y direction. The pixel P is provided with a pixel circuit including a pixel electrode 15, a TFT 30, and a storage capacitor 16. The scanning line 3 is connected to the gate of the TFT 30, the data line 6 is connected to the source of the TFT 30, and the pixel electrode 15 is connected to the drain of the TFT 30. A storage capacitor 16 is connected between the drain of the TFT 30 and the capacitor line 7. Note that the capacitor line 7 to which a fixed potential is applied is not limited to extending in the Y direction, but may extend in the X direction.

Returning to FIG. 3, a data line drive circuit 101 is provided on the element substrate 10 between the terminal portion 10a and the display area E1. Further, a scanning line drive circuit 102 is provided between a pair of side portions facing each other in the X direction and the display area E1. Further, a test circuit 103 is provided between the sealing material 40 (sealing area E3) along the side facing the terminal portion 10a in the Y direction and the display area E1. The data line drive circuit 101 and the scanning line drive circuit 102 are peripheral circuits serving as drive circuits related to drive control of pixel circuits. The inspection circuit 103 is a peripheral circuit that inspects the data line 6 for short circuits and disconnections, or inspects the pixels P for various defects.

In this embodiment, the data line drive circuit 101 includes a first latch circuit 101A, a second latch circuit 101B, and a voltage selection circuit 101C, which are arranged in order from the terminal portion 10a toward the display area E1 in the Y direction. ing. The scanning line drive circuit 102 includes a shift register 102A and an output control circuit 102B, which are arranged in order from a pair of sides facing each other in the X direction toward the display area E1. Note that the output control circuit 102B includes a buffer.

A plurality of (1920) data lines 6 are connected to the data line drive circuit 101. A plurality of (1080) scanning lines 3 are connected to the scanning line drive circuit 102 . Various drive signals and power supply potentials VDD and VSS are input to each of the data line drive circuit 101 and the scanning line drive circuit 102 via external connection terminals 104. Further, in the terminal portion 10a of the element substrate 10, among the plurality of external connection terminals 104, the external connection terminals 104 located at both ends in the X direction are connected to the upper and lower conductive portions 106, and the common potential (LCCOM) is input.
As described above, since the counter electrode 23 of the counter substrate 20 is connected to the upper and lower conductive portions 106, the common potential (LCCOM) is applied to the counter electrode 23 via the upper and lower conductive portions 106. The element substrate 10 is provided with common potential wiring 107 for electrically connecting the upper and lower conductive portions 106 provided at the four corners.

The shift register 102A of the scanning line drive circuit 102 is driven by clock signals CLK and CLKB, and when the start pulse DY is input, it controls the plurality of scanning lines 3 (G1, G2...G1079, G1080). Performs operations to transfer signals sequentially. The control signal is a signal related to ON (selection)/OFF (non-selection) of the TFT 30 of the pixel circuit connected to the scanning line 3. Further, the output control circuit 102B is capable of scanning the display area E1 using ten output control signals ENBY1 to ENBY10, and selects a plurality of scanning lines 3 (G1, G2 . . . G1079, G1080) at an appropriate time. With the above configuration, the liquid crystal device 100 divides one frame into 10 subframes, and weighted time division driving is possible.

The first latch circuit 101A of the data line drive circuit 101 is demultiplexed and stores video signals VID1 to VID240, which are digital signals, in the first latch circuit 101A using first latch signals SEL1 to SEL8. A second latch circuit 101B is connected to the subsequent stage of the first latch circuit 101A, and the logic states stored in the first latch circuit 101A are transferred all at once to the second latch circuit 101B by the second latch signal LAT2. A voltage selection circuit 101C is connected after the second latch circuit 101B. The voltage selection circuit 101C selects one of the voltages V1, V2, and V3 as a plurality of data according to the logic state stored in the second latch circuit 101B and the polarity signal POL that indicates the polarity of the subframe when writing to the pixel P. Output to line 6 (S1, S2...S1919, S1920). If the liquid crystal device 100 is in the normally black mode as described above and the common potential (LCCOM) is 7V, then V1 is a positive white display voltage of 12V, for example. V2 is a black display voltage common to both polarities, and is 7V. V3 is a negative polarity white display voltage and is 2V. That is, the liquid crystal device 100 performs display by alternating current driving in which the potential changes between a positive potential and a negative potential with respect to a common potential (LCCOM).

In this embodiment, the data line drive circuit 101, the scan line drive circuit 102, and the inspection circuit 103, which are peripheral circuits, are arranged so as to overlap the parting section 21 in a plan view. Furthermore, among these peripheral circuits, the first latch circuit 101A is arranged to overlap the seal area E3 in plan view. Furthermore, the shift register 102A is also arranged to overlap the seal area E3 in plan view. Therefore, the lengths of the element substrate 10 in the X and Y directions are shorter than in the case where the parting part 21 is extended so that all of these peripheral circuits overlap with the parting part 21.

Placing the first latch circuit 101A and the shift register 102A in the sealing area E3 where the photocurable sealant 40 is placed affects the process of curing the sealant 40 by irradiating it with light. Therefore, in this embodiment, the configuration and arrangement of the first latch circuit 101A and the shift register 102A are devised so as not to affect the curing of the sealing material 40.
Hereinafter, each circuit will be explained with reference to the drawings.

<Configuration and arrangement of the first latch circuit>
5 is a circuit diagram showing the configuration of the first latch circuit, FIG. 6 is a plan view showing the arrangement of each component of the first latch circuit in the seal area, and FIG. 7 is a circuit diagram showing the arrangement of the first latch circuit in the seal area. FIG. 2 is a cross-sectional view showing the structure of a latch circuit. Note that FIG. 5 shows the configuration of a latch circuit unit (unit) corresponding to one data line 6. In other words, the first latch circuit 101A includes 1920 latch circuit units 101AU.

As shown in FIG. 5, the latch circuit unit 101AU of the first latch circuit 101A in this embodiment includes two analog switches (ASW) 121, 122 and two inverters (INV) 123, 124. ing. Each of the two ASWs 121 and 122 is, for example, a transfer gate made up of an N-type transistor and a P-type transistor. Each of the two INVs 123 and 124 is also composed of, for example, an N-type transistor and a P-type transistor. INV123 and INV124 are electrically connected in series and function as a memory element.

As shown in FIG. 6, each of the ASW 121, ASW 122, INV 123, and INV 124 is arranged in an island shape extending in the X direction in the seal area E3 outside the peripheral area E2 where the parting part 21 is arranged, and They are arranged at intervals in the Y direction. Further, an island-shaped light shielding layer 131 is arranged on the back side of each of the ASW 121, ASW 122, INV 123, and INV 124 so as to overlap with each other in plan view. Furthermore, a light shielding pattern 137 is arranged on the front side of each of the ASW 121, ASW 122, INV 123, and INV 124 so as to overlap with each other in plan view. In addition, in FIG. 6, the outer shape of the light shielding pattern 137 is shown with a broken line so that the structure of the lower layer can be seen. In this embodiment, the power supply potential VSS is supplied to the light shielding pattern 137 that overlaps with each of the ASW 121, ASW 122, and INV 123 in plan view, and the power supply potential VDD is supplied to the light shield pattern 137 that overlaps with the INV 124 in plan view. Supplied. In other words, the light shielding pattern 137 is a power supply wiring.

Two signal lines 126a and 126b extending in the X direction are arranged outside the ASW 121 in the Y direction with an interval in the Y direction. A latch signal LAT is supplied to the signal line 126a, and an inverted latch signal LATB is supplied to the signal line 126b. The latch signal LAT corresponds to the first latch signals SEL1 to SEL8 in the first latch circuit 101A described above. Specifically, each of the first latch signals SEL1 to SEL8 is buffered and at the same time, an inverted signal is generated, and becomes the latch signal LAT and the inverted latch signal LATB.

The signal line 126a to which the latch signal LAT is supplied is connected to the gate of the N-type transistor 121N in the ASW 121 and the gate of the P-type transistor 122P in the ASW 122 by a connection wiring 127a extending in the Y direction. Further, the signal line 126b to which the inverted latch signal LATB is supplied is connected to the gate of the P-type transistor 121P in the ASW 121 and the gate of the N-type transistor 122N in the ASW 122 by a connection wiring 127b extending in the Y direction.

The input wiring 125, which extends in the Y direction between the connecting wiring 127a and the connecting wiring 127b and is supplied with any of the video signals VID1 to VID240 described above, connects the N-type transistor 121N and the N-type transistor 121N of the ASW 121 via the connecting wiring 135a. It is connected to the input side of the P-type transistor 121P. The outputs of the N-type transistor 121N and P-type transistor 121P of the ASW 121 are connected to the input sides of the N-type transistor 122N and P-type transistor 122P of the ASW 122 via a connection wiring 135b extending in the Y direction. Further, the output of the ASW 121 is connected to the gates of the N-type transistor 123N and the P-type transistor 123P of the INV 123 via a connection wiring 127c connected to the connection wiring 135b. The outputs of the N-type transistor 123N and the P-type transistor 123P of the INV 123 are connected to the gates of the N-type transistor 124N and the P-type transistor 124P of the INV 124 via a connection wiring 135d and a connection wiring 127d. The inputs of the N-type transistor 122N and P-type transistor 122P of the ASW 122 and the outputs of the N-type transistor 124N and P-type transistor 124P of the INV 124 are connected by a connection wiring 135c, and the connection wiring 135c is further connected to the output wiring 129. . Note that in this embodiment, the connection wiring 135c and the output wiring 129 are integrally formed in the same wiring layer.

The connection wiring 135e connected to the P-type transistor 123P of the INV123 and the P-type transistor 124P of the INV124 is connected to the light shielding pattern 137 to which the power supply potential VDD is supplied through a contact hole CNT5 provided on the P-type transistor 124P side. has been done. Further, the connection wiring 135f connected to the N-type transistor 123N of the INV123 and the N-type transistor 124N of the INV124 is connected to a light-shielding pattern 137 to which the power supply potential VSS is supplied through a contact hole CNT6 provided on the N-type transistor 123N side. It is connected to the.

According to the latch circuit unit 101AU, one of the video signals VID1 to VID240 input to the input wiring 125 is stored in the latch circuit unit 101AU by the latch signal LAT and the inverted latch LATB. Then, the video signal stored in the latch circuit unit 101AU is outputted to the subsequent second latch circuit 101B by the second latch signal LAT2 inputted to the data line drive circuit 101.

In addition, in FIG. 6, wirings hatched in the same pattern are formed in the same wiring layer on the base material 10s. Specifically, the input wiring 125 and the connection wirings 127a, 127b, 127c, and 127d are in the same wiring layer. Further, the signal lines 126a, 126b, the connection wirings 135a, 135b, 135c, 135d, 135e, 135f, and the output wiring 129 are in the same wiring layer.

Next, the wiring structure of the latch circuit unit 101AU will be explained using the ASW 121 as an example. The line A-A' in FIG. 6 is a line segment that crosses the ASW 121 in the X direction, and FIG. 7 is a cross-sectional view showing the wiring structure of the ASW 121 on the base material 10s of the element substrate 10.

As shown in FIG. 7, a light shielding layer 131 is first formed on the transparent base material 10s. The light shielding layer 131 of this embodiment includes, for example, Ti, Cr, Mo, Ta, W, It is formed using a single metal, an alloy, a metal silicide, a laminate of these, or conductive polysilicon, including at least one of high-melting point metals such as. In particular, the light-shielding layer 131 is made of metal silicide having light-shielding properties from the viewpoint of blocking light incident from the side of the base material 10s and preventing light incident from the side opposite to the base material 10s from being reflected toward the semiconductor layer side of the transistor. In this embodiment, the light shielding layer 131 is preferably formed using tungsten silicide (WSi). The thickness of the light shielding layer 131 is, for example, 150 nm. Note that the light shielding layer 131 is formed into an island shape by photolithography so as to overlap the ASW 121 in a plan view, as described above.

A first insulating film 132 is formed to cover the light shielding layer 131. The first insulating film 132 is formed using, for example, a silicon oxide film (None-doped Silicate Glass; NSG film) or a silicon nitride film (Si _x N _y film) to which impurities are not intentionally introduced. The first insulating film 132 can be formed using a normal pressure CVD method or a low pressure CVD method using a processing gas such as monosilane (SiH ₄ ), dichlorosilane (SiCl ₂ H ₂ ), TEOS (tetraethoxysilane), or ammonia. , or plasma CVD method. The thickness of the first insulating film 132 is, for example, 200 nm.

Next, a semiconductor layer 121Na of the N-type transistor 121N and a semiconductor layer 121Pa of the P-type transistor 121P are formed on the first insulating film 132. The semiconductor layer 121Na and the semiconductor layer 121Pa are made of a polysilicon film obtained by crystallizing an amorphous silicon film deposited by, for example, a low pressure CVD method. N-type impurity ions are selectively implanted into the polysilicon film to form a source region 121Ns, a low concentration source region 121Ne, a channel region 121Nc, a low concentration drain region 121Nf, and a drain region 121Nd, and a semiconductor layer 121Na is formed. It is configured. Furthermore, P-type impurity ions are selectively implanted into the polysilicon film to form a drain region 121Pd, a channel region 121Pc, and a source region 121Ps, thereby configuring the semiconductor layer 121Pa. The thickness of each of the semiconductor layers 121Na and 121Pa is, for example, 50 nm.

Next, a gate insulating film 133 covering the semiconductor layer 121Na and the semiconductor layer 121Pa is formed. The gate insulating film 133 is made of, for example, a first silicon oxide film obtained by thermally oxidizing a silicon semiconductor film, and a second silicon oxide film formed using a low pressure CVD method under high temperature conditions of 700° C. to 900° C. It has a layered structure. The thickness of the gate insulating film 133 is, for example, 75 nm.

Next, a gate electrode 121Ng is formed on the gate insulating film 133 at a position facing the channel region 121Nc of the semiconductor layer 121Na. Furthermore, a gate electrode 121Pg is formed at a position facing the channel region 121Pc of the semiconductor layer 121Pa. The gate electrodes 121Ng and 121Pg are formed using a conductive polysilicon film, a metal silicide film, a metal film, a metal compound film, or the like. In this embodiment, the gate electrodes 121Ng and 121Pg have a two-layer structure of a conductive polysilicon film and a tungsten silicide film. The conductive polysilicon film is made by depositing a polysilicon film doped with phosphorus (P) using a low-pressure CVD method, and then performing a phosphorus diffusion process to form a polysilicon film with 1×10 ¹⁹ phosphorus atoms/cm. It is formed so that it is contained at a concentration of ³ or more. The film thickness of the gate electrodes 121Ng and 121Pg is, for example, 150 nm. Note that the atoms doped into the polysilicon film are not limited to phosphorus (P).

Further, in this embodiment, a part of the connection wiring 127a (see FIG. 6) functions as the gate electrode 121Ng, and a part of the connection wiring 127b (see FIG. 6) functions as the gate electrode 121Pg. .

Next, a second insulating film 134 is formed to cover the gate insulating film 133 and the gate electrodes 121Ng and 121Pg. The second insulating film 134 includes the aforementioned NSG film, a PSG (Phospho Silicate Glass) film containing phosphorus (P), a BSG (Boro Silicate Glass) film containing boron, or a boron (B) and phosphorus (P) film. It is formed using a silicon-based oxide film such as a BPSG (Boro-phospho Silicate Glass) film. Methods for forming these silicon-based oxide films include normal pressure CVD, low pressure CVD, or plasma CVD using monosilane, dichlorosilane, TEOS, TEB (triethyl borate), TMPO (trimethyl phosphate), etc. can be mentioned. The thickness of the second insulating film 134 is, for example, 300 nm.

A total of four through holes are formed through the second insulating film 134 and the gate insulating film 133 to reach the source region 121Ns and drain region 121Nd of the semiconductor layer 121Na, and the drain region 121Pd and source region 121Ps of the semiconductor layer 121Pa. Ru. By forming and patterning a conductive film on the second insulating film 134 so as to cover at least the inner walls of these through holes or to fill the through holes, contact holes CNT1 and source regions are formed through contact holes CNT1. A connection wiring 135a electrically connected to 121Ns is formed. Further, the connection wiring 135a is also connected to the source region 121Ps of the semiconductor layer 121Pa via the contact hole CNT4. Further, a connecting wiring 135b is formed which is electrically connected to the drain region 121Nd of the semiconductor layer 121Na through the contact hole CNT2 and electrically connected to the drain region 121Pd of the semiconductor layer 121Pa through the contact hole CNT3. The conductive film forming the connection wirings 135a, 135b and the contact holes CNT1, CNT2, CNT3, CNT4 is, for example, a layer made of low resistance metal such as Al (aluminum), Ti (titanium), or TiN (titanium nitride). A multilayer structure including: The thickness of the wiring layer including the connection wirings 135a and 135b is, for example, 500 nm. This wiring layer is given the reference numeral 135 and is called a first wiring layer 135.

Next, a third insulating film 136 covering the first wiring layer 135 is formed. Similarly to the second insulating film 134, the third insulating film 136 is also formed using a silicon-based oxide film such as an NSG film, a PSG film, a BSG film, or a BPSG film. Since the surface of the third insulating film 136 formed is uneven due to the influence of the underlying wiring layer, a planarization process such as a CMP process is performed, for example. The average thickness of the third insulating film 136 after the planarization process is, for example, 300 nm.

Next, a plurality of light shielding patterns 137 are formed on the third insulating film 136. Like the first wiring layer 135 described above, the light shielding pattern 137 has a multilayer structure including a layer made of, for example, a low resistance metal such as Al (aluminum), Ti (titanium), or TiN (titanium nitride). The thickness of the light shielding pattern 137 is, for example, 500 nm. The wiring layer in which the plurality of light shielding patterns 137 are formed may be collectively referred to as a second wiring layer 137.

<Configuration and arrangement of shift register>
8 is a circuit diagram showing the configuration of the shift register, FIG. 9 is a plan view showing the arrangement of each component of the shift register in the seal area, and FIG. 10 is a diagram showing the structure of the shift register along line BB' in FIG. 9. FIG. Note that FIG. 8 shows the configuration of a shift register unit (unit) corresponding to one scanning line 3. In other words, the shift register 102A is configured to include 1080 shift register units.

As shown in FIG. 8, the shift register unit 102AU of the shift register 102A of this embodiment includes two N-type transistors 141 and 142 and two inverters (INV) 143 and 144. Each of the two INVs 143 and 144 includes, for example, a P-type transistor and an N-type transistor. INV143 and INV144 are electrically connected in series and function as a memory element. A start pulse DY is connected to IN of the first stage shift register unit 102AU of the shift register 102A. OUT of the first stage shift register unit 102AU is connected to IN of the second stage shift register unit 102AU. When the configuration of the first stage of the shift register 102A is the shift register unit 102AU shown in FIG. 8, the configuration of the second stage is the configuration in which the clock signal CLK and its inverted signal CLKB are exchanged and connected in the shift register unit 102AU shown in FIG. Become. Thereafter, a large number of shift register units 102AU are connected while changing the clock signals in the same manner to form a shift register 102A.

As shown in FIG. 9, each of the two N-type transistors 141, 142, INV143, and INV144 has an island shape extending in the Y direction in a sealing area E3 outside the peripheral area E2 where the parting part 21 is arranged. and spaced apart from each other in the X direction. Further, for each of the two N-type transistors 141, 142, INV143, and INV144, an island-shaped light shielding layer 151 is arranged on the back side thereof so as to overlap in plan view. Further, a light shielding pattern 153 is arranged on the front side of each of the two N-type transistors 141, 142, INV143, and INV144 so as to overlap with each other in plan view. In addition, in FIG. 9, the outer shape of the light shielding pattern 153 is shown with a broken line so that the structure of the lower layer can be seen. In this embodiment, the power supply potential VSS is supplied to the light shielding pattern 153 that overlaps each of the two N-type transistors 141, 142 and INV143 in plan view, and the power supply potential VSS is supplied to the light shielding pattern 153 that overlaps with the INV144 in plan view. A potential VDD is supplied. In other words, the light shielding pattern 153 is a power supply wiring.

Two signal lines 145a and 145b extending in the Y direction are arranged outside the two N-type transistors 141 and 142 in the X direction, with an interval in the X direction. A clock signal CLK is supplied to the signal line 145a, and an inverted clock signal CLKB is supplied to the signal line 145b.

A signal line 145a to which the clock signal CLK is supplied is connected to the gate of the N-type transistor 141 via a connecting wire 146a extending in the X direction. The signal line 145b to which the inverted clock signal CLKB is supplied is connected to the gate of the N-type transistor 142 via a connection wiring 146b that also extends in the X direction. An input wiring 152a is connected to the input side of the N-type transistor 141. A connection wiring 152b is connected to the output side of the N-type transistor 141 and the output side of the N-type transistor 142.

The INV 143 includes an N-type transistor 143N and a P-type transistor 143P. The gate of the N-type transistor 143N and the gate of the P-type transistor 143P are connected via a connection wiring 146c. The connection wiring 146c is electrically connected to the connection wiring 152b connected to the output side of the N-type transistor 141. The connecting wire 152b is arranged so as to overlap the connecting wire 146a and is connected to the connecting wire 146c. This reduces the pattern area ratio of each wiring, making it suitable for transmitting ultraviolet light (UV light) from the back surface. A connection wiring 152d is connected to the output side of the N-type transistor 143N and the output side of the P-type transistor 143P of the INV143.

The INV144 is composed of an N-type transistor 144N and a P-type transistor 144P. The gate of the N-type transistor 144N and the gate of the P-type transistor 144P are connected via a connection wiring 146d. The connection wiring 146d is electrically connected to the connection wiring 152d connected to the output side of the N-type transistor 143N of the INV143. The connecting wire 152d is arranged so as to overlap the connecting wire 146c and is connected to the connecting wire 146d. This reduces the pattern area ratio of each wiring, making it suitable for UV light to pass through from the back surface. A connection wiring 152c is connected to the output side of the N-type transistor 144N and the output side of the P-type transistor 144P of the INV144. The connection wiring 152c is also electrically connected to the input (OUT) side of the N-type transistor 142.
Note that the connection wiring 152c also functions as an output wiring.

The connection wiring 152e connected to the P-type transistor 143P of the INV143 and the P-type transistor 144P of the INV144 is connected to the light-shielding pattern 153 to which the power supply potential VDD is supplied through a contact hole CNT15 provided on the P-type transistor 144P side. has been done. Further, the connection wiring 152f connected to the N-type transistor 143N of the INV143 and the N-type transistor 144N of the INV144 is connected to a light-shielding pattern 153 to which the power supply potential VSS is supplied through a contact hole CNT16 provided on the N-type transistor 143N side. It is connected to the.

According to such a shift register unit 102AU, a control signal related to switching control of the TFT 30 in the pixel circuit described above is supplied to the N-type transistor 141 via the input wiring 152a. When the start pulse DY is input to the scanning line drive circuit 102, the switching of the two N-type transistors 141 and 142 is controlled by the clock signal CLK and the inverted clock signal CLKB, and the control signal is applied to the INVs 143 and 144 and the connection wiring 152c. The signal is output to the subsequent output control circuit 102B via the .

Note that, in FIG. 9, wirings hatched in the same pattern are formed in the same wiring layer on the base material 10s. Specifically, the connection wirings 146a, 146b, 146c, and 146d are in the same wiring layer. Further, the signal lines 145a, 145b, the input wiring 152a, and the connection wirings 152b, 152c, 152d, 152e, and 152f are in the same wiring layer.

Next, the wiring structure of the shift register unit 102AU will be explained using the INV 144 as an example. The line B-B' in FIG. 9 is a line segment that crosses the INV 144 in the Y direction, and FIG. 10 is a cross-sectional view showing the wiring structure of the INV 144 on the base material 10s of the element substrate 10. Note that the same components as those of the latch circuit unit 101AU described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 10, a light shielding layer 151 is first formed on the transparent base material 10s. The light-shielding layer 151 is made of the same high-melting point metal material as the light-shielding layer 131 in the latch circuit unit 101AU described above, and in this embodiment is made of low-reflectivity tungsten silicide (WSi). The thickness of the light shielding layer 151 is, for example, 150 nm, the same as the thickness of the light shielding layer 131. Note that the light shielding layer 151 is formed into an island shape by photolithography so as to overlap the INV 144 in plan view, as described above.

A first insulating film 132 is formed to cover the light shielding layer 151. The first insulating film 132 is formed using, for example, an NSG film or a silicon nitride film (Si _x N _y film) into which impurities are not intentionally introduced. The thickness of the first insulating film 132 is, for example, 200 nm.

A semiconductor layer 144Na of an N-type transistor 144N and a semiconductor layer 144Pa of a P-type transistor 144P in the INV 144 are formed on the first insulating film 132. The semiconductor layer 144Na includes a drain region 144Nd, a lightly doped drain region 144Ne, a channel region 144Nc, a lightly doped source region 144Nf, and a source region 144Ns, which are formed by selectively implanting N-type impurity ions into a polysilicon film. . The semiconductor layer 144Pa includes a drain region 144Pd, a channel region 144Pc, and a source region 144Ps, which are formed by selectively implanting P-type impurity ions into a polysilicon film. The thickness of each of the semiconductor layers 144Na and 144Pa is, for example, 50 nm.

Next, a gate insulating film 133 covering the semiconductor layer 144Na and the semiconductor layer 144Pa is formed. As described above, the gate insulating film 133 has a two-layer structure of a first silicon oxide film and a second silicon oxide film, and has a thickness of, for example, 75 nm.

Next, a gate electrode 144Ng is formed on the gate insulating film 133 at a position facing the channel region 144Nc of the semiconductor layer 144Na. Furthermore, a gate electrode 144Pg is formed at a position facing the channel region 144Pc of the semiconductor layer 144Pa. In this embodiment, the gate electrodes 144Ng and 144Pg have a two-layer structure of a conductive polysilicon film and a tungsten silicide film. The film thickness of each gate electrode 144Ng, 144Pg is, for example, 150 nm.

Further, in this embodiment, a part of the connection wiring 146d (see FIG. 9) functions as the gate electrode 144Ng and the gate electrode 144Pg.

Next, a second insulating film 134 is formed to cover the gate insulating film 133 and the gate electrodes 144Ng and 144Pg. The second insulating film 134 is formed using a silicon-based oxide film such as the aforementioned NSG film, PSG film, BSG film, or BPSG film. The thickness of the second insulating film 134 is, for example, 300 nm.

A total of four through holes are formed through the second insulating film 134 and the gate insulating film 133 to reach the source region 144Ns and drain region 144Nd of the semiconductor layer 144Na, and the drain region 144Pd and source region 144Ps of the semiconductor layer 144Pa. Ru. By forming and patterning a conductive film on the second insulating film 134 so as to cover at least the inner walls of these through holes or to fill the through holes, contact holes CNT11 and a semiconductor layer are formed through contact holes CNT11. A connecting wiring 152f electrically connected to the 144Na source region 144Ns is formed. Furthermore, a connecting wiring 152c is formed which is electrically connected to the drain region 144Nd of the semiconductor layer 144Na through the contact hole CNT12 and electrically connected to the drain region 144Pd of the semiconductor layer 144Pa through the contact hole CNT13. Further, a contact hole CNT14 and a connection wiring 152e electrically connected to the source region 144Ps of the semiconductor layer 144Pa via the contact hole CNT14 are formed. The conductive films forming such connection wirings 152c, 152e, 152f and contact holes CNT11, CNT12, CNT13, CNT14 are made of, for example, low resistance metals such as Al (aluminum), Ti (titanium), or TiN (titanium nitride). A multilayer structure including a layer of The thickness of the wiring layer including the connection wirings 152c, 152e, and 152f is, for example, 500 nm. This wiring layer is the same layer as the first wiring layer 135 described above.

Next, a third insulating film 136 is formed to cover the connection wirings 152c, 152e, and 152f. Similarly to the second insulating film 134, the third insulating film 136 is also formed using a silicon-based oxide film such as an NSG film, a PSG film, a BSG film, or a BPSG film. Since the surface of the third insulating film 136 formed is uneven due to the influence of the underlying wiring layer, a planarization process such as a CMP process is performed, for example. The average thickness of the third insulating film 136 after the planarization process is, for example, 300 nm.

Next, a light shielding pattern 153 is formed on the third insulating film 136. Like the connection wirings 152c, 152e, and 152f, the light-shielding pattern 153 has a multilayer structure including, for example, a layer made of low-resistance metal such as Al (aluminum), Ti (titanium), or TiN (titanium nitride). The thickness of the light shielding pattern 153 is, for example, 500 nm. The light shielding pattern 153 is formed in the same layer as the second wiring layer 137 in the latch circuit unit 101AU described above.

In this way, the data line drive circuit 101 including the first latch circuit 101A, the scanning line drive circuit 102 including the shift register 102A, and the inspection circuit 103 are formed on the base material 10s. Furthermore, pixel circuits and external connection terminals 104 connected to these peripheral circuits are formed.

FIG. 11 is a schematic cross-sectional view showing the process of curing the sealing material placed between the element substrate and the counter substrate. Specifically, FIG. 11 shows a cross section along the Y direction of a portion where the above-mentioned latch circuit unit 101AU is arranged in the seal area E3.

A photo-curable adhesive is applied in a frame shape to the seal area E3 of the element substrate 10 where the pixel circuits and peripheral circuits are formed. A predetermined amount of liquid crystal is dropped under reduced pressure on the inside of the adhesive applied in a frame shape, and the element substrate 10 and the counter substrate 20 are bonded together. By applying pressure and bonding, the adhesive spreads within the sealing area E3. As described above, since the adhesive includes a spacer (not shown in FIG. 11), the element substrate 10 and the counter substrate 20 are arranged facing each other with a predetermined interval as shown in FIG. Ru. At this time, the predetermined interval, that is, the thickness of the adhesive is, for example, 1.5 μm to 3.0 μm.

As shown in FIG. 11, masks 60 are placed on both sides of the element substrate 10 and the counter substrate 20, which are arranged to face each other, so that ultraviolet rays (UV light) do not enter the display area unnecessarily. The mask 60 is placed across the display area E1 and the peripheral area E2 where the parting section 21 is placed. Then, UV light is irradiated from both the element substrate 10 side and the counter substrate 20 side to cure the photocurable adhesive to form the sealing material 40.

A counter electrode 23 made of a transparent conductive film is arranged in the sealing area E3 of the counter substrate 20, but since the base material 20s and the counter electrode 23 transmit ultraviolet rays (UV light), they are not irradiated from the counter substrate 20 side. UV light reaches the adhesive unobstructed.

On the other hand, the latch circuit unit 101AU is arranged in the seal area E3 of the element substrate 10, as described above. The ASW121, ASW122, INV123, and INV124 that constitute the latch circuit unit 101AU are arranged at intervals in the Y direction. Further, each of the ASW 121, ASW 122, INV 123, and INV 124, which are composed of N-type and P-type transistors, is arranged between the light-shielding layer 131 and the light-shielding pattern 137 on the base material 10s. That is, each of the ASW 121, ASW 122, INV 123, and INV 124 is shielded from light by the light shielding layer 131 and the light shielding pattern 137.

Assuming that the width of the light shielding layer 131 (light shielding pattern 137) in the Y direction is L, and the interval between adjacent light shielding layers 131 (light shielding pattern 137) is S, in this embodiment, L:S=1:1. . Therefore, the UV light irradiated from the element substrate 10 side passes through the light-transmitting base material 10s and the interval S between the adjacent light-shielding layers 131 (light-shielding patterns 137), and reaches the adhesive.
Furthermore, even if UV light is irradiated from both the element substrate 10 side and the counter substrate 20 side, the light is blocked by the light shielding layer 131 and the light shielding pattern 137. No incident. That is, even if part of the UV light is blocked by the latch circuit unit 101AU, a sufficient amount of UV light is allowed to enter to cure the photocurable adhesive. On the other hand, since UV light does not enter the semiconductor layers of the N-type transistors and P-type transistors that constitute each of ASW121, ASW122, INV123, and INV124, the electrical characteristics of these transistors will not deteriorate due to UV light irradiation. Prevented.

Note that although FIG. 11 shows the state of photocuring of the sealing material 40 in the sealing area E3 where the latch circuit unit 101AU is arranged, the state of photocuring of the sealing material 40 in the sealing area E3 where the shift register unit 102AU is arranged is shown. The situation is also similar. Specifically, on the base material 10s of the element substrate 10, each of the two N-type transistors 141, 142, INV143, and INV144 constituting the shift register unit 102AU has a light shielding layer 151 provided in an island shape, It is arranged between the light shielding pattern 153 and the light shielding pattern 153. Assuming that the width of the light shielding layer 151 (light shielding pattern 153) in the X direction is L, and the interval between adjacent light shielding layers 151 (light shielding pattern 153) is S, in this embodiment, L:S=1:1. .
If the thickness of the photocurable adhesive is, for example, 1.5 μm to 3.0 μm as described above, the distance S may be the same as or larger than the width L from the viewpoint of promoting photocuring of the adhesive. Preferably, the spacing S is at least 5 μm or more. Furthermore, from the viewpoint of arranging transistors and various wiring lines in the peripheral circuit, the width L is also preferably at least 5 μm or more.

According to the liquid crystal device 100 of the first embodiment described above, the following effects can be obtained.
(1) A part of the peripheral circuitry (first latch circuit 101A, shift register 102A) related to driving the pixel circuit is arranged in the sealing region E3 where the sealing material 40 of the element substrate 10 is arranged. Therefore, the external shapes of the element substrate 10 and the counter substrate 20 are smaller than in the case where a seal area E3 of a predetermined width is secured and a part of these peripheral circuits is placed in the peripheral area E2 where the parting section 21 is placed. can be made small in both the X and Y directions.

(2) The element substrate 10 and the counter substrate 20 are bonded together using a photocurable sealant 40. The semiconductor layer of the N-type or P-type transistor constituting a part of the peripheral circuit arranged in the sealing region E3 is formed by a light-shielding layer 131 arranged at a distance S in the X direction or the Y direction on the base material 10s. (the light-shielding layer 151) and the light-shielding pattern 137 (the light-shielding pattern 153). Therefore, even if ultraviolet light (UV light) is incident from the element substrate 10 side when photocuring the sealing material 40, the UV light passes through the base material 10s and the distance S, so that the sealing material 40 can be sufficiently cured. Can be done. Further, even if UV light is incident from both the element substrate 10 side and the counter substrate 20 side, the UV light does not enter the semiconductor layer of the N-type or P-type transistor that constitutes a part of the peripheral circuit. In other words, it is possible to prevent the electrical characteristics of these transistors from deteriorating due to UV light irradiation for photocuring the sealing material 40.

(Second embodiment)
Next, an electro-optical device according to a second embodiment will be described with reference to FIGS. 12 and 13, using a liquid crystal device as an example, similar to the first embodiment. The liquid crystal device as an electro-optical device according to the second embodiment is different from the liquid crystal device 100 according to the first embodiment in that the arrangement of transistors forming part of the peripheral circuit arranged in the seal area E3 is different from that of the liquid crystal device 100 according to the first embodiment. be.

FIG. 12 is a plan view showing the arrangement of each component of the first latch circuit in the seal area of the second embodiment, and FIG. 13 is a cross-sectional view showing the structure of the first latch circuit along line CC' in FIG. It is.
Note that FIG. 12 shows the arrangement of each component in a latch circuit unit (unit) corresponding to one data line 6. In the liquid crystal device of the second embodiment, the same components as those of the liquid crystal device 100 of the first embodiment are given the same reference numerals, and detailed description thereof will be omitted.

The liquid crystal device 200 of the second embodiment includes an element substrate 10B and a counter substrate 20 bonded to each other with a gap between them using a photocurable sealant 40, and a liquid crystal layer 50 containing liquid crystal filled in the gap. Similar to the element substrate 10 in the liquid crystal device 100 of the first embodiment, a first latch circuit 101A and a shift register 102A are arranged in the seal area E3 of the element substrate 10B. The circuit diagram of the latch circuit unit 101AU in the first latch circuit 101A is basically the same as that shown in FIG. 5 of the first embodiment. That is, as shown in FIG. 5, the latch circuit unit 101AU includes two analog switches (ASW) 121 and 122 and two inverters (INV) 123 and 124. Each of the two ASWs 121 and 122 is, for example, a transfer gate made up of an N-type transistor and a P-type transistor. Each of the two INVs 123 and 124 is also composed of, for example, a P-type transistor and an N-type transistor. INV123 and INV124 are electrically connected in series and function as a memory element. However, in the second embodiment, the arrangement of the semiconductor layers of the transistors in the INV 124 is different.

Specifically, as shown in FIG. 12, each of the ASW 121, ASW 122, INV 123, and INV 124 has an island shape extending in the and spaced apart from each other in the Y direction. Further, an island-shaped light shielding layer 131 is arranged on the back side of each of the ASW 121, ASW 122, INV 123, and INV 124 so as to overlap with each other in plan view. Furthermore, a light shielding pattern 137 is arranged on the front side of each of the ASW 121, ASW 122, INV 123, and INV 124 so as to overlap with each other in plan view. Note that in FIG. 12 as well, the outline of the light shielding pattern 137 is shown with broken lines so that the structure of the lower layer can be seen. A power supply potential VSS is supplied to the light shielding pattern 137 that overlaps each of the ASW 121, ASW 122, and INV 123 in a plan view, and a power supply potential VDD is supplied to the light shield pattern 137 that overlaps the INV 124 in a plan view. In other words, the light shielding pattern 137 is a power supply wiring.

Two signal lines 126a and 126b extending in the X direction are arranged outside the ASW 121 in the Y direction with an interval in the Y direction. A latch signal LAT is supplied to the signal line 126a, and an inverted latch signal LATB is supplied to the signal line 126b.

The arrangement of the input wiring 125, connection wiring 127a, 127b, 127c, and connection wiring 135a, 135b related to the electrical connection between the two signal lines 126a, 126b and the ASW 121, ASW 122, INV 123 is explained in the first embodiment. The content is the same as that.

In this embodiment, the INV 124 includes an N-type transistor 124N1, a P-type transistor 124P1, an N-type transistor 124N2, and a P-type transistor 124P2, which are arranged below (lower layer) of the adjacent light-shielding patterns 137. The N-type transistor 124N1 and the P-type transistor 124P1 are arranged along the X direction, and are arranged adjacent to each other with an interval in the Y direction with respect to the INV 123. The N-type transistor 124N2 and the P-type transistor 124P2 are arranged along the X direction, and are arranged adjacent to each other at intervals in the Y direction with respect to the N-type transistor 124N1 and the P-type transistor 124P1.

The outputs of the N-type transistor 123N and the P-type transistor 123P of the INV 123 are connected to the gates of the N-type transistor 124N1 and the N-type transistor 124N2 of the INV 124 via a connection wiring 135d and a connection wiring 127e. Further, the connection wiring 127e is connected to the gates of the P-type transistor 124P1 and the P-type transistor 124P2. The inputs of the N-type transistor 122N and P-type transistor 122P of the ASW122 and the outputs of the two N-type transistors 124N1, 124N2 and the two P-type transistors 124P1, 124P2 of the INV124 are connected by a connection wiring 135g, and the connection wiring 135g is an output. It functions as a wiring.

The connection wiring 135e connected to the P-type transistor 123P of the INV123 and the two P-type transistors 124P1 and 124P2 of the INV124 is a light-shielding pattern 137 to which VDD is supplied through the contact hole CNT5 provided on the P-type transistor 124P1 side. It is connected to the. In addition, the connection wiring 135f connected to the N-type transistor 123N of the INV123 and the two N-type transistors 124N1 and 124N2 of the INV124 is connected to a light shielding line 135f that is supplied with VSS through a contact hole CNT6 provided on the N-type transistor 123N side. Connected to pattern 137.

That is, the two N-type transistors 124N1 and 124N2 constituting the INV 124 are electrically connected in parallel and share the gate, source, and drain with each other. In other words, one N-type transistor 124N is configured by the two N-type transistors 124N1 and 124N2, and the semiconductor layer is in a divided state. The divided semiconductor layers are arranged below adjacent light shielding patterns 137. Similarly, the two P-type transistors 124P1 and 124P2 constituting the INV124 are electrically connected in parallel and share the gate, source, and drain with each other. In other words, one P-type transistor 124P is configured by the two P-type transistors 124P1 and 124P2, and the semiconductor layer is in a divided state. The divided semiconductor layers are arranged below adjacent light shielding patterns 137.

Next, the wiring structure of the INV 124 will be described with reference to FIG. 13, taking the N-type transistor 124N2 and the P-type transistor 124P2 as examples. Note that the line CC' in FIG. 12 is a line segment that crosses the N-type transistor 124N2 and the P-type transistor 124P2 in the X direction.

As shown in FIG. 13, on the base material 10s of the element substrate 10B, a light shielding layer 131 made of a high melting point metal material such as tungsten silicide (WSi) is first formed in an island shape.
The thickness of the light shielding layer 131 is, for example, 150 nm. A first insulating film 132 made of, for example, an NSG film is formed to cover the light shielding layer 131. The thickness of the first insulating film 132 is, for example, 200 nm. A semiconductor layer 124N2a of the N-type transistor 124N2 and a semiconductor layer 124P2a of the P-type transistor 124P2 in the INV 124 are formed on the first insulating film 132. The semiconductor layer 124N2a includes a drain region 124N2d, a lightly doped drain region 124N2e, a channel region 124N2c, a lightly doped source region 124N2f, and a source region 124N2s, which are formed by selectively implanting N-type impurity ions into a polysilicon film. .
The semiconductor layer 124P2a includes a drain region 124P2d, a channel region 124P2c, and a source region 124P2s, which are formed by selectively implanting P-type impurity ions into a polysilicon film. The thickness of each of the semiconductor layers 124N2a and 124P2a is, for example, 50 nm.

Next, a gate insulating film 133 covering the semiconductor layer 124N2a and the semiconductor layer 124P2a is formed. A gate electrode 124N2g is formed on the gate insulating film 133 at a position facing the channel region 124N2c of the semiconductor layer 124N2a. Further, a gate electrode 124P2g is formed at a position facing the channel region 124P2c of the semiconductor layer 124P2a. In this embodiment, the gate electrodes 124N2g and 124P2g have a two-layer structure of a conductive polysilicon film and a tungsten silicide film. The film thickness of each gate electrode 124N2g, 124P2g is, for example, 150 nm.

Further, in this embodiment, a part of the connection wiring 127e (see FIG. 12) functions as the gate electrode 124N2g and the gate electrode 124P2g.

Next, a second insulating film 134 is formed to cover the gate insulating film 133 and the gate electrodes 124N2g and 124P2g. The second insulating film 134 is formed using a silicon-based oxide film such as the aforementioned NSG film, PSG film, BSG film, or BPSG film. The thickness of the second insulating film 134 is, for example, 300 nm.

A total of four through holes are formed through the second insulating film 134 and the gate insulating film 133 to reach the source region 124N2s and drain region 124N2d of the semiconductor layer 124N2a, and the drain region 124P2d and source region 124P2s of the semiconductor layer 124P2a. Ru. By forming and patterning a conductive film on the second insulating film 134 so as to cover at least the inner walls of these through holes or to fill the through holes, a conductive film is formed on the contact hole CNT7 and the semiconductor layer via the contact hole CNT7. A connection wiring 135f electrically connected to the source region 124N2s of the source region 124N2a is formed. Furthermore, a connecting wiring 135g is formed which is electrically connected to the drain region 124N2d of the semiconductor layer 124N2a via the contact hole CNT8 and electrically connected to the drain region 124P2d of the semiconductor layer 124P2a via the contact hole CNT9. Further, a contact hole CNT10 and a connection wiring 135e electrically connected to the source region 124P2s of the semiconductor layer 124P2a via the contact hole CNT10 are formed. The conductive films forming such connection wirings 135e, 135f, 135g and contact holes CNT7, CNT8, CNT9, CNT10 may be made of, for example, low resistance metals such as Al (aluminum), Ti (titanium), or TiN (titanium nitride). A multilayer structure including a layer of The thickness of the first wiring layer 135 including the connection wirings 135e, 135f, and 135g is, for example, 500 nm.

Next, a third insulating film 136 is formed to cover the connection wirings 135e, 135f, and 135g. Similarly to the second insulating film 134, the third insulating film 136 is also formed using a silicon-based oxide film such as an NSG film, a PSG film, a BSG film, or a BPSG film. Since the surface of the third insulating film 136 formed is uneven due to the influence of the underlying wiring layer, a planarization process such as a CMP process is performed, for example. The average thickness of the third insulating film 136 after the planarization process is, for example, 300 nm.

Next, a light shielding pattern 137 is formed on the third insulating film 136. Like the connection wirings 135e, 135f, and 135g, the light-shielding pattern 137 has a multilayer structure including, for example, a layer made of low-resistance metal such as Al (aluminum), Ti (titanium), or TiN (titanium nitride). The thickness of the light shielding pattern 137 is, for example, 500 nm.

According to the configuration of the element substrate 10B in the liquid crystal device 200 of the second embodiment, the same effects as (1) and (2) in the liquid crystal device 100 of the first embodiment can be obtained. Further, the semiconductor layers of the N-type transistor 124N and the P-type transistor 124P constituting the INV 124 are both divided and disposed below the light-shielding pattern 137 (lower layer). Therefore, compared to the first embodiment in which the semiconductor layer is not divided, it is possible to configure a circuit in which the driving capacity of the INV 124 is greater. In FIG. 12, the configuration is applied to the INV 124, but the configuration may be similarly applied to the analog switches (ASW) 121, 122 and the INV 123. Thereby, for example, the first latch circuit 101A compatible with high-speed driving can be realized.

Note that the configuration in which the semiconductor layer of the transistor arranged below (lower layer) the light shielding pattern 137 is divided is applicable not only to the first latch circuit 101A (latch circuit unit 101AU) but also to the shift register 102A (shift register unit 102AU). Applicable. That is, even if the semiconductor layer of the transistor arranged below (lower layer) the light shielding pattern 153 of the shift register unit 102AU is divided and arranged, the same effect can be obtained.

In the liquid crystal device 100 of the first embodiment and the liquid crystal device 200 of the second embodiment, some of the peripheral circuits arranged in the seal area E3 of the element substrate 10 (element substrate 10B) include the first latch circuit 101A and the liquid crystal device 200 of the second embodiment. The circuit is not limited to both of the shift registers 102A, and may be either one of the circuits. As a result, the length of the outer shape of the element substrate 10 (element substrate 10B) in the X direction or the Y direction can be reduced. If the outer shape of the element substrate 10 (element substrate 10B) is made smaller, the outer shape of the counter substrate 20 can also be made smaller.

From the viewpoint of reducing the external size of the element substrate 10 (element substrate 10B), the semiconductor layer of at least one transistor included in a part of the peripheral circuit is placed in the sealing area E3 using a plurality of light-shielding patterns arranged at intervals. What is necessary is just to arrange|position so that it may overlap with one of the light-shielding patterns in planar view. In other words, by arranging a part of the peripheral circuit in the seal area E3, the seal area E3 of a predetermined width can be secured, and the number of transistors arranged below (lower layer) of the plurality of light shielding patterns can be accommodated. , the width of the peripheral region E2 in which the peripheral circuits are arranged can be reduced.

The liquid crystal device 100 of the first embodiment and the liquid crystal device 200 of the second embodiment are microdisplays suitably used as a light valve (light modulation means) of a projection display device to be described later. Therefore, a plurality of element substrates 10 (element substrates 10B) are manufactured in a state where they are laid out on a motherboard. Even if the size of the display area E1 is the same, if the outer shape of the element substrate 10 (element substrate 10B) becomes smaller, the number of element substrates 10 (element substrate 10B) that can be laid out on the mother board increases. Productivity in manufacturing is improved, and the cost of the liquid crystal device 100 (liquid crystal device 200) can be reduced.

(Third embodiment)
<Electronic equipment>
Next, an electronic device to which the liquid crystal device of this embodiment is applied will be described with reference to FIG. 14, taking a projection display device as an example. FIG. 14 is a schematic diagram showing the configuration of a projection display device as an electronic device according to the third embodiment.

As shown in FIG. 14, a projection display device 1000 as an electronic device of this embodiment includes a polarized illumination device 1100 arranged along the system optical axis Ls, and two dichroic mirrors 1104 and 1105 as light separation elements. , three reflecting mirrors 1106, 1107, 1108, five relay lenses 1201, 1202, 1203, 1204, 1205, three transmissive liquid crystal light valves 1210, 1220, 1230 as light modulation means, and a light combining element. A cross dichroic prism 1206 and a projection lens 1207 are provided.

The polarized illumination device 1100 is generally composed of a lamp unit 1101 as a light source made of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102, and a polarization conversion element 1103.

The dichroic mirror 1104 reflects the red light (R) out of the polarized light beam emitted from the polarized illumination device 1100, and transmits the green light (G) and the blue light (B). Another dichroic mirror 1105 reflects the green light (G) that has passed through the dichroic mirror 1104 and transmits the blue light (B).

The red light (R) reflected by the dichroic mirror 1104 is reflected by the reflective mirror 1106 and then enters the liquid crystal light valve 1210 via the relay lens 1205.
The green light (G) reflected by the dichroic mirror 1105 enters the liquid crystal light valve 1220 via the relay lens 1204.
The blue light (B) transmitted through the dichroic mirror 1105 enters the liquid crystal light valve 1230 via a light guide system consisting of three relay lenses 1201, 1202, 1203 and two reflection mirrors 1107, 1108.

The liquid crystal light valves 1210, 1220, and 1230 are arranged opposite to the incident surface of the cross dichroic prism 1206 for each color light. The colored light incident on the liquid crystal light valves 1210, 1220, and 1230 is modulated based on video information (video signal) and is emitted toward the cross dichroic prism 1206. This prism consists of four rectangular prisms bonded together, and has a cross-shaped dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light formed on its inner surface. These dielectric multilayer films combine three colored lights to create a light representing a color image. The combined light is projected onto the screen 1300 by a projection lens 1207, which is a projection optical system, and the image is enlarged and displayed.

The liquid crystal light valve 1210 is applied with the liquid crystal device 100 of the first embodiment described above. A pair of polarizing elements arranged in crossed nicols are arranged with a gap between them on the color light incident side and the color light exit side of the liquid crystal panel 110. The same applies to the other liquid crystal light valves 1220 and 1230.

According to such a projection type display device 1000, the liquid crystal device 100 described above is used as the liquid crystal light valves 1210, 1220, and 1230, so that the projection type display device 1000 having excellent display quality and cost performance is provided. can do. Note that similar effects can be obtained by using the liquid crystal device 200 of the second embodiment as the liquid crystal light valves 1210, 1220, and 1230. Further, the light source is not limited to a white light source, and an LED or laser light source that supports red light (R), green light (G), or blue light (B) may be used.

The present invention is not limited to the embodiments described above, and various changes and improvements can be made to the embodiments described above. A modified example will be described below.

(Modification 1) If at least the base material 20s of the base material 10s of the element substrate 10 (element substrate 10B) and the base material 20s of the counter substrate 20 has a light-transmitting property, ultraviolet rays can be transmitted from the counter substrate 20 side. It is possible to cure the photocurable sealing material 40 by injecting (UV light).
In that case as well, the outer shape of the element substrate 10 (element substrate 10B) can be made smaller by arranging a part of the peripheral circuit in the seal area E3 of the element substrate 10 (element substrate 10B).
Furthermore, by arranging the transistor that forms part of the peripheral circuit below (lower layer) the light-shielding pattern, the light-shielding pattern can block ultraviolet light (UV light) that enters the semiconductor layer of the transistor.

(Modification 2) As shown in the second embodiment, the structure in which the semiconductor layer of the transistor forming part of the peripheral circuit arranged in the seal area E3 is divided and arranged is to The semiconductor layer is not limited to being placed in the (lower layer), and for example, all or part of the divided semiconductor layer may be placed below one light-shielding pattern. According to this, it is possible to reduce the number of the plurality of light shielding patterns and to reduce the length of the element substrate in the X direction or the Y direction in which the plurality of light shielding patterns are arranged.

(Modification 3) The plurality of light-shielding patterns 137 (light-shielding patterns 153) are not limited to all being power supply wiring, and it is sufficient if one of them is a power supply wiring. In addition, at least one of the plurality of light shielding patterns 137 (light shielding patterns 153) has a common potential wiring 107 (see FIG. 3) for supplying a common potential (LCCOM) to the counter electrode 23, which is a common electrode of the counter substrate 20. ). In this case, the stabilization of the common potential required for driving the pixels P can be strengthened, and the display quality can be improved. Furthermore, in the case of high-speed driving, in order to reduce the parasitic capacitance that becomes a driving load of the high-speed signal system, the light-shielding pattern may be formed not in the form of a continuous wiring but in the form of floating divided islands. For example, in FIG. 6 of the first embodiment, the light shielding pattern 137 overlapping the analog switches 121 and 122 of the first latch circuit unit 101AU is strongly capacitively coupled to the latch signal LAT or inverted latch signal LATB that is driven at high speed. Here, if the light-shielding pattern 137 is configured not to be connected to the power supply potential VSS, and separated into islands for each semiconductor layer and left floating, a configuration suitable for high-speed driving will be obtained.

(Modification 4) Electro-optical devices to which the present invention can be applied are not limited to transmissive liquid crystal devices 100 and 200, but can also be applied to reflective liquid crystal devices. Further, the present invention is not limited to liquid crystal devices, and can be applied to, for example, active drive type light emitting devices in which each pixel includes a light emitting element and a pixel circuit for driving the light emitting element.

(Modification 5) Electronic devices to which the liquid crystal devices 100 and 200 of the above embodiments can be applied are not limited to the projection display device 1000 of the third embodiment. For example, by configuring a liquid crystal device with a color filter having a colored layer in each pixel, it can be used for projection-type HUDs (head-up displays), direct-view HMDs (head-mounted displays), e-books, personal computers, and digital still cameras. It can be suitably used as a display section of information terminal equipment such as a liquid crystal television, a viewfinder type or direct view type video recorder, a car navigation system, an electronic notebook, and a POS.

Below, contents derived from the above embodiment will be described.

The electro-optical device of the present application is an electro-optical device in which an electro-optic element is provided between a first substrate and a second substrate that are arranged to face each other with a photocurable sealing material interposed therebetween, and at least a second substrate. The substrate is translucent and has a plurality of light shielding patterns arranged at intervals in a sealing area of the first substrate where the sealing material is arranged, and drives an electro-optical element on the first substrate. The semiconductor layer of the transistor included in the drive circuit for the invention is characterized in that it is arranged to overlap with at least one light-shielding pattern among the plurality of light-shielding patterns in a plan view.

According to the present application, even if a predetermined width is secured for the sealing area where the photocurable sealing material is placed, the semiconductor layer of the transistor included in the drive circuit for driving the electro-optical element is not placed in the sealing area. In the electro-optical device, the frame area including the seal area can be made smaller than before. In addition, since the semiconductor layer is arranged so as to overlap in plan view with at least one light-shielding pattern among the plurality of light-shielding patterns arranged at intervals on the first substrate, the light-curing pattern is formed by the light-shielding pattern. Light for curing the sealing material can be prevented from entering the semiconductor layer. In other words, the physical properties of the semiconductor layer are prevented from changing due to the incidence of light and the characteristics of the transistor are prevented from deteriorating. That is, even if a photocurable sealing material is adopted, an electro-optical device that can be miniaturized can be provided by arranging the semiconductor layer of at least one transistor related to the drive circuit of the electro-optical element in the sealing region. .

In the above electro-optical device, the first substrate and the second substrate are translucent, and the semiconductor layer includes a light-shielding layer provided in an island shape on the first substrate and one of the plurality of light-shielding patterns. It is preferable that the light shielding pattern is arranged between the light shielding pattern and the light shielding pattern.
According to this configuration, even if light for curing the photocurable sealant is incident from both the first substrate and the second substrate, the light blocking layer and the light blocking pattern prevent the light entering the semiconductor layer. Can be shaded.

In the electro-optical device described above, the transistor may include two transistors in which semiconductor layers are connected in parallel.
According to this configuration, a drive circuit with a large drive capacity can be configured. In other words, it is possible to realize a compact electro-optical device including a transistor having a semiconductor layer that can be used in a digital circuit that requires high-speed driving.

Further, in the above electro-optical device, the semiconductor layer of one of the two transistors connected in parallel overlaps one of two adjacent light-shielding patterns among the plurality of light-shielding patterns in a plan view on the first substrate. The other semiconductor layer of the two transistors arranged in parallel and connected in parallel is preferably arranged so as to overlap the other of the two adjacent light shielding patterns in a plan view on the first substrate.
According to this configuration, it is possible to block light incident on each of the semiconductor layers connected in parallel by adjacent light blocking patterns.

The electro-optical device described above is characterized in that at least one of the plurality of light shielding patterns is a power supply wiring.
According to this configuration, the power supply wiring can block light that enters the semiconductor layer of the transistor. In addition, it is possible to supply the necessary power to the drive circuit.

In the electro-optical device described above, the electro-optical element is a liquid crystal element, and includes a pixel electrode provided for each pixel on the first substrate, and a common electrode provided on the second substrate to which a common potential is applied. However, at least one of the plurality of light shielding patterns may be a common potential wiring.
According to this configuration, light entering the semiconductor layer of the transistor can be blocked by the common potential wiring. In addition, stabilization of the common potential required for driving pixels can be strengthened.

An electronic device of the present application is characterized by including the electro-optical device described above.
According to the present application, it is possible to downsize an electro-optical device and provide an electronic device with excellent cost performance.

10s...Base material as a first substrate, 15...Pixel electrode, 20s...Base material as a second substrate, 23...Counter electrode as a common electrode, 40...Photocurable sealing material, 50...As an electro-optical element Liquid crystal layer as a liquid crystal element, 100, 200...Liquid crystal device as an electro-optical device, 101...Data line drive circuit as a drive circuit, 102...Scanning line drive circuit as a drive circuit, 107...Common potential wiring, 1000...Electronic A projection type display device as a device, E3... seal area, P... pixel.

Claims (6)

a first portion extending in a first direction along the scanning line driving circuit; and a first portion extending in the first direction along the scanning line driving circuit;
a second portion extending in a second direction intersecting the first direction ;
a first transistor disposed at a position overlapping the sealing material in plan view;
a second transistor disposed at a position overlapping the sealing material in plan view;
a third transistor arranged at a position overlapping the sealing material in plan view;
a fourth transistor arranged at a position overlapping the sealing material in plan view;
a fifth transistor disposed at a position overlapping the sealing material in plan view;
a sixth transistor arranged at a position overlapping the sealing material in plan view;
a first wiring layer disposed between the first transistor and the second transistor and the sealing material;
a second wiring layer disposed between the third transistor and the fourth transistor and the sealing material;
a third wiring layer disposed between the fifth transistor and the sixth transistor and the sealing material;
Equipped with
the first transistor and the second transistor are arranged along the first direction,
The first transistor, the third transistor, and the fifth transistor are arranged along the second direction,
the third transistor and the fourth transistor are arranged along the first direction,
The second transistor, the fourth transistor, and the sixth transistor are arranged along the second direction,
The fifth transistor and the sixth transistor are arranged along the first direction,
The first wiring layer extends along the first direction so as to overlap the first transistor and the second transistor in a plan view,
The second wiring layer extends along the first direction so as to overlap the third transistor and the fourth transistor in a plan view,
The third wiring layer extends along the first direction so as to overlap the fifth transistor and the sixth transistor in a plan view,
a semiconductor layer of the third transistor, a semiconductor layer of the fourth transistor, and a semiconductor layer of the third transistor;
The semiconductor layer of the fifth transistor and the semiconductor layer of the sixth transistor are arranged in the second direction.
The electro-optical device has a length in the first direction that is longer than a length of the electro-optical device. The electro-optical device according to claim 1, wherein the first transistor and the second transistor are not electrically connected to the first wiring layer. The distance between the first wiring layer and the second wiring layer and the distance between the second wiring layer and the third wiring layer are wider than the width of the first wiring layer in the second direction. The electro-optical device according to claim 1 or 2 . the first transistor, the second transistor, the third transistor,
The fourth transistor, the fifth transistor, and the sixth transistor are:
The electro-optical device according to claim 1 , wherein the channel length directions are arranged along the same direction. The width of the second wiring layer in the second direction and the width of the third wiring layer in the second direction are equal to the width of the first wiring layer in the second direction . The electro-optical device according to any one of the items. An electronic device comprising the electro-optical device according to any one of claims 1 to 5 .

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