JP2013246228A - Manufacturing method for electro-optical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in which it is difficult to improve productivity of an electro-optical device by a conventional manufacturing method.SOLUTION: A manufacturing method for electro-optical device that forms at least a first electro-optical device and a second electro-optical device on a mother substrate comprises the steps of: forming wiring 123 constituting the first electro-optical device and wiring 123 constituting the second electro-optical device; forming common wiring 161 surrounding the first electro-optical device and common wiring that is electrically connected to the common wiring 161 and surrounds the second electro-optical device; and forming connection wiring electrically connecting the common wiring 161 and the wiring 123 and connection wiring electrically connecting the common wiring surrounding the second electro-optical device and the wiring 123 of the second electro-optical device. The step of forming the common wiring 161 and the common wiring surrounding the second electro-optical device includes a step of forming a resistance section 171 in the common wiring 161.

Description

  The present invention relates to a method for manufacturing an electro-optical device and the like.

One of the electro-optical devices is a liquid crystal device. In a liquid crystal device, liquid crystal is sandwiched between a pair of substrates facing each other. In such a liquid crystal device, there is a liquid crystal device in which a plurality of driving elements for controlling driving of liquid crystal for each pixel is formed on at least one of a pair of substrates. Hereinafter, the substrate on which the drive element is formed is referred to as an element substrate.
2. Description of the Related Art Conventionally, in a method for manufacturing an element substrate of a liquid crystal device, a manufacturing method is known in which common wiring (electrostatic countermeasure wiring) for short-circuiting various wirings such as a plurality of scanning lines and data lines is provided on the outer periphery of the element substrate. (For example, refer to Patent Document 1).

Japanese Patent Laid-Open No. 11-95257 (6th page, FIG. 6 and FIG. 7)

In the manufacturing method described in Patent Document 1, charges generated in various wirings due to charging can be diffused into the common wiring, and the driving elements and the like can be easily protected from static electricity.
However, in the above manufacturing method, charges generated in the common wiring may flow from the common wiring into the element substrate via various wirings. In this case, various wirings, driving elements, and the like may be damaged by charges flowing from the common wiring into the element substrate. For this reason, in the above manufacturing method, it is difficult to improve the yield rate of the electro-optical device.
In other words, the conventional manufacturing method has a problem that it is difficult to improve the productivity of the electro-optical device.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 A method for manufacturing an electro-optical device in which at least a first electro-optical device and a second electro-optical device are formed on a mother substrate, the first wiring configuring the first electro-optical device Forming a second wiring that constitutes the second electro-optical device; a first common wiring surrounding the first electro-optical device; and the first common wiring electrically connected A step of forming a second common wiring surrounding the second electro-optical device, a first connection wiring for electrically connecting the first common wiring and the first wiring, Forming a second connection wiring for electrically connecting the second common wiring and the second wiring, and in the step of forming the first and second common wiring, And a method of manufacturing an electro-optical device, including a step of forming a resistance portion in the common wiring

  In the manufacturing method of this application example, since the common wiring that surrounds the electro-optical device is formed in the step of forming the common wiring, the electro-optical device can be easily protected from static electricity. Further, in this manufacturing method, since the common wiring resistance portion is formed, the charge generated in the common wiring can be consumed by the resistance portion, so that the electro-optical device is further protected from static electricity from the charge generated in the common wiring. Therefore, the yield rate of the electro-optical device can be easily improved, and the productivity of the electro-optical device can be easily improved.

Application Example 2 In the above-described electro-optical device manufacturing method, the resistor is formed on at least one of the four sides of the first common wiring that surrounds the first electro-optical device. A method for manufacturing an electro-optical device.
In this application example, the resistance portion can be formed on at least one of the four sides of the common wiring.

  Application Example 3 In the above-described method for manufacturing an electro-optical device, the resistance portion is formed by making the cross-sectional area of a part of the first common wiring smaller than the other part. A method for manufacturing an electro-optical device.

  In this application example, the resistance portion can be formed by forming a partial cross-sectional area of the common wiring smaller than the other portions.

  Application Example 4 In the method of manufacturing the electro-optical device, the path per unit distance of a part of the first common wiring is made longer than the path per unit distance of the other part. A method of manufacturing an electro-optical device, comprising forming a resistance portion.

  In this application example, the resistance portion can be formed by making the path per unit distance of a part of the common wiring longer than the path per unit distance of the other part.

  Application Example 5 In the electro-optical device manufacturing method described above, the step of forming the first and second common wirings includes a photolithography step, and exposure is performed in one shot in the photolithography step. An electro-optical device manufacturing method, wherein at least one of the resistance portions is formed in a range.

  In this application example, since at least one resistance portion is formed in the exposure unit in the photolithography process, the charge generated in the common wiring can be consumed by the resistance portion. It is easy to avoid flowing in the wiring. As a result, the plurality of wirings can be more easily protected from static electricity.

  Application Example 6 A method for manufacturing an electro-optical device according to the above-described method, wherein the resistance value of the resistance portion is 1 kΩ or more and 1 MΩ or less.

  In this application example, the resistance value of the resistance portion can be 1 kΩ or more and 1 MΩ or less.

(A) is a schematic plan view which shows the structure of the liquid crystal device in this embodiment, (b) is a schematic sectional drawing in alignment with the H-H 'line | wire of the liquid crystal device shown to (a). FIG. 3 is a circuit diagram illustrating an electrical configuration of the liquid crystal device according to the present embodiment. FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of a pixel in the present embodiment. FIG. 3 is a cross-sectional view illustrating a schematic configuration of the liquid crystal device according to the embodiment. The top view explaining the mother board in this embodiment. The top view explaining common wiring in this embodiment. The top view which shows the example of the resistance part in this embodiment. The top view which shows the example of the resistance part in this embodiment. The figure explaining the structural example of the resistance part in this embodiment. FIG. 2 is a diagram illustrating a schematic configuration of a projector according to the present embodiment.

Embodiments will be described with reference to the drawings. In addition, in each drawing, in order to make each structure the size which can be recognized, the structure and the scale of a member may differ.
In the following description, for example, when “on the substrate” is described, the substrate is disposed so as to be in contact with the substrate, or is disposed on the substrate via another component, or is disposed on the substrate. It is assumed that a part is arranged so as to contact with and a part is arranged via another component.

  In the present embodiment, an active matrix liquid crystal device including a thin film transistor (TFT) as a pixel switching element will be described as an example of an electro-optical device. This liquid crystal device can be suitably used as, for example, a light modulation element (liquid crystal light valve) of a projection type display device (liquid crystal projector) described later.

<Liquid crystal device>
First, a liquid crystal device as an electro-optical device according to this embodiment will be described with reference to FIGS. 1 and 2. 1A is a schematic plan view showing the configuration of the liquid crystal device according to the first embodiment, and FIG. 1B is a schematic cross-sectional view taken along the line HH ′ of the liquid crystal device shown in FIG. . FIG. 2 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device according to the first embodiment.

  As shown in FIGS. 1A and 1B, a liquid crystal device 100 according to the present embodiment includes an element substrate 10 and a counter substrate 20 that are disposed to face each other, and a liquid crystal layer 50 that is sandwiched between the pair of substrates. . The element substrate 10 and the counter substrate 20 are made of, for example, a transparent quartz substrate or glass substrate.

  The element substrate 10 is larger than the counter substrate 20, and both the substrates are bonded via a sealing material 40 disposed along the outer edge of the counter substrate 20, and liquid crystal having positive or negative dielectric anisotropy is enclosed in the gap. Thus, the liquid crystal layer 50 is configured. As the sealing material 40, for example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed. A spacer (not shown) is mixed in the sealing material 40 to keep the distance between the pair of substrates constant.

  A pixel region E in which a plurality of pixels P are arranged is provided inside the sealing material 40. Further, a parting portion 21 is provided between the sealing material 40 and the pixel region E so as to surround the pixel region E. The parting portion 21 is made of, for example, a light shielding metal or metal oxide. The pixel region E may include dummy pixels arranged so as to surround the plurality of pixels P in addition to the plurality of pixels P contributing to display. Although not shown in FIG. 1, a light shielding portion (black matrix; BM) that divides a plurality of pixels P in a plane in the pixel region E is provided on the counter substrate 20.

  A data line driving circuit 101 is provided between the element substrate 10 and the sealing material 40 along the first side. In addition, an inspection circuit 103 is provided inside the sealing material 40 along the second side that faces the first side. Further, a scanning line driving circuit 102 is provided inside the sealing material 40 along the third and fourth sides that are orthogonal to the first side and face each other. A plurality of wirings 105 that connect the two scanning line driving circuits 102 are provided inside the sealing material 40 on the second side.

  Wirings connected to the data line driving circuit 101 and the scanning line driving circuit 102 are connected to a plurality of external connection terminals 104 arranged along the first side. In the following description, the direction along the first side is defined as the X direction, and the direction along the third side is defined as the Y direction. Note that the arrangement of the inspection circuit 103 is not limited to this, and the inspection circuit 103 may be provided at a position along the inner side of the sealant 40 between the data line driving circuit 101 and the pixel region E.

  As shown in FIG. 1B, on the surface of the element substrate 10 on the liquid crystal layer 50 side, a light-transmitting pixel electrode 15 provided for each pixel P and a thin film transistor (hereinafter referred to as TFT) as a switching element. 30), signal wirings, and an alignment film 18 covering them. In addition, a light shielding structure is employed that prevents light from entering the semiconductor layer in the TFT 30 to make the switching operation unstable. The element substrate 10 as a substrate in the present invention includes at least a base material 10s, a pixel electrode 15, a TFT 30, a signal wiring, and an alignment film 18 formed on the base material 10s.

  The counter substrate 20 disposed to face the element substrate 10 includes at least a base material 20s, a parting part 21 formed on the base material 20s, a planarization layer 22 formed so as to cover the part, and a planarization layer. 22 includes a common electrode 23 provided so as to cover 22 and an alignment film 24 covering the common electrode 23.

  The parting part 21 surrounds the pixel region E as shown in FIG. 1A and is provided at a position overlapping the scanning line driving circuit 102 and the inspection circuit 103 in plan view. Thus, the light incident on the peripheral circuit including these drive circuits from the counter substrate 20 side is shielded, and the peripheral circuit is prevented from malfunctioning due to the light. Further, unnecessary stray light is shielded from entering the pixel region E to ensure high contrast in the display of the pixel region E.

  The planarization layer 22 is made of an inorganic material such as silicon oxide, for example, and is provided so as to cover the parting portion 21 with light transmittance. As a method for forming such a planarizing layer 22, for example, a method of forming a film using a plasma CVD method or the like can be given.

  The common electrode 23 is made of, for example, a transparent conductive film such as ITO (Indium Tin Oxide), covers the planarization layer 22, and as shown in FIG. 1 (a), the vertical conduction portions 106 provided at the four corners of the counter substrate 20. Thus, the wiring is electrically connected to the wiring on the element substrate 10 side.

  The alignment film 18 covering the pixel electrode 15 and the alignment film 24 covering the common electrode 23 are selected based on the optical design of the liquid crystal device 100. For example, by depositing an organic material such as polyimide and rubbing the surface, an organic alignment film obtained by subjecting liquid crystal molecules having positive dielectric anisotropy to a substantially horizontal alignment process, or vapor phase growth Examples thereof include an inorganic alignment film formed by depositing an inorganic material such as SiOx (silicon oxide) using a method and substantially vertically aligning liquid crystal molecules having negative dielectric anisotropy.

  Such a liquid crystal device 100 is a transmission type, and adopts an optical design of a normally white mode in which the pixel P is brightly displayed when not driven and a normally black mode in which the pixel P is darkly displayed when not driven. Polarizing elements are arranged and used according to the optical design on the light incident side and the light exit side, respectively. In this embodiment, a normally black mode is employed.

Next, the electrical configuration of the liquid crystal device 100 will be described with reference to FIGS. As shown in FIG. 2, the liquid crystal device 100 drives the data line driving circuit 101, the scanning line driving circuit 102, the sampling circuit 70, and the like formed in the peripheral region located around the pixel region E on the element substrate 10. A circuit, a plurality of external connection terminals 104, and a plurality of wirings 123 are provided. The plurality of wirings 123 include a data line driving circuit wiring 114, a scanning line driving circuit wiring 121, and a plurality of image signal lines 111. Further, the plurality of wirings 123 include a pair of connection wirings 131, a pair of connection wirings 132, and a routing wiring 133 which will be described later.
The data line driving circuit wiring 114 is connected to the external connection terminal 104 and supplies power (VDDX, VSSX) and driving signals (DX, CLX, etc.) to the data line driving circuit 101. The scanning line driving circuit wiring 121 supplies power (VDDY, VSSY) and driving signals (DY, CLY, etc.) to the scanning line driving circuit 102. The plurality of image signal lines 111 supply image signals (VID1 to VID6) to the data line 6a via the sampling circuit 70.

  The data line driving circuit 101 is supplied with an X clock signal CLX (and an inverted X clock signal CLX) and an X start pulse DX from an external circuit via the external connection terminal 104 and the data line driving circuit wiring 114. When the X start pulse DX is input, the data line driving circuit 101 sequentially generates selection signals S1, S2,..., Sn at a timing based on the X clock signal CLX (and the inverted X clock signal CLX). Each is output to a plurality of selection signal supply lines 113.

  A Y clock signal CLY (and an inverted Y clock signal CLY) and a Y start pulse signal DY are supplied to the scanning line driving circuit 102 from an external circuit via the external connection terminal 104 and the scanning line driving circuit wiring 121. The scanning line driving circuit 102 sequentially generates scanning signals G1, G2,..., Gm based on these signals and outputs them to the plurality of scanning lines 3a.

  The sampling circuit 70 includes a plurality of sampling transistors (hereinafter referred to as S-TFTs) 71 composed of N-channel single-channel TFTs or complementary TFTs. The gates of the six S-TFTs 71 to which the six adjacent data lines 6a are connected are combined into one and connected to one selection signal supply line 113. That is, each selection signal S1, S2,..., Sn is supplied from the data line driving circuit 101 as six S-TFTs 71 as one unit (series). One of the six image signal lines 111 is connected via the connection wiring 112 to the sources of the six S-TFTs 71 constituting one unit (series). A data line 6 a is connected to the drain of the S-TFT 71. When the selection signals S1, S2,..., Sn are input, the sampling circuit 70 supplies the selection signals S1, S2, S2 to the data lines 6a corresponding to the six S-TFTs 71 constituting one unit (series). ..., image signals (VID1 to VID6) are sequentially supplied according to Sn.

  As shown in FIG. 2, the liquid crystal device 100 has a plurality of pixels P arranged in a matrix in the pixel region E occupying the central portion of the element substrate 10 as described above.

  As shown in FIG. 3, each of the plurality of pixels P includes a pixel electrode 15, a TFT 30 for controlling the switching of the pixel electrode 15, and a storage capacitor 16. A data line 6 a to which image signals (VID 1 to VID 6) are supplied is electrically connected to the source of the TFT 30. A scanning line 3 a to which scanning signals G 1, G 2,... Gm are supplied is connected to the gate of the TFT 30. One electrode of the pixel electrode 15 and the storage capacitor 16 is connected to the drain of the TFT 30. The other electrode of the storage capacitor 16 is connected to a capacitor line 3b arranged in parallel with the scanning line 3a.

As shown in FIG. 2, the capacitance line 3 b is drawn to the outside of the pixel region E in the X direction, and a pair of capacitance lines 3 b extends in the Y direction between the scanning line driving circuit 102 and the pixel region E. The connection wiring 131 is electrically connected. Each of the pair of connection wirings 131 is electrically connected to a pair of connection wirings 132 that electrically connect the vertical conduction parts 106 facing each other in the X direction among the four vertical conduction parts 106 provided at the corners of the counter substrate 20. Connected.
The pair of connection wirings 132 are electrically connected to each other via the common electrode 23 of the counter substrate 20 that is electrically connected to the vertical conduction part 106. Further, the connection wiring 132 positioned on the external connection terminal 104 side of the pair of connection wirings 132 is connected to a lead wiring 133 connected to the terminal 104 to which a common potential (LCCOM) is supplied. That is, the common potential (LCCOM) is applied to the capacitor line 3b.

  The selection signals S1, S2,..., Sn supplied to the S-TFT 71 having six sampling circuits 70 as one unit (series) may be sequentially supplied in this order, or six adjacent signals. The S-TFT 71 corresponding to the data line 6a may be supplied for each series. As shown in FIG. 2, in the present embodiment, the selection signals S1, S2,..., Sn correspond to the image signals (VID1 to VID6) serially and parallelly developed in six phases. , A group of six data lines 6a is supplied for each group (series). The number of phase expansion of the image signals (VID1 to VID6) (that is, the number of series of image signals that are serial-parallel-expanded) is not limited to 6 phases, for example, 9 phases, 12 phases, 24 phases, etc. The image signals expanded in a plurality of phases may be supplied to a set of data lines 6a in which the number corresponding to the expanded number is set as one set.

Scanning signals G1, G2,..., Gm are sequentially applied to the scanning line 3a in this order from the scanning line driving circuit 102 in a pulsed manner at a predetermined timing. As described above, the pixel electrode 15 is electrically connected to the drain of the TFT 30, and the TFT 30 is turned on for a certain period by the scanning signals G1, G2,..., Gm, and the image signal (from the data line 6a ( VID1 to VID6) are written to the pixel electrode 15 at a predetermined timing.
Further, in order to prevent the image signals (VID1 to VID6) held in each pixel P from leaking, a holding capacitor 16 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 15 and the common electrode 23. Yes.

  Image signals (VID1 to VID6) of a predetermined level written in the liquid crystal layer 50 (see FIG. 1B) through the pixel electrode 15 are held for a certain period with the common electrode 23 formed on the counter substrate 20. Is done. In the liquid crystal layer 50, the orientation and order of liquid crystal molecules change depending on the applied voltage level, and the light transmitted through the liquid crystal layer 50 is modulated to enable gradation display. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel P, resulting in dark display. In the normally black mode, the pixels are applied in units of each pixel P. Depending on the voltage, the transmittance for incident light is increased and bright display is performed. As a whole, display light having a contrast corresponding to the image signals (VID1 to VID6) is emitted from the liquid crystal device 100 and displayed. The image signals (VID1 to VID6) are configured by combining a potential pulse having a positive polarity and a potential pulse having a negative polarity with respect to the common potential (LCCOM) in order to drive the liquid crystal layer 50 with an alternating current. The The driving method of the liquid crystal device 100 as described above is called a phase expansion driving method. The driving method of the liquid crystal device 100 is not limited to the phase expansion driving method.

Next, the structure of the pixel P of the liquid crystal device 100, particularly the detailed wiring structure of the element substrate 10 and the alignment state of the liquid crystal molecules will be described with reference to FIG.
As shown in FIG. 4, the scanning line 3 a is first formed on the base material 10 s of the element substrate 10. The scanning line 3a is, for example, a simple metal or alloy containing at least one of metals such as Al (aluminum), Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). Further, metal silicide, polysilicide, nitride, or a laminate of these can be used and has light shielding properties.

A first insulating film (base insulating film) 11a made of, for example, silicon oxide is formed so as to cover the scanning lines 3a, and a semiconductor layer 30a is formed in an island shape on the first insulating film 11a. The semiconductor layer 30a is made of, for example, a polycrystalline silicon film, and an impurity ion is implanted to form an LDD structure having a first source / drain region, a junction region, a channel region, a junction region, and a second source / drain region. .
A second insulating film (gate insulating film) 11b is formed so as to cover the semiconductor layer 30a. Further, a gate electrode 30g is formed at a position facing the channel region with the second insulating film 11b interposed therebetween.

A third insulating film 11c is formed so as to cover the gate electrode 30g and the second insulating film 11b, and penetrates the second insulating film 11b and the third insulating film 11c at positions overlapping with respective end portions of the semiconductor layer 30a. Two contact holes CNT1 and CNT2 are formed.
Then, a conductive film is formed using a light-shielding conductive part material such as Al (aluminum) or an alloy thereof so as to fill the two contact holes CNT1 and CNT2 and to cover the third insulating film 11c, and pattern this. Thus, the source electrode 31 and the data line 6a connected to the first source / drain region through the contact hole CNT1 are formed. At the same time, the drain electrode 32 (first relay electrode 6b) connected to the second source / drain region via the contact hole CNT2 is formed.

Next, a first interlayer insulating film 12 is formed to cover the data line 6a, the first relay electrode 6b, and the third insulating film 11c. The first interlayer insulating film 12 is made of, for example, silicon oxide or nitride, and is subjected to a flattening process for flattening surface irregularities caused by covering the region where the TFT 30 is provided. Examples of the planarization method include chemical mechanical polishing (CMP) and spin coating.
A contact hole CNT3 penetrating the first interlayer insulating film 12 is formed at a position overlapping the first relay electrode 6b. A conductive film made of a light-shielding metal such as Al (aluminum) or an alloy thereof is formed so as to cover the contact hole CNT3 and the first interlayer insulating film 12, and is patterned to form the first The capacitor electrode 16a and the second relay electrode 16d are formed.

The insulating film 13b is patterned to cover the outer edge of the portion of the first capacitor electrode 16a that faces the second capacitor electrode 16c with the dielectric layer 16b formed later. Further, the insulating film 13b is formed by patterning so as to cover the outer edge of the second relay electrode 16d excluding the portion overlapping the contact hole CNT5.
A dielectric layer 16b is formed covering the insulating film 13b and the first capacitor electrode 16a. As the dielectric layer 16b, a silicon nitride film, a single layer film such as humic oxide (HfO ₂ ), alumina (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), or at least one of these single layer films is used. A multilayer film in which two types of single-layer films are stacked may be used. The portion of the dielectric layer 16b that overlaps the second relay electrode 16d in plan view is removed by etching or the like. A conductive film such as, for example, TiN (titanium nitride) is formed so as to cover the dielectric layer 16b. By patterning the conductive film, the second capacitive electrode is disposed opposite to the first capacitive electrode 16a and connected to the second relay electrode 16d. 16c is formed. The storage capacitor 16 is configured by the dielectric layer 16b, and the first capacitor electrode 16a and the second capacitor electrode 16c that are disposed to face each other with the dielectric layer 16b interposed therebetween.

Next, a second interlayer insulating film 14 that covers the second capacitor electrode 16c and the dielectric layer 16b is formed. The second interlayer insulating film 14 is also made of, for example, silicon oxide or nitride, and is subjected to a planarization process such as a CMP process. A contact hole CNT5 penetrating through the second interlayer insulating film 14 is formed so that the second capacitor electrode 16c reaches a portion in contact with the second relay electrode 16d.
A transparent conductive film (electrode film) such as ITO is formed so as to cover the contact hole CNT5 and cover the second interlayer insulating film 14. The transparent conductive film (electrode film) is patterned to form a pixel electrode 15 that is electrically connected to the second capacitor electrode 16c and the second relay electrode 16d through the contact hole CNT5.

The second capacitor electrode 16c is electrically connected to the drain electrode 32 of the TFT 30 via the second relay electrode 16d, the contact hole CNT3, and the first relay electrode 6b, and electrically connected to the pixel electrode 15 via the contact hole CNT5. Connected to.
The first capacitor electrode 16a is formed so as to straddle a plurality of pixels P, and functions as the capacitor line 3b in the equivalent circuit (see FIG. 3). Thereby, the potential applied to the pixel electrode 15 via the drain electrode 32 of the TFT 30 can be held between the first capacitor electrode 16a and the second capacitor electrode 16c.

  An alignment film 18 is formed so as to cover the pixel electrode 15, and an alignment film 24 is formed so as to cover the common electrode 23 of the counter substrate 20 disposed to face the element substrate 10 with the liquid crystal layer 50 interposed therebetween. As described above, the alignment films 18 and 24 are inorganic alignment films, and are formed of an assembly of columns 18a and 24a grown in a columnar shape by, for example, oblique deposition of an inorganic material such as silicon oxide from a predetermined direction. The liquid crystal molecules LC having negative dielectric anisotropy with respect to the alignment films 18 and 24 have a pretilt angle of 3 to 5 degrees in the inclination direction of the columns 18a and 24a with respect to the normal direction of the alignment film surface. Aligned substantially vertically with θp. When the liquid crystal layer 50 is driven by applying an AC potential between the pixel electrode 15 and the common electrode 23, the liquid crystal molecules LC behave (vibrate) so as to be inclined in the direction of the electric field generated between the pixel electrode 15 and the common electrode 23. To do.

In the present embodiment, the element substrate 10 is formed from a mother substrate 10M as shown in FIG. The mother substrate 10M has a size that covers the plurality of element substrates 10. In the mother substrate 10M, a region where the element substrate 10 is formed is assigned as a substrate formation region 10a. A plurality of substrate formation regions 10a are allocated to the mother substrate 10M. The plurality of substrate forming regions 10a are arranged in the X direction and the Y direction.
After forming the TFT 30, the pixel electrode 15, the alignment film 18 and the like in the state of the mother substrate 10M, the element substrate 10 is formed by dividing (scribing) the mother substrate 10M along the outer edge of the substrate formation region 10a. . At this time, the base material of the mother substrate 10M becomes the base material 10s.

As shown in FIG. 5, a gap is provided between two adjacent substrate formation regions 10a. In the mother substrate 10M, a common wiring 161 surrounding each substrate formation region 10a is formed. The common wiring 161 includes a first common wiring 161a extending in the X direction and a second common wiring 161b extending in the Y direction.
In the present embodiment, a plurality of first common wires 161a are arranged in the Y direction. A plurality of second common wires 161b are arranged in the X direction. A gap is provided between two adjacent first common wires 161a. Similarly, a gap is also provided between two adjacent second common wires 161b. The substrate formation region 10a is set in a region surrounded by two adjacent first common wires 161a and two adjacent second common wires 161b.

In each substrate forming region 10a, a plurality of wirings 123 are connected to a common wiring 161 as shown in FIG. Thereby, the plurality of wirings 123 are electrically connected to each other. In the present embodiment, the plurality of wirings 123 are connected to the first common wiring 161 a via the external connection terminals 104.
In the present embodiment, the common wiring 161 is provided on the same level as the gate electrode 30g. In the present embodiment, the common wiring 161 and the gate electrode 30g are each composed of p-type or n-type polysilicon. The common wiring 161 is formed in the same process as the gate electrode 30g.
In contrast, the wiring 123 and the external connection terminal 104 are provided in a layer different from the layer of the common wiring 161. For this reason, the external connection terminal 104 is connected to the first common wiring 161a through a contact hole (not shown) reaching the first common wiring 161a.

  According to the above configuration, the charge generated in the wiring 123 due to charging can be diffused to the common wiring 161, and the TFT 30 and the like can be easily protected from static electricity. However, the charge generated in the common wiring 161 may flow from the common wiring 161 into the element substrate 10 through the wiring 123. As a result, the wiring 123 and the TFT 30 may be damaged.

  Here, in the present embodiment, as shown in FIG. 6A, the resistance portion 171 is provided in the second common wiring 161 b. The resistance portion 171 has a higher electrical resistance than other portions of the second common wiring 161b. Since the charge generated in the common wiring 161 can be consumed by the resistance portion 171, the charge generated in the common wiring 161 can be easily prevented from flowing to the wiring 123. As a result, the plurality of wirings 123 can be more easily protected from static electricity.

As for the number of the resistance portions 171, it is sufficient that at least one resistance portion 171 is provided in the common wiring 161 surrounding one substrate formation region 10 a. Further, the place where the resistance portion 171 is provided is not limited to the second common wiring 161b, but may be the first common wiring 161a.
In the mother substrate 10M, a photolithography process is used to form the gate electrode 30g and the common wiring 161. The photolithography process is used for patterning the gate electrode 30g and the common wiring 161. Then, at least one resistance portion 171 is formed in an exposure unit in the photolithography process.

At this time, for example, as shown in FIG. 5B, when four adjacent substrate forming regions 10a are one exposure unit, the first common wiring sandwiched between the two adjacent substrate forming regions 10a. 161a is referred to as a first common wiring 161aC. The other two first common lines 161a are referred to as first common lines 161aD.
The second common wiring 161b sandwiched between two adjacent substrate formation regions 10a is referred to as a second common wiring 161bC, and the other two second common wirings 161b are referred to as second common wirings 161bD.
In this case, a method in which the resistance portion 171 is not provided in at least one of the first common wiring 161aC and the second common wiring 161bC can be employed. Thereby, for example, when the two first common wirings 161aD and the two second common wirings 161bD are destroyed due to destruction (disconnection) of the resistance portion 171 due to static electricity, the substrate formation region 10a is electrically It is possible to avoid a floating state.

The resistance value of the resistance portion 171 is preferably in the range of 1 kΩ or more and 1 MΩ or less. Note that the sheet resistance of other parts of the common wiring 161 excluding the resistance portion 171 is approximately 7Ω / μm ² .
When the resistance value of the resistance portion 171 is less than 1 kΩ, the charge generated in the common wiring 161 easily passes through the resistance portion 171. Further, when the resistance value of the resistance portion 171 exceeds 1 MΩ, the charge generated in the common wiring 161 easily flows to the wiring 123 side.
In the present embodiment, as the configuration of the resistance portion 171, the wiring width W of the second common wiring 161 b is set to the resistance portion 171 as shown in FIG. In this area, a narrowed configuration is adopted. Thereby, since the cross-sectional area of the 2nd common wiring 161b can be made small in the resistance part 171, the electrical resistance of the resistance part 171 can be made higher than another site | part.

The configuration of the resistance portion 171 is not limited to the configuration in which the wiring width W is narrowed. As the configuration of the resistance portion 171, for example, a configuration in which the thickness of the second common wiring 161 b is thinned in the region of the resistance portion 171 can be employed. Also with this configuration, since the cross-sectional area of the second common wiring 161b can be reduced in the resistance portion 171, the electrical resistance of the resistance portion 171 can be made higher than that of other portions.
Further, as the configuration of the resistance portion 171, for example, a configuration in which the second common wiring 161 b is swung as shown in FIG. 7 can be adopted. Accordingly, the distance per unit distance of the second common wiring 161b in the resistance part 171 can be made longer than the distance per unit distance of the other part, so that the electrical resistance per unit distance in the resistance part 171 is changed to other values. Can be higher than the site.

Further, as the configuration of the resistance portion 171, for example, as illustrated in FIG. 8, a configuration in which the material of the second common wiring 161 b is higher in the region of the resistance portion 171 than the material of other portions is also employed. Can be done.
In addition, a configuration in which the second common wiring 161b and the resistance portion 171 are provided in different layers can be employed. In this case, the second common wiring 161b and the resistance portion 171 are connected to each other through the contact hole CNT6 as shown in FIG. 9A. The configuration in which the second common wiring 161b and the resistance portion 171 are provided in different layers is the second common wiring as shown in FIG. 9B, which is a cross-sectional view taken along the line CC ′ in FIG. A structure in which the wiring 161b and the resistance portion 171 are separated from each other with an insulating layer 173 or the like interposed therebetween. And the 2nd common wiring 161b and the resistance part 171 are connected through the contact hole CNT6 provided in the insulating layer 173.
In the example shown in FIG. 9B, the resistance portion 171 is provided in the same layer as the semiconductor layer 30a (FIG. 4). In this case, the insulating layer 173 corresponds to the second insulating film (gate insulating film) 11b.

  In the example shown in FIG. 9B, the resistance portion 171 is provided on the lower side (the base material 10s side) than the second common wiring 161b. However, the hierarchical configuration of the second common wiring 161b and the resistance portion 171 is not limited to this. As a hierarchical configuration of the second common wiring 161b and the resistance portion 171, a configuration in which the second common wiring 161b is provided below the resistance portion 171 (on the base material 10s side) may be employed.

In the present embodiment, the liquid crystal constituting the liquid crystal layer 50 corresponds to the electro-optical material, the base material 10s corresponds to one substrate, the X direction corresponds to the first direction, and the Y direction corresponds to the second direction. ing.
In the present embodiment, in the process of manufacturing the element substrate 10, the substrate forming region 10 a is surrounded by the common wiring 161 that connects the plurality of wirings 123 to each other, so that the plurality of wirings 123 can be easily protected from static electricity.
Further, in this embodiment, since the resistance portion 171 having a higher electrical resistance than other portions is formed in a part of the common wiring 161, the charge generated in the common wiring 161 can be consumed. It is possible to easily prevent the generated charge from flowing through the plurality of wirings 123. As a result, the plurality of wirings 123 can be more easily protected from static electricity, so that the yield rate of the liquid crystal device 100 can be easily improved and the productivity of the liquid crystal device 100 can be easily improved.

  In the present embodiment, an example in which the substrate forming region 10a is surrounded by the square common wiring 161 in plan view is shown, but the shape of the common wiring 161 is not limited to a square. As the shape of the common wiring 161, for example, an arbitrary shape such as a polygon including a triangle or a pentagon, a shape including a curve in the triangle, or a circle may be employed.

<Electronic equipment>
An electronic apparatus using the liquid crystal device 100 will be described by exemplifying a projector that is one of the projection display devices.
As shown in FIG. 10, the projector 500 according to the present embodiment includes a polarization illumination device 501 arranged along the system optical axis L, two dichroic mirrors 503 and 505 as light separation elements, and three reflection mirrors 507. , 508, 509, five relay lenses 511, 512, 513, 514, 515, three transmissive liquid crystal light valves 517, 518, 519 as light modulating means, and a cross dichroic prism 521 as a light combining element, And a projection lens 523.

The polarization illumination device 501 includes a lamp unit 525 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 527, and a polarization conversion element 529.
The dichroic mirror 503 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 501. Another dichroic mirror 505 reflects the green light (G) transmitted through the dichroic mirror 503 and transmits the blue light (B).

The red light (R) reflected by the dichroic mirror 503 is reflected by the reflection mirror 507 and then enters the liquid crystal light valve 517 via the relay lens 515.
The green light (G) reflected by the dichroic mirror 505 enters the liquid crystal light valve 518 via the relay lens 514.
Blue light (B) transmitted through the dichroic mirror 505 is incident on the liquid crystal light valve 519 via a light guide system including three relay lenses 511, 512, and 513 and two reflecting mirrors 508 and 509.

  The liquid crystal light valves 517, 518, and 519 are disposed to face the incident surface of each color light of the cross dichroic prism 521. The color light incident on the liquid crystal light valves 517, 518, and 519 is modulated based on the video information (video signal) and emitted toward the cross dichroic prism 521. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected onto the screen 531 by the projection lens 523 which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valves 517, 518, and 519 are those to which the above-described liquid crystal device 100 is applied. Each of the liquid crystal light valves 517, 518, and 519 has a configuration in which the liquid crystal device 100 is disposed with a gap between a pair of polarizing elements 533 disposed in crossed Nicols on the incident side and the exit side of the colored light. ing.

Note that the electronic apparatus to which the liquid crystal device 100 is applied is not limited to the projector 500. The liquid crystal device 100 is, for example, a projection type HUD (head-up display), a direct-view type HMD (head-mounted display), an electronic book, a personal computer, a digital still camera, a liquid crystal television, a viewfinder type or a monitor direct-view type video. It can be suitably used as a display unit for information terminal devices such as recorders, car navigation systems, electronic notebooks, and POS.
The electro-optical device is not limited to the liquid crystal device 100, and an organic EL (Electro Luminescence) device can also be applied.

  DESCRIPTION OF SYMBOLS 10 ... Element substrate, 10s ... Base material, 10a ... Substrate formation area, 20 ... Counter substrate, 20s ... Base material, 30a ... Semiconductor layer, 30g ... Gate electrode, 50 ... Liquid crystal layer, 100 ... Liquid crystal device, 104 ... External connection Terminals 123, wiring 161, common wiring, 161 a first common wiring, 161 b second common wiring, 171 resistance unit, 500 projector, P pixel, E pixel region.

Claims (6)

An electro-optical device manufacturing method for forming at least a first electro-optical device and a second electro-optical device on a mother substrate,
Forming a first wiring constituting the first electro-optical device and a second wiring constituting the second electro-optical device;
Forming a first common wiring that surrounds the first electro-optical device, and a second common wiring that is electrically connected to the first common wiring and surrounds the second electro-optical device;
A first connection wiring that electrically connects the first common wiring and the first wiring; and a second connection wiring that electrically connects the second common wiring and the second wiring. And forming a process,
The step of forming the first and second common wirings includes a step of forming a resistance portion in the first common wirings.
A method of manufacturing an electro-optical device. The resistance portion is formed on at least one of the four sides of the first common wiring that surrounds the first electro-optical device.
The method of manufacturing an electro-optical device according to claim 1. Forming the resistance portion by making a cross-sectional area of a part of the first common wiring smaller than the other part;
The method of manufacturing an electro-optical device according to claim 1 or 2. Forming the resistance portion by making a path per unit distance of a part of the first common wiring longer than a path per unit distance of the other part;
The method of manufacturing an electro-optical device according to claim 1 or 2. The step of forming the first and second common wirings includes a photolithography step,
5. The electro-optical device manufacturing method according to claim 1, wherein at least one of the resistance portions is formed in a range exposed in one shot in the photolithography process. 6. Method. The resistance value of the resistance portion is 1 kΩ or more and 1 MΩ or less.
6. The method of manufacturing an electro-optical device according to claim 1, wherein

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