JP2004179436A - Laminated ceramic capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated ceramic capacitor where a delamination after burning can be prevented when a dielectric layer is made thin and the number of laminated layers is increased, and to provide a manufacturing method of the capacitor. <P>SOLUTION: The laminated ceramic capacitor 10 is provided with the laminated body 1 where first and second confronted inner electrode layers 3 and 4 and dielectric loading layers 12 for substantially eliminating a step due to thickness of the first and the second inner electrode layers 3 and 4 are installed between a plurality of the dielectric layers 2 and with a pair of outer electrodes 5 and 6 which are formed at ends of the laminated body 1 and are connected to the first and the second inner electrode layers 3 and 4. The size of the first inner electrode layer 3 is larger than that of the second inner electrode layer 4. <P>COPYRIGHT: (C)2004,JPO

Description

【００４８】
表に示すように、図２、３、４の製造方法では、第１の内部電極層となる導体パターン３の幅Ｗが、第２の内部電極層となる導体パターン４の幅ｗより大きい本実施例（試料番号１〜３）は、焼成後のデラミネーションが０／５００個、耐熱衝撃（ΔＴ）試験時のクラックが０／３００個となった。
【００４９】
また、本実施例（試料番号１〜３）について、未焼成状態の積層体各１００個について金属顕微鏡を用いて観察することにより。焼成前の密着不良発生数を確認したところ、全て密着不良数は０個だった。
【００５０】
これに対し、第１の内部電極層となる導体パターン３の幅寸法が、第２の内部電極層となる導体パターン４の幅寸法が同じである比較例（試料番号４）では、焼成後のデラミネーションが１０／５００個、耐熱衝撃（ΔＴ）試験時のクラックが３２／３００個となった。
【００５１】
これらの結果から、本発明は、第１の内部電極層となる導体パターン３の寸法が、第２の内部電極層となる導体パターン４の寸法より大きいため、焼成後のデラミネーション、耐熱衝撃（ΔＴ）試験時のクラックを防止できることがわかった。
【００５２】
【発明の効果】
本発明によれば、第１の内部電極層の外側辺間の幅Ｗが、第２の内部電極層の幅ｗより大きいため、誘電体層を薄層化して積層数を増加した場合にも、焼成後のデラミネーションを防止できる。
【図面の簡単な説明】
【図１】本発明の積層セラミックコンデンサを示す図であり、（ａ）外観斜視図、（ｂ）平面断面図、（ｃ）縦断面図である。
【図２】本発明の積層セラミックコンデンサの製造方法を示す各工程の断面図である。
【図３】本発明の他の実施の形態の積層セラミックコンデンサの製造方法により作製された大型積層体を示す断面図である。
【図４】本発明のさらに他の実施の形態の積層セラミックコンデンサの製造方法を示す各工程の断面図である。
【図５】従来の積層セラミックコンデンサを示す図であり、（ａ）外観斜視図、（ｂ）平面断面図、（ｃ）縦断面図である。
【図６】図５の積層セラミックコンデンサの製造方法を示す図であり、大型積層体の断面図である。
【図７】図６の積層セラミックコンデンサの製造方法の問題点を示す断面図である。
【符号の説明】
１０ 積層セラミックコンデンサ
１ 積層体
２ 誘電体層（セラミックグリーンシート）
３、４ 内部電極層（導体パターン）
５、６ 外部電極
１１ 大型積層体
１２ セラミックパターン
１３、１４ パターン非形成部
２０ 支持体（キャリアフィルム）[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer ceramic capacitor.
[0002]
[Prior art]
In recent years, as electronic devices have become smaller and denser, multilayer ceramic capacitors, which are typical ceramic components, have been required to be smaller and have higher capacitance. For this reason, dielectric layers and internal electrode layers have been made thinner and more multilayered. Is being promoted.
[0003]
In such a multilayer ceramic capacitor, as the dielectric layers are made thinner and more multilayered, the thickness of the internal electrode layer formed on the dielectric layer becomes relatively thick, and the portion where the internal electrode layer exists is formed. And the step due to the thickness of the internal electrode layer accumulates with the non-existing part, the adhesion between the dielectric layers at the part where the internal electrode layer is not formed becomes weak, and delamination and cracks are easily generated during firing There was a problem of becoming.
[0004]
In order to solve the above problems, a multilayer ceramic capacitor 40 as shown in FIG. 5 has been proposed. As shown in the figure, the multilayer ceramic capacitor 40 includes a multilayer body 31 and external electrodes 35 and 36 formed on a pair of end surfaces of the multilayer body 31. The laminate 31 is formed by laminating a plurality of dielectric layers 32, and between the dielectric layers 32, first and second internal electrode layers 33 and 34 facing each other, A dielectric filling layer 42 for substantially eliminating a step due to the thickness of the second internal electrode layers 33 and 34 is interposed. Specifically, the first and second internal electrode layers 33 and 34 have a substantially rectangular shape, and a side (one short side in the figure) connected to the external electrodes 35 and 36 is a connection side. The side that forms a pair with the connection side is the tip side, and the remaining pair of sides (a pair of long sides in the figure) is the outer side.
On the outer side of the first internal electrode layers 33 and 34, a dielectric filling layer 42 having substantially the same thickness as the first and second internal electrode layers 33 and 34 is disposed.
[0005]
External electrodes 35 and 36 are formed on a pair of opposed end surfaces of the multilayer body 31, respectively, and are electrically connected to connection sides of the first and second internal electrode layers 33 and 34, respectively.
[0006]
FIG. 6 shows a method of manufacturing the multilayer ceramic capacitor 40. In addition, each code is not distinguished before and after firing. FIG. 6 is a cross-sectional view of the large laminate 41 from which the unfired laminate 31 is extracted.
[0007]
As shown in the figure, the large-sized laminated body 41 is filled with a dielectric between conductive patterns (same reference numerals for convenience) serving as the first and second internal electrode layers 33 and 34 so as to be in contact with the conductive patterns 33 and 34. It is created by laminating a plurality of ceramic green sheets (with the same reference numerals for convenience) serving as the dielectric layer 32 on which the ceramic patterns (with the same reference numerals for convenience) serving as the layer 42 are formed (Japanese Patent Laid-Open No. 2000-311831, See JP-A-2001-76958).
[Patent Document 1]
JP-A-2000-311831 (page 5-8, FIG. 1-2)
[Patent Document 2]
JP 2001-76958 A (page 2-3, FIG. 2-3)
[0008]
[Problems to be solved by the invention]
However, as shown in FIG. 6, in a manufacturing method in which the conductor patterns 33 and 34 and the ceramic pattern 42 are formed so as to be in contact with each other, usually, the accuracy of screen printing for forming the ceramic pattern 42 is about 30 to 200 μm. As shown in FIG. 7, a part of the ceramic pattern 42 rides on the conductor patterns 33 and 34 due to a misregistration of the printing, which results in a step increase. Further, in order to meet the demand for cost reduction of the multilayer ceramic capacitor 40, the large-sized multilayer body 41 has been increased in area in the manufacturing process, so that the problem of misalignment due to printing has become more and more apparent. I was
[0009]
When the number of stacked layers is increased by making the dielectric layer 32 and the internal electrode layers 33 and 34 thinner, there is a problem that delamination after firing tends to occur due to a local increase in thickness due to displacement. Was.
[0010]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multilayer ceramic capacitor that can prevent delamination after firing even when the number of stacked layers is increased by thinning the dielectric layers. Is to do.
[0011]
[Means for Solving the Problems]
The present invention provides a laminate formed by laminating a plurality of dielectric layers,
First and second internal electrode layers each having a substantially rectangular shape and disposed between the dielectric layers of the laminate and facing each other, and having a pair of outer sides, a tip side, and a connection side;
A dielectric filling layer interposed between dielectric layers on the outer side of the first and second internal electrode layers;
A multilayer ceramic capacitor formed at both ends of the multilayer body and serving as a pair of external electrodes respectively connected to connection sides of the first and second internal electrode layers,
A width W between a pair of outer sides of the first internal electrode layer is set to be larger than a width w between a pair of outer sides of the second internal electrode layer. is there.
[0012]
In addition, a part of the dielectric filling layer on the outer side of the first internal electrode layer extends beyond the outer side of the first internal electrode layer within the range of (W−w) / 2, and Of the internal electrode layer.
[0013]
Further, the dielectric filling layer on the outer side of the second internal electrode layer is separated from the outer side of the second internal electrode layer, and the distance Ll is (W−w) / It is smaller than 2.
[0014]
[Action]
According to the present invention, the width W between the pair of outer sides of the conductor pattern serving as the first internal electrode layer is larger than the width w of the conductor pattern serving as the second internal electrode layer. For this reason, in the manufacturing method in which the first and second conductor patterns and the ceramic pattern are formed so as to be in contact with each other, a part of the ceramic pattern rides on the first and second conductor patterns due to printing misalignment. In this case, (when the first and second conductor patterns and the ceramic pattern are separated from each other on the opposite side), the climbed portions (separated portions) do not accumulate in the laminating direction. Steps in the outer side region can be reduced. Also, even when the number of laminations is increased by making the dielectric layers thinner, delamination after firing can be prevented.
[0015]
Further, even if the ceramic pattern serving as the dielectric filling layer is intentionally overlapped and coated on the conductor pattern serving as the first and second internal electrode layers, the conductor pattern serving as the first internal electrode layer may be covered. Since this covering region is located within the range of the displacement amount ΔW = (W−w) / 2 of the width of the first internal electrode layer and the second internal electrode layer, that is, the displacement amount on one outer side, Steps in the outer side regions of the first and second internal electrode layers can be effectively suppressed.
[0016]
Conversely, even when the conductor pattern serving as the first and second internal electrode layers and the ceramic pattern serving as the dielectric filling layer are intentionally separated from each other, the separation region located on the outer side of the second internal electrode layer is not removed. , The width of the first internal electrode layer and the width of the second internal electrode layer are formed within the range of the displacement amount ΔW = (W−w) / 2, that is, within the range of the displacement amount on one outer side. The step in the outer side region of the second internal electrode layer can be effectively suppressed.
[0017]
Thereby, the close contact between the upper and lower ceramic green sheets is improved, so that delamination after firing can be prevented.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the multilayer ceramic capacitor of the present invention will be described with reference to the drawings.
[0019]
FIG. 1 is a view showing a multilayer ceramic capacitor of the present invention, in which (a) is an external perspective view, (b) is a plan sectional view, and (c) is a longitudinal sectional view. FIG. 2 is a process chart showing a method for manufacturing the multilayer ceramic capacitor of FIG.
[0020]
In FIG. 1, a multilayer ceramic capacitor 10 includes a multilayer body 1 and external electrodes 5 and 6 formed on a pair of end surfaces of the multilayer body 1. The laminate 1 is formed by laminating a plurality of dielectric layers 2, and between the dielectric layers 2, first and second internal electrode layers 3 and 4 facing each other, and a first and a second A dielectric filling layer 12 for substantially eliminating a step due to the thickness of the internal electrode layers 3 and 4 is provided. Here, the first internal electrode layer 3 and the second internal electrode layer 4 have a substantially rectangular shape, and the four sides are a pair of outer sides (long sides in FIG. 1B). , The connection side, and the tip side (both are short sides in FIG. 1B). The distance (width W) between the pair of outer sides of the first internal electrode layer 3 is set to be larger than the distance (width w) between the pair of outer sides of the second internal electrode layer 4. I have.
[0021]
External electrodes 5 and 6 are formed on a pair of opposed end surfaces of the multilayer body 1, respectively, and are electrically connected to the connection sides of the first and second internal electrode layers 3 and 4.
[0022]
Next, a method for manufacturing the multilayer ceramic capacitor 10 of the present invention will be described. Note that, in the drawings, each symbol is not distinguished before and after firing.
[0023]
As shown in FIG. 2A, first, a ceramic slurry is applied to a support (carrier film) 20 to form a ceramic green sheet (same reference numeral for convenience) serving as the dielectric layer 2.
[0024]
Next, as shown in FIG. 2 (b), a conductive pattern is printed on one main surface of the ceramic green sheet 2a to form a first internal electrode layer 3 (the same reference numeral is attached for convenience). Form. This conductive paste is composed of a metal particle, an organic solvent composed of a mixture of an aliphatic hydrocarbon and a higher alcohol, an organic binder composed of ethyl cellulose soluble in the organic solvent, and a poorly soluble organic solvent. And an organic binder made of an epoxy resin.
[0025]
Next, as shown in FIG. 2C, a width L _{1 of} 10 μm or more from the outer side of the conductor pattern 3 is provided between the conductor patterns 3 (portion on the outer side of the first internal electrode layer 3). Then, a ceramic pattern (with the same reference numeral for convenience) serving as the dielectric filling layer 12 is formed with the pattern non-forming portions 13 separated from each other.
Thus, the formed ceramic green sheet is peeled from the support body 20 to obtain the ceramic green sheet on which the conductor pattern 3 and the ceramic pattern 12 to be the first internal electrode layer are formed. Similarly, through the steps of FIGS. 2A to 2C, a ceramic green sheet on which a conductor pattern to be the second internal electrode layer 4 (described with the same reference numerals for convenience) and a ceramic pattern 12 are formed.
Next, as shown in FIG. 2D, a ceramic green sheet 2 on which a conductor pattern 3 serving as a first internal electrode layer is formed, and a ceramic green sheet 2 on which a conductor pattern 4 serving as a second internal electrode layer is formed. The large sheets 11 are obtained by sequentially laminating the green sheets 2.
[0026]
In addition, the width w between the pair of outer sides of the conductor pattern 4 serving as the second internal electrode layer is smaller than the width W of the conductor pattern 3 serving as the first internal electrode layer. Then, on the outer side of the conductor pattern 4, a ceramic pattern 12 serving as a dielectric filling layer having a pattern non-forming portion 14 separated by 10 μm or more (width L ₁ ) is formed. Here, a portion of the ceramic pattern 12 by the position deviation of the printing in order to prevent the ride on the conductor pattern 3 and 4, it is preferable width L ₁ of the pattern non-formation portions 13, 14 is 10μm or more .
[0027]
As the binder composition of the ceramic paste, both the same composition as the conductive paste or a different composition can be applied. In particular, the same conditions as in the printing of the conductive paste can be employed, and the binder from the surface of the ceramic green sheet 2 can be used. It is desirable that the ceramic paste has the same binder composition as the conductive paste, because the volatilization rates of the ceramic pastes are matched.
[0028]
Further, as the ceramic powder composition used for the ceramic slurry, both the powder composition of the ceramic green sheet 2 and the ceramic paste having a different powder composition can be applied. However, the adhesion between the ceramic green sheet 2 and the ceramic pattern is enhanced, and the firing shrinkage rate is increased. It is desirable that the ceramic paste has the same powder composition as the ceramic slurry forming the ceramic green sheet 2 because of the following.
[0029]
Thereafter, the large-sized laminate 11 is cut for each element region to obtain the unfired laminate 1.
[0030]
Further, the unfired laminate 1 is fired under predetermined atmosphere and temperature conditions to obtain the laminate 1. In the laminate 1, a plurality of dielectric layers 2 and internal electrode layers 3, 4 are laminated, and the internal electrode layers 3, 4 are exposed on a pair of end surfaces.
[0031]
Next, conductor films 5 and 6 serving as external electrodes are formed on a pair of end surfaces of the laminate 1 by a dipping method. Further, the conductor film is fired by applying a predetermined atmosphere, temperature and time to form the external electrodes 5 and 6. Then, Ni plating / Sn plating is formed on the surfaces of the external electrodes 5 and 6.
[0032]
Thus, a multilayer capacitor 10 as shown in FIG. 1 is obtained.
[0033]
Thus, according to the present invention, the ceramic which becomes the dielectric filling layer between the conductor patterns 3 and 4 which become the first and second internal electrode layers and is separated from the first and second conductor patterns 3 and 4 Since the pattern 12 is interposed, it is possible to prevent a part of the ceramic pattern 12 from riding on the first and second conductor patterns 3 and 4 due to misregistration of printing.
[0034]
Further, since the pattern non-formed portions 13 and 14 are shifted without being continuous in the laminating direction, the close contact between the upper and lower ceramic green sheets 2 of the pattern non-formed portions 13 and 14 is improved, so that the delamination after firing is reduced. Can be prevented.
[0035]
For example, in FIG. 2D, the pattern non-formed portion 14 in the outer side region of the conductor pattern 4 to be the second internal electrode layer is formed by the pattern non-formed portion formed in the conductor pattern 3 to be the first internal electrode layer. The width displacement ΔW (ΔW is the displacement of the outer side on one side) between the conductor pattern 3 serving as the first internal electrode layer and the conductor pattern 4 serving as the second internal electrode layer so as not to overlap the portion 13 in the thickness direction. And (W−w) / 2). That is, the conductor pattern 3 serving as the first internal electrode layer overlaps the pattern non-formed portion 14 in the thickness direction.
[0036]
Further, the non-pattern forming portion 13 in the outer side region of the conductor pattern 3 serving as the first internal electrode layer has a dielectric layer in the thickness direction as long as the above-mentioned non-pattern forming portion 14 is formed within the range of the displacement ΔW. The second ceramic green sheet is located.
[0037]
In other words, even if misalignment of the stack occurs, the pattern non-formed portions 13 and 14 in the outer side regions of the conductor patterns 3 and 4 serving as the first and second internal electrode layers are intentionally formed. Since the non-pattern forming portions 13 and 14 do not overlap with each other, a step in the outer side regions of the first and second internal electrode layers 3 and 4 can be effectively suppressed. Thereby, the close contact between the upper and lower ceramic green sheets is improved, so that delamination after firing can be prevented.
[0038]
Furthermore, according to the above-described manufacturing method, since the conductor patterns 3 and 4 can be formed on the main surface of the flat ceramic green sheet 2, the precision of forming the conductor patterns 3 and 4 is improved, and the capacitance variation can be reduced, and the lamination can be performed. Even if the number is increased, the precision of forming the conductor patterns 3 and 4 is not affected, so that the multilayer ceramic capacitor 10 can be highly laminated and large in size.
[0039]
It should be noted that the present invention is not limited to the above embodiments, and various changes and improvements can be made without departing from the spirit of the present invention.
[0040]
FIG. 3 is a cross-sectional view showing a large-sized laminated body 11 manufactured by a manufacturing method according to another embodiment of the present invention. According to the drawing, the first and second conductor patterns 3 and 4 are formed so as to be in contact with (partially covered by) the ceramic pattern 12. Since the width W of the conductive pattern 3 serving as the first internal electrode layer is larger than the width w of the conductive pattern 4 serving as the second internal electrode layer, as shown in FIG. Therefore, even when a part of the ceramic pattern 12 rides on the first and second conductor patterns 3 and 4, the stepped part can be reduced because the part on which the ceramic pattern 12 rides is shifted without being continuous in the laminating direction. Then, even when the number of layers is increased by making the dielectric layer 2 thinner, delamination after firing can be prevented.
[0041]
Also, when a part of the ceramic pattern 12 to be the dielectric filling layer 12 is intentionally coated from the outer side to the inner side of the conductor pattern 4 to be the first internal electrode layer, the first and second ceramic patterns are also required. The conductor pattern 3 to be the first internal electrode layer and the conductor pattern to be the second internal electrode layer so that the covering patterns formed on the conductor patterns 3 and 4 serving as the internal electrode layers do not overlap in the thickness direction. 4, the width displacement ΔW (ΔW is a displacement amount of the outer side on one side and becomes (W−w) / 2). As a result, even if a part of the ceramic pattern serving as the dielectric filling layer 12 is covered near the outer sides of the conductor patterns 3 and 4 serving as the first and second internal electrode layers, they do not overlap with each other. Steps near the outer sides of the second internal electrode layers 3 and 4 can be effectively suppressed. Thereby, the close contact between the upper and lower ceramic green sheets is improved, so that delamination after firing can be prevented.
[0042]
FIG. 4 is a process chart of another embodiment for manufacturing the multilayer ceramic capacitor 10 of the present invention. A step of mounting the ceramic green sheet 2a on the support 20 as shown in FIG. 4A, and a step of printing a conductive paste on the main surface of the ceramic green sheet 2a as shown in FIG. 4C, a step of forming a plurality of conductive patterns 3 at predetermined intervals, a step of printing ceramic paste around the conductive patterns 3 to form a ceramic pattern 12 as shown in FIG. 4) mounting another ceramic green sheet 2b on the ceramic green sheet 2a on which the ceramic pattern 12 and the conductor pattern 3 are formed, as shown in FIG. By repeating the process of forming the ceramic pattern 12 and the conductor pattern 4 on the surface, as shown in FIG. It is produced. According to this manufacturing method, the lamination accuracy is improved, the capacitance variation can be reduced, and the side margin and the end margin can be reduced, so that the multilayer ceramic capacitor can be downsized. Further, in the step shown in FIG. 4D, another ceramic green sheet 2b lined with a film is placed on the ceramic green sheet 2a on which the ceramic pattern 12 and the conductor pattern 3 are formed, and the ceramic green sheet 2b is applied from the film side. The ceramic green sheet 2b may be laminated on the ceramic green sheet 2a by pressure heating. Thus, there is no need to provide a step of adsorbing the ceramic green sheets 2b, so that defects in the ceramic green sheets 2b can be prevented.
[0043]
Further, in the above embodiment, the present invention is described using an example in which the present invention is applied to a method of manufacturing a multilayer ceramic capacitor 10. However, the present invention is applicable to a method of manufacturing any other multilayer ceramic component such as an electronic component or a semiconductor component. Applicable to
[0044]
The inventor manufactured multilayer ceramic capacitors 10 and 40 using the manufacturing method of the present invention (FIGS. 2, 3, and 4) and the manufacturing method of the comparative example (FIG. 6). The manufacturing method shown in FIGS. 3 and 6 is obtained by manufacturing the laminates 11 and 41 having the structures shown in FIGS. 3 and 6 by the manufacturing method shown in FIG. The obtained sample was examined for delamination after firing and cracks during a thermal shock (ΔT) test.
[0045]
The number of delaminations after firing was confirmed by polishing each of the fifty samples after firing from the end face and side face, and observing them with a metallographic microscope.
[0046]
The number of cracks during the thermal shock (ΔT) test was confirmed by immersing 300 fired samples in a solder layer at 280 ° C. for 2 seconds and observing them using a metallographic microscope.
[0047]
[Table 1]

[0048]
As shown in the table, in the manufacturing method of FIGS. 2, 3, and 4, the width W of the conductor pattern 3 serving as the first internal electrode layer is larger than the width w of the conductor pattern 4 serving as the second internal electrode layer. In Examples (Sample Nos. 1 to 3), the number of delaminations after firing was 0/500, and the number of cracks in the thermal shock (ΔT) test was 0/300.
[0049]
Moreover, about this Example (sample number 1-3), by observing using a metallurgical microscope about 100 each of the laminated bodies of an unfired state. When the number of occurrences of adhesion failure before firing was confirmed, the number of adhesion failures was all zero.
[0050]
On the other hand, in the comparative example (sample No. 4) in which the width dimension of the conductor pattern 3 serving as the first internal electrode layer and the width dimension of the conductor pattern 4 serving as the second internal electrode layer are the same, The number of delaminations was 10/500, and the number of cracks during the thermal shock (ΔT) test was 32/300.
[0051]
From these results, according to the present invention, the dimensions of the conductor pattern 3 serving as the first internal electrode layer are larger than the dimensions of the conductor pattern 4 serving as the second internal electrode layer. ΔT) It was found that cracks during the test could be prevented.
[0052]
【The invention's effect】
According to the present invention, since the width W between the outer sides of the first internal electrode layer is larger than the width w of the second internal electrode layer, even when the number of stacked layers is increased by making the dielectric layer thinner, In addition, delamination after firing can be prevented.
[Brief description of the drawings]
FIG. 1 is a view showing a multilayer ceramic capacitor of the present invention, in which (a) is an external perspective view, (b) is a plan sectional view, and (c) is a longitudinal sectional view.
FIG. 2 is a cross-sectional view of each step showing a method for manufacturing a multilayer ceramic capacitor of the present invention.
FIG. 3 is a cross-sectional view illustrating a large-sized laminate manufactured by a method for manufacturing a multilayer ceramic capacitor according to another embodiment of the present invention.
FIG. 4 is a cross-sectional view of each step showing a method for manufacturing a multilayer ceramic capacitor according to still another embodiment of the present invention.
FIG. 5 is a view showing a conventional multilayer ceramic capacitor, in which (a) is an external perspective view, (b) is a plan sectional view, and (c) is a longitudinal sectional view.
FIG. 6 is a sectional view of a large-sized laminated body, illustrating a method for manufacturing the multilayer ceramic capacitor of FIG. 5;
FIG. 7 is a cross-sectional view showing a problem in a method of manufacturing the multilayer ceramic capacitor of FIG.
[Explanation of symbols]
10 multilayer ceramic capacitor 1 multilayer 2 dielectric layer (ceramic green sheet)
3, 4 Internal electrode layer (conductor pattern)
5, 6 external electrode 11 large laminated body 12 ceramic pattern 13, 14 non-patterned portion 20 support (carrier film)

Claims (3)

A laminate formed by laminating a plurality of dielectric layers,
First and second internal electrode layers each having a substantially rectangular shape and disposed between the dielectric layers of the laminate and facing each other, and having a pair of outer sides, a tip side, and a connection side;
A dielectric filling layer interposed between dielectric layers on the outer side of the first and second internal electrode layers;
A multilayer ceramic capacitor formed at both ends of the multilayer body and serving as a pair of external electrodes respectively connected to connection sides of the first and second internal electrode layers,
The width W between the pair of outer sides of the first internal electrode layer is set to be larger than the width w between the pair of outer sides of the second internal electrode layer. A part of the dielectric filling layer on the outer side of the first internal electrode layer extends beyond the outer side of the first internal electrode layer within a range of (W−w) / 2 to a first inner side. 2. The multilayer ceramic capacitor according to claim 1, wherein a part of the electrode layer is covered. The dielectric filling layer on the outer side of the second internal electrode layer is separated from the outer side of the second internal electrode layer, and the distance Ll is (W−w) / 2. The multilayer ceramic capacitor according to claim 1, wherein

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