JP2004177532A - Electronic equipment equipped with cascade connection circuit, and circuit thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely transfer start signals between data side drivers connected in cascade manner. <P>SOLUTION: The start signal is supplied in parallel to each data side driver 40. When an enable signal EN is supplied to an input terminal 43 of an initial stage data side driver 40, the start signal is read with an inside start signal read circuit 42, is supplied to a data input terminal (D) of an initial stage flip-flop 45, and is sampled by the rise of the pulse of an inside clock signal CLKB, to successively transfer each flip-flops 45. The enabling signal EN to a next stage data side driver 40 is output to an output terminal 44 from a regular output terminal (Q) of the single-stage flip-flop 45. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a cascade connection circuit and an electronic device having the cascade connection circuit, and more particularly to a cascade connection circuit for sequentially reading start signals into a plurality of semiconductor integrated circuit devices and an electronic device having the cascade connection circuit.
[0002]
[Prior art]
As a dot matrix type display device, the liquid crystal display device is used for various devices such as personal computers because of its features of thinness, light weight and low power, and it is particularly advantageous for controlling the image quality with high definition. Display devices dominate.
[0003]
As shown in FIG. 6, a liquid crystal display module of this type of liquid crystal display device includes a liquid crystal panel (LCD panel) 1 and a control circuit (hereinafter, referred to as a controller) 2 including a semiconductor integrated circuit device (hereinafter, referred to as an IC). , A plurality of scan-side drive circuits (hereinafter, referred to as scan-side drivers) 3 and data-side drive circuits (hereinafter, referred to as data-side drivers) 4 composed of ICs. Although not shown in detail, the liquid crystal panel 1 has a semiconductor substrate on which a transparent pixel electrode and a thin film transistor (TFT) are arranged, a counter substrate on which one transparent electrode is formed on the entire surface, and these two substrates facing each other. A predetermined voltage is applied to each pixel electrode by controlling a TFT having a switching function, and the transmittance of the liquid crystal is determined by a potential difference between each pixel electrode and a counter substrate electrode. The image is displayed by changing it. On the semiconductor substrate, a data line for transmitting a gradation voltage to be applied to each pixel electrode and a scanning line for transmitting a switching control signal (scanning signal) for the TFT are wired.
[0004]
The controller 2 has an input side connected to a PC (personal computer) 5 and an output side connected to the scanning side driver 3 and the data side driver 4. Output sides of the scanning driver 3 and the data driver 4 are connected to scanning lines and data lines of the liquid crystal panel 1, respectively. The chip size of the scanning driver 3 and the data driver 4 is limited due to manufacturing restrictions. Therefore, the number of outputs corresponding to the scanning lines and data lines that can be output by one IC is also limited, and the size of the liquid crystal panel 1 is large. In this case, it is necessary to arrange a plurality of each on the outer periphery of the liquid crystal panel 1. For example, in the case of a liquid crystal panel of XGA (1024 × 768 pixels) color display, mounting of the drivers 3 and 4 on the module is as follows.
{Circle around (1)} The scanning driver 3 needs to drive 768 gate lines. For example, if it has a driving capability of 192 gates, it requires four, and is arranged on one side of the liquid crystal panel 1 in a cascade connection on the left outer periphery. You.
{Circle around (2)} The data side driver 4 needs three data lines for R (red), G (green), and B (blue) in order to display one pixel in color, so that 1024 × 3 = 3072 lines It is necessary to drive the data lines. For example, when the data lines have a driving capability of 384 lines, eight (A, B,..., H) of the cascade connection are arranged on one side on the upper outer periphery of the liquid crystal panel 1.
[0005]
Image data is sent from the PC 5 to the controller 2 of the liquid crystal display module, a clock signal and the like are sent from the controller 2 to the scanning driver 3 in parallel with each scanning driver 3, and a start signal STV for vertical synchronization is sent to the first stage. The data is sent to the scanning driver 3 and sequentially transferred to the scanning driver 3 in the cascade connection and subsequent stages. Further, a timing signal such as a clock signal CLK and a data signal DATA are sent from the controller 2 to the data side driver 4 in parallel to each data side driver 4, and a start signal STH for horizontal synchronization is transmitted to the first stage data side driver A. , And are sequentially transferred to data drivers B, C,... Then, a pulse-like scanning signal is sent from the scanning driver 3 to each scanning line, and when the scanning signal applied to the scanning line is at a high level, all the TFTs connected to that scanning line are turned on, The gray scale voltage sent from the driver 4 to the data line is applied to the pixel electrode via the turned-on TFT. Then, when the scanning signal becomes low level and the TFT changes to the off state, the potential difference between the pixel electrode and the counter substrate electrode is held until the next gradation voltage is applied to the pixel electrode. Then, by sequentially transmitting a scanning signal to each scanning line, a predetermined gradation voltage is applied to all the pixel electrodes, and an image can be displayed by rewriting the gradation voltage in a frame cycle.
[0006]
The data side driver 4 needs to be driven with a small cascade output delay in order to sequentially transfer the start signal STH by cascade connection, and the present applicant has applied for a data side driver having this kind of improvement ( See Patent Document 1.). Hereinafter, a circuit for sequentially transferring the start signal STH by cascade connection included in the conventional data-side driver 4 will be described with reference to FIG. The data side driver 4 is a circuit for sequentially transferring the start signal STH by cascade connection, and includes an input terminal 6 for an external clock signal CLKA, an input terminal 7 for a start signal STH, an output terminal 8 for a start signal STH, and an input terminal 6 And a shift register 10 having a clock signal input / output circuit 9 having a clock stop circuit for delaying the external clock signal CLKA supplied to the internal clock signal CLKA by a predetermined time td1 and outputting the internal clock signal CLKB.
[0007]
The shift register 10 has, for example, a 64-stage flip-flop. The first stage has a first-stage flip-flop 11, and the second to 63-th stages have intermediate-stage flip-flops 12, 12,..., 12, 12, and 64. Has a flip-flop 13 at the last stage. The clock input terminal (C) of each of the flip-flops 11 and 12 of the first stage and the intermediate stage is connected to the input terminal 6 via the input / output circuit 9. The data input terminal (D) of the first-stage flip-flop 11 is connected to the input terminal 7, and the data input terminal (D) of each intermediate-stage flip-flop 12 is a regular output terminal of the preceding flip-flop 11, 12 ( Q). Complementary output terminals (Q bar) of the flip-flops 11 and 12 of the first stage and the intermediate stage are respectively connected to respective registers of a data register circuit (not shown) provided in correspondence with the flip-flops 11 and 12. The last-stage flip-flop 13 is divided into a first flip-flop 13a and a second flip-flop 13b, and the clock input terminal (C) of the first flip-flop 13a is connected to the input terminal 6 via the input / output circuit 9. The data input terminal (D) is provided at the normal output terminal (Q) of the 63rd stage flip-flop 12 and the complementary output terminal (Q bar) is provided corresponding to the flip-flop 13a. The clock input terminal (C) of the second flip-flop 13b is directly connected to the input terminal 6 and the data input terminal (D) of the second flip-flop 13b without the intervention of the input / output circuit 9. The terminal (Q) and the regular output terminal (Q) are connected to the output terminal 8, respectively.
[0008]
The operation of the above configuration circuit will be described with reference to FIG. When the external clock signal CLKA is supplied to the input terminal 6, the flip-flops 11 and 12 of the first stage and the intermediate stage of the shift register 10 and the first flip-flop of the last stage are provided as an internal clock signal CLKB via the input / output circuit 9. 13a and directly to the second flip-flop 13b at the final stage. When the start signal STH is supplied to the input terminal 7 in this state, the start signal STH is sampled and transferred by the internal clock signal CLKB in order from the first stage flip-flop 11 to the last stage first flip-flop 13a, and is transferred to the first stage. And a control signal for taking in a data signal from the intermediate stage flip-flops 11 and 12 and the final stage first flip-flop 13a to a data register circuit (not shown) at the subsequent stage, and transfer from the 63-stage flip-flop 12. The signal is transferred to the second flip-flop 13b at the last stage, sampled directly by the external clock signal CLKA, and the start signal of the data-side driver 4 cascaded from the second flip-flop 13b at the last stage to the next stage. The signal is output to the output terminal 8 as STH.
[0009]
Therefore, the delay time (hereinafter referred to as cascade delay time) td with respect to the external clock signal CLKA when the start signal STH, which is the output of the second flip-flop 13b in the last stage, is input to the data driver 4 in the next stage. Since the delay time td1 of the internal clock signal CLKB with respect to the external clock signal CLKA is not added, and only the delay time td2 due to the parasitic resistance and the parasitic capacitance between the cascaded data-side drivers 4 is added, the cascade delay time td = td2.
[0010]
As described above, the last flip-flop 13 in the shift register 10 is connected to the first flip-flop 13a to which the internal clock signal CLKB is input to the clock input terminal (C) and the external clock to the clock input terminal (C). The signal CLKA is directly input, and the normal output terminal (Q) is divided into a flip-flop 13b connected to the output terminal 8 so that the signal output timing to the output terminal 8 can be directly synchronized with the external clock signal CLKA. Thus, the cascade delay time td can be shortened. The maximum clock frequency at the time of cascade connection (hereinafter abbreviated as fmax) is determined by the signal read time ts between the data side drivers 4 and the cascade delay time td, and is expressed by the following equation (1). Can be increased, fmax can be increased.
fmax = 1 / (ts + td) (1)
[0011]
[Patent Document 1]
JP-A-9-281924
[Problems to be solved by the invention]
By the way, the data driver 4 is supplied to the input terminal 6 when the start signal STH is read at the rising edge of the clock signal by the data drivers B, C,... If the external clock signal CLKA is directly used as it is, it is necessary to read at the rising edge of the pulse b. However, depending on the magnitude of the delay time td2 of the start signal STH between the data side drivers 4, the original read signal may be used. Cannot be read at the rising edge of the pulse b, and may be read at the rising edge of the next pulse c. Therefore, taking the delay time td2 of the start signal STH into consideration, the external clock signal CLKA is Reading is performed at the rising edge of the pulse b 'of the internal clock signal CLKB delayed by td1. However, as the size of the liquid crystal panel 1 further increases in the future and the number of pixels increases, higher-speed operation is required. Accordingly, the ratio of the delay time td2 of the start signal STH to the pulse width of the clock signal CLKB increases, When reading is performed at the rising edge of the internal clock signal CLKB, there is a possibility that reading may be performed at the rising edge of the next next pulse c ′, and transfer of the start signal STH between the data side drivers 4 may be uncertain. There's a problem.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a cascade connection circuit in which the transfer of a start signal STH is reliably performed between a plurality of cascade-connected semiconductor integrated circuit devices, and an electronic device including the circuit.
[0013]
[Means for Solving the Problems]
In the cascade connection circuit of the present invention, a start signal is sequentially read into a plurality of cascade-connected semiconductor integrated circuit devices, and the start signal is read into a semiconductor integrated circuit device at a preceding stage of the cascade connection, and thereafter, a start signal is read at a subsequent stage of the cascade connection. In the cascade connection circuit in which data is read into the preceding-stage semiconductor integrated circuit device until the data is read into the semiconductor integrated circuit device, in each of the cascade-connected circuits, each of the semiconductor integrated circuit devices reads a start signal by inputting an enable signal. A signal reading circuit; and a shift register that sequentially shifts a plurality of flip-flops inside by a start signal from the start signal reading circuit at an edge of a clock signal, and one to two stages before the last stage from the first stage to the last stage of the flip-flop. One of the flip-flops up to the output of the subsequent semiconductor Characterized in that it is outputted as an enable signal to the AND circuit device.
According to the electronic device of the present invention, a start signal is sequentially read into a plurality of cascade-connected semiconductor integrated circuit devices, and a start signal is read into a semiconductor integrated circuit device at a preceding stage of the cascade connection, and then a semiconductor device at a later stage of the cascade connection is read. In an electronic device in which data is read into the preceding-stage semiconductor integrated circuit device until the data is read into the integrated circuit device, each of the semiconductor integrated circuit devices reads a start signal by inputting an enable signal. And a shift register for sequentially shifting a plurality of internal flip-flops at the edge of a clock signal from a start signal from a start signal reading circuit, and from the first stage to the last stage of the flip-flop by one or two stages before the last stage. One of the outputs of the flip-flops is connected to a semiconductor integrated circuit device at the subsequent stage. Characterized in that it is outputted as the enable signal.
The electronic device is used as a display device, and the semiconductor integrated circuit device is a data drive circuit.
The display device is used as a liquid crystal display device.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS. 6 and 7 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, the liquid crystal display module of the liquid crystal display device includes a liquid crystal panel 1, a controller 2, a plurality of scanning drivers 3 and a data driver 40. The start signal STH sent from the controller 2 to the data driver 40 is sent to each data driver 40 in parallel.
[0015]
As shown in FIG. 2, the data-side driver 40 is a circuit for sequentially transferring the start signal STH by cascade connection, in addition to the input terminals 6 and 7 and the input / output circuit 9 shown in FIG. A start signal reading circuit 42 for reading the start signal STH into the shift register 41, an input terminal 43 of an enable signal EN for controlling the start signal reading circuit 42, and an output of the enable signal EN to the data driver 40 at the next stage. And a terminal 44.
[0016]
The shift register 41 has, for example, a 64-stage flip-flop 45 composed of D flip-flops. The clock input terminal (C) of each flip-flop 45 is connected to the input terminal 6 via the input / output circuit 9. The data input terminal (D) of the first-stage flip-flop 45 is connected to the input terminal 7 via the start signal reading circuit 42, and the data input terminal (D) of each of the subsequent flip-flops 45 is connected to the preceding flip-flop. Is connected to the regular output terminal (Q) of the loop 45. The complementary output terminal (Q bar) of each flip-flop 45 is connected to each register of a data register circuit (not shown) provided at a subsequent stage corresponding to each flip-flop 45. The normal output terminal (Q) of the first-stage flip-flop 45 is connected to the output terminal 44. The output from each flip-flop 45 to the data register circuit may be from the regular output terminal (Q) instead of the complementary output terminal (from Q bar). The flip-flop 45, to which the normal output terminal (Q) is connected to the output terminal 44, starts from the next stage instead of the first stage flip-flop 45 unless the enable signal EN and the pulse of the start signal STHA overlap. One or two flip-flops 45 before the last stage may be used.
[0017]
As shown in FIG. 3, the start signal reading circuit 42 has an RS latch 46 and an internal start signal generation circuit 47 that generates an internal start signal STHB based on an output from the RS latch 46. The RS latch 46 has a set terminal (S) connected to the input terminal 7 of the start signal STHA, a reset input terminal (R) connected to the input terminal 43 of the enable signal EN, and a regular output terminal (Q) connected to the internal start signal. The input terminal of the generation circuit 47 is connected. When the start signal STHA and the enable signal EN are input to the RS latch 46, as shown in FIG. 4, the output of the normal output terminal (Q) of the RS latch 46 changes the enable signal EN to the “H” level at time T1. Becomes "L" level, and if "L" level is reached at time T2, "L" level is maintained as it is. Then, when the start signal STHA goes to the “H” level at time T3, it goes to the “H” level, and the “H” level is held until the enable signal EN goes to the “H” level again. When the output from the normal output terminal (Q) of the RS latch 46 is input to the internal start signal generation circuit 47, the output of the internal start signal generation circuit 47 becomes "H" level at time T3 as shown in FIG. At the time T4 of one clock cycle from the time T3, the signal goes to the “L” level, and is output as the internal start signal STHB.
[0018]
Next, the operation of the data side driver 40 in the cascade connection will be described with reference to FIG. The external clock signal CLKA is supplied from the controller 2 to the input terminal 6 of each data side driver 40. The external clock signal CLKA supplied to the input terminal 6 is supplied to the input / output circuit 9, and the clock signal CLKA supplied to the input / output circuit 9 is delayed by a predetermined time td 1 and becomes the internal clock signal CLKB of each flip-flop 45. It is supplied to the data input terminal (D).
[0019]
The enable signal EN is supplied from the controller 2 to the input terminal 43 of the data driver A at the rise to the “H” level at time t0, and the RS latch 46 of the start signal reading circuit 42 of the data driver A is reset. In this state, when the start signal STHA is supplied from the controller 2 to the input terminal 7 of each data driver 40 at the rise to the “H” level at the time t1, the start signal reading circuit of the data driver A is synchronized therewith. The RS latch 46 is set, and the internal start signal STHB is generated by the internal start signal generation circuit 47 of the start signal reading circuit 42 of the data driver A. The internal start signal STHB is supplied to the data input terminal (D) of the first-stage flip-flop 45 of the data driver A, and the internal start signal STHB is sampled at time t3 by the rise of the pulse b 'of the internal clock signal CLKB. Then, each flip-flop 45 of the data side driver A is sequentially transferred, and each flip-flop 45 outputs a control signal for taking in a data signal to a subsequent data register circuit (not shown). Then, in synchronization with the rise of the pulse b 'of the internal clock signal CLKB at the time t3 from the normal output terminal (Q) of the first-stage flip-flop 45 of the data-side driver A, the next-stage data-side driver B is connected to the output terminal 44. Is output.
[0020]
Next, the enable signal EN is supplied to the input terminal 43 of the data driver B at the next stage at the rise to the “H” level at the time t0 ′ delayed by a predetermined time from the time t3. , The RS latch 46 of the start signal reading circuit 42 is reset. In this state, when the start signal STHA is supplied from the controller 2 to the input terminal 7 of each data driver 40 at the rise to the “H” level at time t1 ′, the start signal of the data driver B is read in synchronization with the start signal STHA. The RS latch 46 of the circuit 42 is set, and the internal start signal STHB is generated by the internal start signal generation circuit 47 of the start signal reading circuit 42 of the data driver B. The internal start signal STHB is supplied to the data input terminal (D) of the flip-flop 45 at the first stage of the data side driver B. Then, each flip-flop 45 of the data-side driver B is sequentially transferred, and a control signal for taking in a data signal from each flip-flop 45 of the data-side driver B to a subsequent data register circuit (not shown) is output. Then, in synchronization with the rise of the pulse b 'of the internal clock signal CLKB at the time t3' from the normal output terminal (Q) of the first-stage flip-flop 45 of the data-side driver B, the next-stage data-side driver is connected to the output terminal 44. An enable signal EN to C is output.
[0021]
Similarly, the enable signal EN is supplied to the input terminals 43 of the data-side drivers C, D,..., G and H of the third and subsequent stages, and the internal start signal STHB is changed to the data-side drivers C, D,. G and H flip-flops 45 are sequentially transferred. When the transfer to the data side driver H is completed, the same operation is started by sending the enable signal EN to the data side driver A again.
[0022]
As described above, the enable signal EN for reading and controlling the start signal STHA is supplied to the input terminal 43 of the data driver A, and the input terminals 43 of the data drivers B, C,. , The RS latch 46 of the start signal reading circuit 42 for each of the data side drivers B, C,..., G, H is sequentially reset, and the start signal STHA is reset for each of the data side drivers A, B,. , G, and H sequentially, and sequentially transferred through the flip-flops 45 of the data-side drivers A, B,..., G, and H. Since the start signal STHA is supplied from the controller 2 to the respective data drivers A, B,..., G, H in parallel, the input timing of the internal start signal STHB in the respective data drivers A, B,. .., G, H can normally read the internal start signal STHB at the rising edge of the original reading pulse b ′ of the internal clock signal CLKB. .
[0023]
In the above embodiment, the start signal is read and transferred at the rising edge of the internal clock signal. However, the reading and transfer may be performed at the falling edge or a double edge of the rising edge and the falling edge. In addition, the liquid crystal display device has been described as an example, but the present invention is not limited to this, and the present invention can be applied to a case where a data side driver of another display device is cascaded and a start signal is transferred. Further, the present invention is not limited to a display device, and can be used in a case where a start signal is transferred by cascading semiconductor integrated circuit devices in another electronic device to which data is transferred.
[0024]
【The invention's effect】
As described above, according to the present invention, when a plurality of semiconductor integrated circuit devices are used and a start signal is transferred by cascade connection between the semiconductor integrated circuit devices, an enable signal EN for reading and controlling the start signal is provided in the first stage. A start signal supplied in parallel to each semiconductor integrated circuit device is sequentially read into each semiconductor integrated circuit device by supplying the signal to the semiconductor integrated circuit device and transferring the signal to the next and subsequent semiconductor integrated circuit devices. Therefore, in each semiconductor integrated circuit device, the input timing of the start signal becomes the same condition, and each semiconductor integrated circuit device can normally read the start signal at the rising edge of the original reading pulse of the clock signal, The start signal can be reliably transferred, and a stable operation is guaranteed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a circuit of a liquid crystal display device according to one embodiment of the present invention.
FIG. 2 is a main part circuit diagram of the data-side driver shown in FIG. 1;
FIG. 3 is a circuit diagram showing an example of a start signal reading circuit used in the data driver shown in FIG. 2;
FIG. 4 is a waveform chart illustrating the operation of the start signal reading circuit shown in FIG.
FIG. 5 is a waveform chart for explaining the operation of the data-side driver shown in FIG.
FIG. 6 is a circuit diagram showing a circuit of a conventional liquid crystal display device.
FIG. 7 is a main part circuit diagram of the data side driver shown in FIG. 6;
8 is a waveform chart for explaining the operation of the data-side driver shown in FIG.
[Explanation of symbols]
Reference Signs List 1 liquid crystal panel 6 clock signal input terminal 7 start signal input terminal 9 input / output circuit 40 data side driver 41 shift register 42 start signal reading circuit 43 enable signal input terminal 44 enable signal output terminal 45 flip-flop 46 RS latch 47 internal start Signal generation circuit

Claims (4)

A start signal is sequentially read into a plurality of cascade-connected semiconductor integrated circuit devices, and the start signal is read into a preceding semiconductor integrated circuit device in the cascade connection, and then read into a succeeding semiconductor integrated circuit device in the cascade connection. In the period up to, in the cascade connection circuit in which data is read into the preceding-stage semiconductor integrated circuit device,
Each of the semiconductor integrated circuit devices includes a start signal reading circuit for reading a start signal in response to an input of an enable signal, and a shift that sequentially shifts a start signal from the start signal reading circuit to a plurality of flip-flops inside at a clock signal edge. A cascade, wherein an output of one of the flip-flops from the first stage to the last stage or one to two stages before the last stage of the flip-flop is output as an enable signal to a semiconductor integrated circuit device at a subsequent stage. Connection circuit. A start signal is sequentially read into a plurality of cascade-connected semiconductor integrated circuit devices, and the start signal is read into a preceding semiconductor integrated circuit device in the cascade connection, and then read into a succeeding semiconductor integrated circuit device in the cascade connection. In the electronic device in which data is read into the preceding-stage semiconductor integrated circuit device during the period up to,
Each of the semiconductor integrated circuit devices includes a start signal reading circuit for reading a start signal in response to an input of an enable signal, and a shift that sequentially shifts a start signal from the start signal reading circuit to a plurality of flip-flops inside at a clock signal edge. An output of one of flip-flops from the first stage to one or two stages before the last stage of the flip-flop is output as an enable signal to a semiconductor integrated circuit device at a subsequent stage. apparatus. 3. The electronic device according to claim 2, wherein the device is used as a display device, and the semiconductor integrated circuit device is a data-side drive circuit. The electronic device according to claim 3, wherein the electronic device is used as a liquid crystal display device.

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