JP2004328556A - Pulse signal transmitting circuit and drive circuit using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a delay of a pulse signal supplied to a processing circuit via wiring. <P>SOLUTION: While a switch SW1 is turned on, the terminal potential of wiring L1 is made higher than a reference voltage V1 by an "H" level input of a clock signal and when an output of a comparator 62 reaches an "H" level, an output of an EXOR circuit 63 reaches the "H" level. Then, a switch SW3 is turned on and the terminal potential of the wiring L1 is backed up by the rising side of the clock signal to rapidly reach the "H" level. An output of a delay circuit 64 reaches the "H" level, an output of an EXOR circuit 65 reaches the "H" level, and a switch SW2 is turned on. In such a state, the terminal potential of the wiring L1 becomes lower than a reference potential V2 by an "L" level input of the clock signal and when the output of the comparator 62 reaches an "L" level, the output of the EXOR circuit 63 reaches the "H" level. Then, the switch SW3 is turned on, and the terminal potential of the wiring L1 is backed up with the falling side of the clock signal to rapidly reach the "L" level. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a pulse signal transmission circuit and a driving circuit using the circuit.
[0002]
[Prior art]
Liquid crystal display devices are used for various devices such as personal computers because of their features of thinness, light weight, and low power consumption. Active matrix color liquid crystal display devices, which are particularly advantageous for controlling image quality with high definition, dominate. I have.
[0003]
Hereinafter, a conventional liquid crystal display device described in Patent Document 1 will be described with reference to FIG. This liquid crystal display device includes a liquid crystal panel (LCD panel) 11, a control circuit (hereinafter, referred to as a controller) 12 including a semiconductor integrated circuit device (hereinafter, referred to as an IC), and a plurality of scanning side drive circuits (hereinafter, referred to as an IC). , A scanning side driver) 13 and a data side driving circuit (hereinafter, referred to as a data side driver) 14. Although not shown in detail, the liquid crystal panel 11 has a semiconductor substrate on which a transparent pixel electrode and a thin film transistor (TFT) are arranged, a counter substrate on which one transparent electrode is formed over the entire surface, and these two substrates facing each other. A predetermined voltage is applied to each pixel electrode by controlling a TFT having a switching function, and the transmittance of the liquid crystal is determined by a potential difference between each pixel electrode and a counter substrate electrode. The image is displayed by changing it. On the semiconductor substrate, a data line for transmitting a gradation voltage to be applied to each pixel electrode and a scanning line for transmitting a switching control signal (scanning signal) for the TFT are wired.
[0004]
The controller 12 has an input side connected to a PC (personal computer) 15 and an output side connected to a scanning driver 13 and a data driver 14. The output sides of the scanning driver 13 and the data driver 14 are connected to the scanning lines and the data lines of the liquid crystal panel 11, respectively. The chip size of the scanning driver 13 and the data driver 14 is limited due to manufacturing restrictions. Therefore, the number of outputs corresponding to the scanning lines and data lines that can be output by one IC is also limited, and the size of the liquid crystal panel 11 is large. In this case, it is necessary to arrange a plurality of them on the outer periphery of the liquid crystal panel 11. For example, in the case of a liquid crystal panel of XGA (1024 × 768 pixels) color display, mounting of the drivers 13 and 14 on the module is as follows.
{Circle around (1)} The scanning driver 13 needs to drive 768 gate lines. For example, if it has a driving capability of 192 gates, four drivers are required. You.
{Circle around (2)} The data-side driver 14 needs three data lines for R (red), G (green), and B (blue) in order to display one pixel in color. It is necessary to drive the data lines. For example, when the data lines have a driving capability of 384 lines, eight cascade-connected (A, B,..., H) are arranged on the upper outer periphery of the liquid crystal panel 11 on one side.
[0005]
The image data is transmitted from the PC 15 to the controller 12 of the liquid crystal display module, the clock signal CLK and the like are transmitted from the controller 12 to the scanning driver 13 in parallel to each scanning driver 13, and a start signal STV for vertical synchronization is supplied to the first stage. , And sequentially transferred to the cascaded scanning driver 13 at the next and subsequent stages. In addition, a timing signal such as a clock signal CLK and a data signal DA of a predetermined bit indicating a gradation are sent from the controller 12 to the data side driver 14 in parallel to each data side driver 14, and a start signal STH for horizontal synchronization is sent to the data side driver 14. The data is sent to the data driver A in the first stage, and is sequentially transferred to the data drivers B, C,... Then, a pulse-like scanning signal is sent to each scanning line from the scanning side driver 13, and when the scanning signal applied to the scanning line is at a high level, all the TFTs connected to that scanning line are turned on, The gray scale voltage sent from the driver 14 to the data line is applied to the pixel electrode via the turned-on TFT. Then, when the scanning signal becomes low level and the TFT changes to the off state, the potential difference between the pixel electrode and the counter substrate electrode is held until the next gradation voltage is applied to the pixel electrode. Then, by sequentially transmitting a scanning signal to each scanning line, a predetermined gradation voltage is applied to all the pixel electrodes, and an image can be displayed by rewriting the gradation voltage in a frame cycle.
[0006]
Next, a conventional example of the data-side driver 14 will be described with reference to FIG. For the sake of simplicity, the description will be made assuming that 4 × 1 (R) pixels in the horizontal direction are driven. In the figure, reference numeral 20 denotes a shift register, which has four stages of flip-flops 21 connected in cascade. The data signal output terminal of each flip-flop 21 is connected to the data signal input terminal of the next succeeding flip-flop 21 and is cascaded. The clock input terminal of each flip-flop 21 is connected to the clock signal input terminal 1 via a common line L1. The data signal input terminal of the first stage flip-flop 21 is connected to the start signal input terminal 2, and the data signal output terminal of the last stage flip-flop 21 is connected to the start signal output terminal 3. Further, the data signal output terminal of each flip-flop 21 is connected to each of the four registers 31 of the data register circuit 30 corresponding to each flip-flop 21. Each register 31 has a data signal input terminal connected to the data signal input terminal 4 via a common line L2, and a data signal output terminal corresponding to each register 31 to each latch (not shown) of the latch circuit 40. It is connected. The latch circuit 40 is connected to the latch signal input terminal 5 and has a data signal output terminal connected to the driver circuit 50. The driver circuit 50 includes a level shifter, a D / A converter, and an output amplifier (not shown) corresponding to each flip-flop 21, and a data signal output terminal is connected to the driver output terminal 6 corresponding to each flip-flop 21. Have been.
[0007]
The operation of the data-side driver having the above configuration will be described with reference to FIG. For simplicity of the following description, it is assumed that the number of pixels in the horizontal direction of the liquid crystal display panel is 4 × 1 (R), and the operation is performed by one data-side driver. A clock signal CLK synchronized with the transmission timing of the data signal DA at the terminal 4 is commonly input from the clock signal input terminal 1 to each flip-flop 21 via the common line L1, and the start signal STH starts at the timing of one horizontal drive period. When the signal is input from the signal input terminal 2 to the first-stage flip-flop 21, the start signal STH is read at the rise of the clock signal CLK and transferred to each flip-flop 21, and the data signal output from each flip-flop 21 corresponds to the start signal STH. The data fetch control signals C1, C2, C3, and C4 for fetching the data signal DA are sequentially output to the register 31, and the start signal STH when the data side driver is cascaded from the last flip-flop 21 to the next stage. Is output to the start signal output terminal 3. At the rise of the data fetch control signals C1, C2, C3, and C4 input to the data register circuit 30, the data signals DA are sequentially fetched from the data signal input terminal 4 to the respective registers 31 via the common line L2. From the output terminals R1, R2, R3, R4. The data signal DA fetched by all the registers 31 is latched by the latch circuit 40 in synchronization with the latch signal STB given to the terminal 5 every one horizontal drive period (hereinafter, not shown in FIG. 6). Output to the circuit 50. The driver circuit 50 selects a gradation voltage from a gradation voltage generation circuit (not shown) corresponding to each data signal DA, and outputs the selected gradation voltage from each driver output terminal 6.
[0008]
[Patent Document 1]
Japanese Patent Application No. 2002-153854 (paragraph numbers “0002” to “0005”, FIG. 4)
[Patent Document 2]
Japanese Patent Application Laid-Open No. 10-214061 (paragraph numbers "0003" to "0004", FIGS. 6 and 7)
[0009]
[Problems to be solved by the invention]
By the way, in the above-described liquid crystal display device, when the size of the liquid crystal panel 11 is further increased from XGA to SXGA (1280 × 1024) and UXGA (1600 × 1200) and the number of pixels increases, the number of data-side drivers connected in cascade is increased. For example, if SXGA is set to 8 and UXGA is set to 10, the number of outputs per data-side driver requires 480 outputs, which is larger than the 384 outputs in the output example of XGA. For this reason, the wirings L1 and L2 are connected to the clock input terminal of the flip-flop for 480 outputs and the data signal input terminal of the data register, so that the wiring length becomes longer than the case of 384 outputs, and the clock signal input terminal The clock signal and the data signal, which are rectangular wave pulse signals input to the data signal input terminal 1 and the data signal input terminal 4, are, for example, the wiring L1 at the end of each of the wirings L1 and L2 due to the influence of the wiring resistance and the wiring capacitance. As shown in FIG. 7, the waveform becomes a dull waveform and is delayed. As a result, there is a problem that the setup time and the hold time required for the data-side driver are shortened with an increase in the speed of the clock signal, and there is a possibility that the data acquisition becomes uncertain.
[0010]
Accordingly, an object of the present invention is to provide a pulse signal transmission circuit for transmitting a pulse signal to a processing circuit via a wiring having a wiring resistance and a wiring capacitance, in which the delay of the pulse signal at the wiring end is reduced. It is to be. Another object is to provide a driving circuit using a pulse signal transmission circuit.
[0011]
[Means for Solving the Problems]
A pulse signal transmission circuit according to the present invention, a pulse signal transmission circuit including a wiring through which a pulse signal is transmitted, and an auxiliary circuit for energizing a rise and a fall of the pulse signal at the end of the wiring, wherein the auxiliary circuit is When a pulse signal from the wiring is input and the potential of the input terminal of the auxiliary circuit becomes higher than the reference voltage V1 (<pulse voltage amplitude / 2) at the time of the rise of the pulse signal, the potential of the input terminal is changed to the pulse signal. And when the pulse signal falls and becomes lower than the reference voltage V2 (> pulse voltage amplitude / 2), the potential of the input terminal is applied to the falling side of the pulse signal. And
Further, in the pulse signal transmission circuit according to the present invention, in the pulse signal transmission circuit, the auxiliary circuit is configured such that a pulse signal from the wiring is input to a non-inverting input terminal and a reference voltage V1 is supplied. A second reference power supply to which a reference power supply and a reference voltage V2 are supplied, a first switch that enables a reference voltage V1 to be supplied to an inverting input terminal of the comparator, and a reference voltage V2 to be supplied. A second switch, a third switch that enables the output of the comparator to be supplied to the non-inverting input terminal of the comparator, and an output of the comparator that is input to one input of the two inputs, and outputs a control signal of the third switch. A first EXOR circuit for outputting, an output of the comparator, a first delay circuit for receiving the delayed input to the other input side of the first EXOR circuit, and an output of the first delay circuit. A second EXOR circuit input to one input side of the two inputs, a second delay circuit whose output from the first delay circuit is delayed and input to the other input side of the second EXOR circuit, and an output of the comparator connected to a data input terminal A flip-flop circuit which receives the output of the second EXOR circuit at a clock input terminal and outputs control signals for the first switch and the second switch from the output terminal.
A drive circuit of the present invention is a drive circuit for driving a data line of a liquid crystal panel using the above-described pulse signal transmission circuit.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
The data-side driver according to an embodiment of the present invention described below is used, for example, in a liquid crystal panel for color display of SXGA (1280 × 1024) or UXGA (1600 × 1200), and has a driving capability for 480 data lines. Have. For the sake of simplicity, the description will be made assuming that 4 × 1 (R) pixels in the horizontal direction are driven, and the same components as those in FIG. 5 are denoted by the same reference numerals and description thereof is omitted. 5 in that pulse signal transmission circuits 60 and 70 are provided in addition to the shift register 20, the data register circuit 30, the latch circuit 40, and the driver circuit 50. The pulse signal transmission circuits 60 and 70 are composed of wirings L1 and L2 and auxiliary circuits 61 and 71 provided at the ends of the wirings L1 and L2. Although the data signal input terminal 4 is shown as a single terminal in the figure, it has terminals corresponding to the number of bits of the data signal input in parallel, and is connected to the wiring L2 for the number of bits. I have. For example, when a data signal of 6 bits × R, G, B = 18 bits of 64 gradation display is input in parallel, it has 18 terminals and 18 lines L2. Therefore, at this time, the pulse signal transmission circuit 70 also has 18 auxiliary circuits 71 corresponding to the 18 lines L2.
[0013]
The auxiliary circuits 61 and 71 have the same circuit configuration. Hereinafter, the auxiliary circuit 61 will be representatively described with reference to FIG. In the figure, reference numeral 62 denotes a comparator, and the non-inverting input terminal (+) of the comparator 62 is connected to the end of the wiring L1. The inverting input terminal (-) of the comparator 62 is connected to a reference power supply V1 for supplying a reference voltage V1 (<pulse voltage amplitude / 2) via a first switch SW1 composed of a CMOS transfer gate. Connected to a reference power supply V2 that supplies a reference voltage V2 (> pulse voltage amplitude / 2) via a second switch SW2. An output terminal of the comparator 62 is connected to a non-inverting input terminal of the comparator 62 via a third switch SW3 formed of a CMOS transfer gate, and one of two input terminals of a first EXOR (exclusive OR) circuit 63. And the other input terminal via the first delay circuit 64. The output terminal of the EXOR circuit 63 is connected to the Nch gate of the switch SW3 and the Pch gate via the first inverter INV1. The output terminal of the delay circuit 64 is connected to one input terminal of the two inputs of the second EXOR circuit 65 and the other input terminal via the second delay circuit 66. The output terminal of the EXOR circuit 65 is connected to the clock input terminal CK of the D reflow 67. The data input terminal D of the D pre-flow 67 is connected to the output terminal of the comparator 62. The normal output terminal Q of the D flip-flop 67 is connected to the Pch gate of the switch SW1, the Nch gate of the switch SW2, and the Nch gate of the switch SW1 and the Pch gate of the switch SW2 via the second inverter INV2.
[0014]
The operation of the auxiliary circuit 61 having the above configuration will be described with reference to FIG.
At time t0, the input of the clock signal CLK is at the “L (ground potential)” level, and the terminal of the wiring L1, that is, the potential of the non-inverting input terminal of the comparator 62 is also at the “L” level. At this time, the output of the D pre-flow 67 is at “L” level, the switch SW1 is on and the switch SW2 is off, and the reference voltage V1 is supplied to the inverting input terminal of the comparator 62. The output is at "L" level. At this time, the outputs of the delay circuits 64 and 66 and the EXOR circuits 63 and 65 are at "L" level, and the switch SW3 is off.
[0015]
At time t1, the input of the clock signal CLK goes to the “H (power supply voltage)” level, but since the potential at the end of the wiring L1 is lower than the reference voltage V1, the output of the comparator 62 also remains at the “L” level. . Accordingly, the outputs of the delay circuits 64, 66, the EXOR circuits 63, 65, and the D-flow 67 also remain at the "L" level, the switch SW1 remains on, and the switches SW2, SW3 remain off.
[0016]
At the time t2, the potential at the end of the wiring L1 becomes higher than the reference voltage V1, and the output of the comparator 62 becomes the “H” level. At this time, the output of the delay circuit 64 remains at the "L" level, the output of the EXOR circuit 63 attains the "H" level, the switch SW3 is turned on, and the wiring is performed with only a slight delay from time t1 to t2. The potential at the end of L1 is energized to the rising side of the clock signal and quickly goes to "H" level. At this time, the output of the delay circuit 66 remains at the “L” level, and the output of the EXOR circuit 65 remains at the “L” level, so that the output of the D flip-flop 67 also remains at the “L” level. The switch SW1 remains on and the switch SW2 remains off.
[0017]
At time t3, when the output of the delay circuit 64 goes to “H” level, the output of the EXOR circuit 63 goes to “L” level, and the switch SW3 is turned off. At this time, the output of the delay circuit 66 remains at the "L" level, the output of the EXOR circuit 65 attains the "H" level, the output of the D pre-flow 67 attains the "H" level, and the switch SW1 is turned off. The switch SW2 is turned on.
[0018]
At time t4, when the output of the delay circuit 66 goes to the “H” level, the output of the EXOR circuit 65 goes to the “L” level, but the output of the D flip-flop 67 remains at the “H” level, and the switch SW1 is turned off. The state and the switch SW2 remain on.
[0019]
At time t5, the input of the clock signal CLK becomes “L” level, but since the potential at the end of the wiring L1 is higher than the reference voltage V2, the output of the comparator 62 remains at “H” level. Accordingly, the outputs of the delay circuits 64 and 66 also remain at the “H” level, the EXOR circuits 63 and 65 also remain at the “L” level, and the output of the D flip-flop 67 also remains at the “H” level, and the switch SW2 Remain in the ON state and the switches SW1 and SW3 remain in the OFF state.
[0020]
At time t6, the potential at the terminal end of the wiring L1 becomes lower than the reference voltage V2, and the output of the comparator 62 becomes "L" level. At this time, the output of the delay circuit 64 remains at the "H" level, the output of the EXOR circuit 63 attains the "H" level, the switch SW3 is turned on, and the wiring is performed with only a slight delay from time t5 to t6. The potential at the end of L1 is energized to the falling side of the clock signal and rapidly goes to the "L" level. At this time, the output of the delay circuit 66 remains at the “H” level and the output of the EXOR circuit 65 remains at the “L” level, so that the output of the D flip-flop 67 also remains at the “H” level. The switch SW1 remains off and the switch SW2 remains on.
[0021]
At time t7, when the output of the delay circuit 64 goes to “L” level, the output of the EXOR circuit 63 goes to “L” level, and the switch SW3 is turned off. At this time, the output of the delay circuit 66 remains at the "H" level, the output of the EXOR circuit 65 attains the "H" level, the output of the D pre-flow 67 attains the "L" level, and the switch SW1 is turned on. The switch SW2 is turned off.
[0022]
At time t8, when the output of the delay circuit 66 goes to "L" level, the output of the EXOR circuit 65 goes to "L" level, but the output of the D flip-flop 67 remains at "L" level, and the switch SW1 is turned on. The state and the switch SW2 remain off.
[0023]
The operation of the data-side driver having the above configuration is the same as the operation of the data-side driver shown in FIG. 5, except that the auxiliary circuits 61 and 71 provided at the end portions of the lines L1 and L2 operate as described above. , The description of which will be omitted.
[0024]
As described above, by providing the auxiliary circuits 61 and 71 at the ends of the lines L1 and L2 through which the pulse signals are transmitted, the auxiliary circuits 61 and 71 are provided at the time of rising of the pulse signals input to the lines L1 and L2. When the potential of the input terminal of the line 71 becomes higher than the reference voltage V1, the potential at the end of the wiring L1 is energized to the rising side of the pulse signal and rapidly goes to the "H" level, and when the pulse signal falls, the reference voltage V2 When the potential becomes lower, the potential at the end of the line L1 is energized to the falling side of the pulse signal and quickly becomes the "L" level, and the processing circuit (the flip-flop 21) connected to the end of the lines L1 and L2 with a small delay. , The register 31) is supplied with a pulse signal.
[0025]
In the above embodiment, the example in which the pulse signal transmission circuit is used for the data driver of the liquid crystal display device has been described. However, the present invention is not limited to this. Any device having a processing circuit supplied via the terminal can be used. Also, in the data side driver, an example has been described in which the register of the data register circuit corresponds to each flip-flop with one output, but a plurality of outputs, for example, three outputs of R, G, and B may be used. .
[0026]
【The invention's effect】
According to the present invention, by providing the auxiliary circuit at the end of the wiring through which the pulse signal is transmitted, the rising and falling of the pulse signal at the end of the wiring can be energized, and the pulse signal with a small delay is supplied to the processing circuit. And a high-speed operation of the clock signal in the driver circuit can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a data side driver of a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of an auxiliary circuit used in the data-side driver shown in FIG.
FIG. 3 is a waveform chart for explaining the operation of the auxiliary circuit shown in FIG. 2;
FIG. 4 is a block diagram illustrating a configuration of a conventional liquid crystal display device.
5 is a circuit diagram of a conventional data-side driver used in the liquid crystal display device shown in FIG.
FIG. 6 is a waveform chart for explaining the operation of the data-side driver shown in FIG.
FIG. 7 is a waveform diagram of a clock signal at the end of a wiring L1 when the data-side driver shown in FIG. 5 has multiple outputs.
[Explanation of symbols]
Reference Signs List 20 shift register 21 flip-flop 30 data register circuit 31 register 60, 70 pulse signal transmission circuit 61, 71 auxiliary circuit 62 comparator 63 first EXOR circuit 64 first delay circuit 65 second EXOR circuit 66 second delay circuit 67 D flip-flop L1, L2 Wiring V1 First reference voltage source V2 Second reference voltage source SW1 First switch SW2 Second switch SW3 Third switch

Claims (3)

A pulse signal transmission circuit having a wiring through which a pulse signal is transmitted, and an auxiliary circuit that energizes the rising and falling of the pulse signal at the end of the wiring,
The auxiliary circuit receives a pulse signal from a wiring and, when the pulse signal rises and the potential of the input terminal of the auxiliary circuit becomes higher than a reference voltage V1 (<pulse voltage amplitude / 2), The potential is applied to the rising side of the pulse signal. When the potential of the input terminal becomes lower than the reference voltage V2 (> pulse voltage amplitude / 2) at the time of the falling of the pulse signal, the potential of the input terminal is applied to the falling side of the pulse signal. A pulse signal transmission circuit. The auxiliary circuit includes a comparator to which a pulse signal from the wiring is input to a non-inverting input terminal, a first reference power supply to which a reference voltage V1 is supplied and a second reference power supply to which a reference voltage V2 is supplied, A first switch enabling the reference voltage V1 to be supplied to the inverting input terminal and a second switch enabling the reference voltage V2 to be supplied to the inverting input terminal; and the output of the comparator is supplied to the non-inverting input terminal of the comparator. A first EXOR circuit that receives the output of the comparator as one input of two inputs and outputs a control signal of the third switch, and a third input that outputs the output of the comparator to the other input of the first EXOR circuit. A first delay circuit which is input with a delay to
A second EXOR circuit in which the output of the first delay circuit is input to one input side of the two inputs, a second delay circuit in which the output of the first delay circuit is delayed and input to another input side of the second EXOR circuit, and a comparator And a flip-flop circuit which receives the output of the second EXOR circuit at a data input terminal, receives the output of a second EXOR circuit at a clock input terminal, and outputs control signals for the first switch and the second switch from the output terminal. The pulse signal transmission circuit according to claim 1, wherein A driving circuit for driving a data line of a liquid crystal panel using the pulse signal transmission circuit according to claim 1.

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